bridge.hh revision 12823:ba630bc7a36d
1/* 2 * Copyright (c) 2011-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 * Steve Reinhardt 42 * Andreas Hansson 43 */ 44 45/** 46 * @file 47 * Declaration of a memory-mapped bridge that connects a master 48 * and a slave through a request and response queue. 49 */ 50 51#ifndef __MEM_BRIDGE_HH__ 52#define __MEM_BRIDGE_HH__ 53 54#include <deque> 55 56#include "base/types.hh" 57#include "mem/mem_object.hh" 58#include "params/Bridge.hh" 59 60/** 61 * A bridge is used to interface two different crossbars (or in general a 62 * memory-mapped master and slave), with buffering for requests and 63 * responses. The bridge has a fixed delay for packets passing through 64 * it and responds to a fixed set of address ranges. 65 * 66 * The bridge comprises a slave port and a master port, that buffer 67 * outgoing responses and requests respectively. Buffer space is 68 * reserved when a request arrives, also reserving response space 69 * before forwarding the request. If there is no space present, then 70 * the bridge will delay accepting the packet until space becomes 71 * available. 72 */ 73class Bridge : public MemObject 74{ 75 protected: 76 77 /** 78 * A deferred packet stores a packet along with its scheduled 79 * transmission time 80 */ 81 class DeferredPacket 82 { 83 84 public: 85 86 const Tick tick; 87 const PacketPtr pkt; 88 89 DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt) 90 { } 91 }; 92 93 // Forward declaration to allow the slave port to have a pointer 94 class BridgeMasterPort; 95 96 /** 97 * The port on the side that receives requests and sends 98 * responses. The slave port has a set of address ranges that it 99 * is responsible for. The slave port also has a buffer for the 100 * responses not yet sent. 101 */ 102 class BridgeSlavePort : public SlavePort 103 { 104 105 private: 106 107 /** The bridge to which this port belongs. */ 108 Bridge& bridge; 109 110 /** 111 * Master port on the other side of the bridge. 112 */ 113 BridgeMasterPort& masterPort; 114 115 /** Minimum request delay though this bridge. */ 116 const Cycles delay; 117 118 /** Address ranges to pass through the bridge */ 119 const AddrRangeList ranges; 120 121 /** 122 * Response packet queue. Response packets are held in this 123 * queue for a specified delay to model the processing delay 124 * of the bridge. We use a deque as we need to iterate over 125 * the items for functional accesses. 126 */ 127 std::deque<DeferredPacket> transmitList; 128 129 /** Counter to track the outstanding responses. */ 130 unsigned int outstandingResponses; 131 132 /** If we should send a retry when space becomes available. */ 133 bool retryReq; 134 135 /** Max queue size for reserved responses. */ 136 unsigned int respQueueLimit; 137 138 /** 139 * Upstream caches need this packet until true is returned, so 140 * hold it for deletion until a subsequent call 141 */ 142 std::unique_ptr<Packet> pendingDelete; 143 144 /** 145 * Is this side blocked from accepting new response packets. 146 * 147 * @return true if the reserved space has reached the set limit 148 */ 149 bool respQueueFull() const; 150 151 /** 152 * Handle send event, scheduled when the packet at the head of 153 * the response queue is ready to transmit (for timing 154 * accesses only). 155 */ 156 void trySendTiming(); 157 158 /** Send event for the response queue. */ 159 EventFunctionWrapper sendEvent; 160 161 public: 162 163 /** 164 * Constructor for the BridgeSlavePort. 165 * 166 * @param _name the port name including the owner 167 * @param _bridge the structural owner 168 * @param _masterPort the master port on the other side of the bridge 169 * @param _delay the delay in cycles from receiving to sending 170 * @param _resp_limit the size of the response queue 171 * @param _ranges a number of address ranges to forward 172 */ 173 BridgeSlavePort(const std::string& _name, Bridge& _bridge, 174 BridgeMasterPort& _masterPort, Cycles _delay, 175 int _resp_limit, std::vector<AddrRange> _ranges); 176 177 /** 178 * Queue a response packet to be sent out later and also schedule 179 * a send if necessary. 180 * 181 * @param pkt a response to send out after a delay 182 * @param when tick when response packet should be sent 183 */ 184 void schedTimingResp(PacketPtr pkt, Tick when); 185 186 /** 187 * Retry any stalled request that we have failed to accept at 188 * an earlier point in time. This call will do nothing if no 189 * request is waiting. 190 */ 191 void retryStalledReq(); 192 193 protected: 194 195 /** When receiving a timing request from the peer port, 196 pass it to the bridge. */ 197 bool recvTimingReq(PacketPtr pkt); 198 199 /** When receiving a retry request from the peer port, 200 pass it to the bridge. */ 201 void recvRespRetry(); 202 203 /** When receiving a Atomic requestfrom the peer port, 204 pass it to the bridge. */ 205 Tick recvAtomic(PacketPtr pkt); 206 207 /** When receiving a Functional request from the peer port, 208 pass it to the bridge. */ 209 void recvFunctional(PacketPtr pkt); 210 211 /** When receiving a address range request the peer port, 212 pass it to the bridge. */ 213 AddrRangeList getAddrRanges() const; 214 }; 215 216 217 /** 218 * Port on the side that forwards requests and receives 219 * responses. The master port has a buffer for the requests not 220 * yet sent. 221 */ 222 class BridgeMasterPort : public MasterPort 223 { 224 225 private: 226 227 /** The bridge to which this port belongs. */ 228 Bridge& bridge; 229 230 /** 231 * The slave port on the other side of the bridge. 232 */ 233 BridgeSlavePort& slavePort; 234 235 /** Minimum delay though this bridge. */ 236 const Cycles delay; 237 238 /** 239 * Request packet queue. Request packets are held in this 240 * queue for a specified delay to model the processing delay 241 * of the bridge. We use a deque as we need to iterate over 242 * the items for functional accesses. 243 */ 244 std::deque<DeferredPacket> transmitList; 245 246 /** Max queue size for request packets */ 247 const unsigned int reqQueueLimit; 248 249 /** 250 * Handle send event, scheduled when the packet at the head of 251 * the outbound queue is ready to transmit (for timing 252 * accesses only). 253 */ 254 void trySendTiming(); 255 256 /** Send event for the request queue. */ 257 EventFunctionWrapper sendEvent; 258 259 public: 260 261 /** 262 * Constructor for the BridgeMasterPort. 263 * 264 * @param _name the port name including the owner 265 * @param _bridge the structural owner 266 * @param _slavePort the slave port on the other side of the bridge 267 * @param _delay the delay in cycles from receiving to sending 268 * @param _req_limit the size of the request queue 269 */ 270 BridgeMasterPort(const std::string& _name, Bridge& _bridge, 271 BridgeSlavePort& _slavePort, Cycles _delay, 272 int _req_limit); 273 274 /** 275 * Is this side blocked from accepting new request packets. 276 * 277 * @return true if the occupied space has reached the set limit 278 */ 279 bool reqQueueFull() const; 280 281 /** 282 * Queue a request packet to be sent out later and also schedule 283 * a send if necessary. 284 * 285 * @param pkt a request to send out after a delay 286 * @param when tick when response packet should be sent 287 */ 288 void schedTimingReq(PacketPtr pkt, Tick when); 289 290 /** 291 * Check a functional request against the packets in our 292 * request queue. 293 * 294 * @param pkt packet to check against 295 * 296 * @return true if we find a match 297 */ 298 bool trySatisfyFunctional(PacketPtr pkt); 299 300 protected: 301 302 /** When receiving a timing request from the peer port, 303 pass it to the bridge. */ 304 bool recvTimingResp(PacketPtr pkt); 305 306 /** When receiving a retry request from the peer port, 307 pass it to the bridge. */ 308 void recvReqRetry(); 309 }; 310 311 /** Slave port of the bridge. */ 312 BridgeSlavePort slavePort; 313 314 /** Master port of the bridge. */ 315 BridgeMasterPort masterPort; 316 317 public: 318 319 virtual BaseMasterPort& getMasterPort(const std::string& if_name, 320 PortID idx = InvalidPortID); 321 virtual BaseSlavePort& getSlavePort(const std::string& if_name, 322 PortID idx = InvalidPortID); 323 324 virtual void init(); 325 326 typedef BridgeParams Params; 327 328 Bridge(Params *p); 329}; 330 331#endif //__MEM_BRIDGE_HH__ 332