bridge.hh revision 10713:eddb533708cb 
1/*
2 * Copyright (c) 2011-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 *          Steve Reinhardt
42 *          Andreas Hansson
43 */
44
45/**
46 * @file
47 * Declaration of a memory-mapped bridge that connects a master
48 * and a slave through a request and response queue.
49 */
50
51#ifndef __MEM_BRIDGE_HH__
52#define __MEM_BRIDGE_HH__
53
54#include <deque>
55
56#include "base/types.hh"
57#include "mem/mem_object.hh"
58#include "params/Bridge.hh"
59
60/**
61 * A bridge is used to interface two different crossbars (or in general a
62 * memory-mapped master and slave), with buffering for requests and
63 * responses. The bridge has a fixed delay for packets passing through
64 * it and responds to a fixed set of address ranges.
65 *
66 * The bridge comprises a slave port and a master port, that buffer
67 * outgoing responses and requests respectively. Buffer space is
68 * reserved when a request arrives, also reserving response space
69 * before forwarding the request. If there is no space present, then
70 * the bridge will delay accepting the packet until space becomes
71 * available.
72 */
73class Bridge : public MemObject
74{
75  protected:
76
77    /**
78     * A deferred packet stores a packet along with its scheduled
79     * transmission time
80     */
81    class DeferredPacket
82    {
83
84      public:
85
86        const Tick tick;
87        const PacketPtr pkt;
88
89        DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt)
90        { }
91    };
92
93    // Forward declaration to allow the slave port to have a pointer
94    class BridgeMasterPort;
95
96    /**
97     * The port on the side that receives requests and sends
98     * responses. The slave port has a set of address ranges that it
99     * is responsible for. The slave port also has a buffer for the
100     * responses not yet sent.
101     */
102    class BridgeSlavePort : public SlavePort
103    {
104
105      private:
106
107        /** The bridge to which this port belongs. */
108        Bridge& bridge;
109
110        /**
111         * Master port on the other side of the bridge.
112         */
113        BridgeMasterPort& masterPort;
114
115        /** Minimum request delay though this bridge. */
116        const Cycles delay;
117
118        /** Address ranges to pass through the bridge */
119        const AddrRangeList ranges;
120
121        /**
122         * Response packet queue. Response packets are held in this
123         * queue for a specified delay to model the processing delay
124         * of the bridge. We use a deque as we need to iterate over
125         * the items for functional accesses.
126         */
127        std::deque<DeferredPacket> transmitList;
128
129        /** Counter to track the outstanding responses. */
130        unsigned int outstandingResponses;
131
132        /** If we should send a retry when space becomes available. */
133        bool retryReq;
134
135        /** Max queue size for reserved responses. */
136        unsigned int respQueueLimit;
137
138        /**
139         * Is this side blocked from accepting new response packets.
140         *
141         * @return true if the reserved space has reached the set limit
142         */
143        bool respQueueFull() const;
144
145        /**
146         * Handle send event, scheduled when the packet at the head of
147         * the response queue is ready to transmit (for timing
148         * accesses only).
149         */
150        void trySendTiming();
151
152        /** Send event for the response queue. */
153        EventWrapper<BridgeSlavePort,
154                     &BridgeSlavePort::trySendTiming> sendEvent;
155
156      public:
157
158        /**
159         * Constructor for the BridgeSlavePort.
160         *
161         * @param _name the port name including the owner
162         * @param _bridge the structural owner
163         * @param _masterPort the master port on the other side of the bridge
164         * @param _delay the delay in cycles from receiving to sending
165         * @param _resp_limit the size of the response queue
166         * @param _ranges a number of address ranges to forward
167         */
168        BridgeSlavePort(const std::string& _name, Bridge& _bridge,
169                        BridgeMasterPort& _masterPort, Cycles _delay,
170                        int _resp_limit, std::vector<AddrRange> _ranges);
171
172        /**
173         * Queue a response packet to be sent out later and also schedule
174         * a send if necessary.
175         *
176         * @param pkt a response to send out after a delay
177         * @param when tick when response packet should be sent
178         */
179        void schedTimingResp(PacketPtr pkt, Tick when);
180
181        /**
182         * Retry any stalled request that we have failed to accept at
183         * an earlier point in time. This call will do nothing if no
184         * request is waiting.
185         */
186        void retryStalledReq();
187
188      protected:
189
190        /** When receiving a timing request from the peer port,
191            pass it to the bridge. */
192        bool recvTimingReq(PacketPtr pkt);
193
194        /** When receiving a retry request from the peer port,
195            pass it to the bridge. */
196        void recvRespRetry();
197
198        /** When receiving a Atomic requestfrom the peer port,
199            pass it to the bridge. */
200        Tick recvAtomic(PacketPtr pkt);
201
202        /** When receiving a Functional request from the peer port,
203            pass it to the bridge. */
204        void recvFunctional(PacketPtr pkt);
205
206        /** When receiving a address range request the peer port,
207            pass it to the bridge. */
208        AddrRangeList getAddrRanges() const;
209    };
210
211
212    /**
213     * Port on the side that forwards requests and receives
214     * responses. The master port has a buffer for the requests not
215     * yet sent.
216     */
217    class BridgeMasterPort : public MasterPort
218    {
219
220      private:
221
222        /** The bridge to which this port belongs. */
223        Bridge& bridge;
224
225        /**
226         * The slave port on the other side of the bridge.
227         */
228        BridgeSlavePort& slavePort;
229
230        /** Minimum delay though this bridge. */
231        const Cycles delay;
232
233        /**
234         * Request packet queue. Request packets are held in this
235         * queue for a specified delay to model the processing delay
236         * of the bridge.  We use a deque as we need to iterate over
237         * the items for functional accesses.
238         */
239        std::deque<DeferredPacket> transmitList;
240
241        /** Max queue size for request packets */
242        const unsigned int reqQueueLimit;
243
244        /**
245         * Handle send event, scheduled when the packet at the head of
246         * the outbound queue is ready to transmit (for timing
247         * accesses only).
248         */
249        void trySendTiming();
250
251        /** Send event for the request queue. */
252        EventWrapper<BridgeMasterPort,
253                     &BridgeMasterPort::trySendTiming> sendEvent;
254
255      public:
256
257        /**
258         * Constructor for the BridgeMasterPort.
259         *
260         * @param _name the port name including the owner
261         * @param _bridge the structural owner
262         * @param _slavePort the slave port on the other side of the bridge
263         * @param _delay the delay in cycles from receiving to sending
264         * @param _req_limit the size of the request queue
265         */
266        BridgeMasterPort(const std::string& _name, Bridge& _bridge,
267                         BridgeSlavePort& _slavePort, Cycles _delay,
268                         int _req_limit);
269
270        /**
271         * Is this side blocked from accepting new request packets.
272         *
273         * @return true if the occupied space has reached the set limit
274         */
275        bool reqQueueFull() const;
276
277        /**
278         * Queue a request packet to be sent out later and also schedule
279         * a send if necessary.
280         *
281         * @param pkt a request to send out after a delay
282         * @param when tick when response packet should be sent
283         */
284        void schedTimingReq(PacketPtr pkt, Tick when);
285
286        /**
287         * Check a functional request against the packets in our
288         * request queue.
289         *
290         * @param pkt packet to check against
291         *
292         * @return true if we find a match
293         */
294        bool checkFunctional(PacketPtr pkt);
295
296      protected:
297
298        /** When receiving a timing request from the peer port,
299            pass it to the bridge. */
300        bool recvTimingResp(PacketPtr pkt);
301
302        /** When receiving a retry request from the peer port,
303            pass it to the bridge. */
304        void recvReqRetry();
305    };
306
307    /** Slave port of the bridge. */
308    BridgeSlavePort slavePort;
309
310    /** Master port of the bridge. */
311    BridgeMasterPort masterPort;
312
313  public:
314
315    virtual BaseMasterPort& getMasterPort(const std::string& if_name,
316                                          PortID idx = InvalidPortID);
317    virtual BaseSlavePort& getSlavePort(const std::string& if_name,
318                                        PortID idx = InvalidPortID);
319
320    virtual void init();
321
322    typedef BridgeParams Params;
323
324    Bridge(Params *p);
325};
326
327#endif //__MEM_BRIDGE_HH__
328