SConscript revision 14296:dafc66b0212f
18706Sandreas.hansson@arm.com# -*- mode:python -*-
28706Sandreas.hansson@arm.com#
38706Sandreas.hansson@arm.com# Copyright (c) 2018 ARM Limited
48706Sandreas.hansson@arm.com# All rights reserved
58706Sandreas.hansson@arm.com#
68706Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall
78706Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual
88706Sandreas.hansson@arm.com# property including but not limited to intellectual property relating
98706Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software
108706Sandreas.hansson@arm.com# licensed hereunder.  You may use the software subject to the license
118706Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated
128706Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software,
135369Ssaidi@eecs.umich.edu# modified or unmodified, in source code or in binary form.
143005Sstever@eecs.umich.edu#
153005Sstever@eecs.umich.edu# Copyright (c) 2006 The Regents of The University of Michigan
163005Sstever@eecs.umich.edu# All rights reserved.
173005Sstever@eecs.umich.edu#
183005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without
193005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are
203005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright
213005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer;
223005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright
233005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the
243005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution;
253005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its
263005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from
273005Sstever@eecs.umich.edu# this software without specific prior written permission.
283005Sstever@eecs.umich.edu#
293005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
303005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
313005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
323005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
333005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
343005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
353005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
363005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
373005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
383005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
393005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
403005Sstever@eecs.umich.edu#
412710SN/A# Authors: Nathan Binkert
422710SN/A
433005Sstever@eecs.umich.eduImport('*')
442889SN/A
456654Snate@binkert.orgSimObject('CommMonitor.py')
466654Snate@binkert.orgSource('comm_monitor.cc')
476654Snate@binkert.org
486654Snate@binkert.orgSimObject('AbstractMemory.py')
496654Snate@binkert.orgSimObject('AddrMapper.py')
502667SN/ASimObject('Bridge.py')
516654Snate@binkert.orgSimObject('DRAMCtrl.py')
526654Snate@binkert.orgSimObject('ExternalMaster.py')
536654Snate@binkert.orgSimObject('ExternalSlave.py')
545457Ssaidi@eecs.umich.eduSimObject('MemObject.py')
556654Snate@binkert.orgSimObject('SimpleMemory.py')
568169SLisa.Hsu@amd.comSimObject('XBar.py')
578169SLisa.Hsu@amd.comSimObject('HMCController.py')
588169SLisa.Hsu@amd.comSimObject('SerialLink.py')
596654Snate@binkert.orgSimObject('MemDelay.py')
603395Shsul@eecs.umich.edu
616981SLisa.Hsu@amd.comSource('abstract_mem.cc')
623448Shsul@eecs.umich.eduSource('addr_mapper.cc')
635369Ssaidi@eecs.umich.eduSource('bridge.cc')
643394Shsul@eecs.umich.eduSource('coherent_xbar.cc')
653444Sktlim@umich.eduSource('drampower.cc')
663444Sktlim@umich.eduSource('dram_ctrl.cc')
673444Sktlim@umich.eduSource('external_master.cc')
683444Sktlim@umich.eduSource('external_slave.cc')
692424SN/ASource('noncoherent_xbar.cc')
702957SN/ASource('packet.cc')
712957SN/ASource('port.cc')
723323Shsul@eecs.umich.eduSource('packet_queue.cc')
733005Sstever@eecs.umich.eduSource('port_proxy.cc')
747787SAli.Saidi@ARM.comSource('physical.cc')
757787SAli.Saidi@ARM.comSource('secure_port_proxy.cc')
765514SMichael.Adler@intel.comSource('simple_mem.cc')
772957SN/ASource('snoop_filter.cc')
785514SMichael.Adler@intel.comSource('stack_dist_calc.cc')
795514SMichael.Adler@intel.comSource('tport.cc')
805514SMichael.Adler@intel.comSource('xbar.cc')
815514SMichael.Adler@intel.comSource('hmc_controller.cc')
828467Snilay@cs.wisc.eduSource('serial_link.cc')
833444Sktlim@umich.eduSource('mem_delay.cc')
842957SN/A
858482Snilay@cs.wisc.eduif env['TARGET_ISA'] != 'null':
868482Snilay@cs.wisc.edu    Source('fs_translating_port_proxy.cc')
878482Snilay@cs.wisc.edu    Source('se_translating_port_proxy.cc')
888482Snilay@cs.wisc.edu    Source('page_table.cc')
898467Snilay@cs.wisc.edu
902957SN/Aif env['HAVE_DRAMSIM']:
912957SN/A    SimObject('DRAMSim2.py')
922957SN/A    Source('dramsim2_wrapper.cc')
932957SN/A    Source('dramsim2.cc')
942957SN/A
952957SN/ASimObject('MemChecker.py')
968167SLisa.Hsu@amd.comSource('mem_checker.cc')
978167SLisa.Hsu@amd.comSource('mem_checker_monitor.cc')
988167SLisa.Hsu@amd.com
995369Ssaidi@eecs.umich.eduDebugFlag('AddrRanges')
1008167SLisa.Hsu@amd.comDebugFlag('BaseXBar')
1018167SLisa.Hsu@amd.comDebugFlag('CoherentXBar')
1028167SLisa.Hsu@amd.comDebugFlag('NoncoherentXBar')
1038167SLisa.Hsu@amd.comDebugFlag('SnoopFilter')
1048167SLisa.Hsu@amd.comCompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar',
1058167SLisa.Hsu@amd.com                      'SnoopFilter'])
1068167SLisa.Hsu@amd.com
1078168SLisa.Hsu@amd.comDebugFlag('Bridge')
1088168SLisa.Hsu@amd.comDebugFlag('CommMonitor')
1098168SLisa.Hsu@amd.comDebugFlag('DRAM')
1108168SLisa.Hsu@amd.comDebugFlag('DRAMPower')
1118167SLisa.Hsu@amd.comDebugFlag('DRAMState')
1128167SLisa.Hsu@amd.comDebugFlag('ExternalPort')
1138168SLisa.Hsu@amd.comDebugFlag('LLSC')
1145369Ssaidi@eecs.umich.eduDebugFlag('MMU')
1155369Ssaidi@eecs.umich.eduDebugFlag('MemoryAccess')
1165369Ssaidi@eecs.umich.eduDebugFlag('PacketQueue')
1175369Ssaidi@eecs.umich.eduDebugFlag('StackDist')
1185369Ssaidi@eecs.umich.eduDebugFlag("DRAMSim2")
1198167SLisa.Hsu@amd.comDebugFlag('HMCController')
1205369Ssaidi@eecs.umich.eduDebugFlag('SerialLink')
1215369Ssaidi@eecs.umich.edu
1222801SN/ADebugFlag("MemChecker")
1232801SN/ADebugFlag("MemCheckerMonitor")
1245514SMichael.Adler@intel.comDebugFlag("QOS")
1255514SMichael.Adler@intel.com