SConscript revision 14183:8116c413222e
1# -*- mode:python -*- 2# 3# Copyright (c) 2018 ARM Limited 4# All rights reserved 5# 6# The license below extends only to copyright in the software and shall 7# not be construed as granting a license to any other intellectual 8# property including but not limited to intellectual property relating 9# to a hardware implementation of the functionality of the software 10# licensed hereunder. You may use the software subject to the license 11# terms below provided that you ensure that this notice is replicated 12# unmodified and in its entirety in all distributions of the software, 13# modified or unmodified, in source code or in binary form. 14# 15# Copyright (c) 2006 The Regents of The University of Michigan 16# All rights reserved. 17# 18# Redistribution and use in source and binary forms, with or without 19# modification, are permitted provided that the following conditions are 20# met: redistributions of source code must retain the above copyright 21# notice, this list of conditions and the following disclaimer; 22# redistributions in binary form must reproduce the above copyright 23# notice, this list of conditions and the following disclaimer in the 24# documentation and/or other materials provided with the distribution; 25# neither the name of the copyright holders nor the names of its 26# contributors may be used to endorse or promote products derived from 27# this software without specific prior written permission. 28# 29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40# 41# Authors: Nathan Binkert 42 43Import('*') 44 45SimObject('CommMonitor.py') 46Source('comm_monitor.cc') 47 48SimObject('AbstractMemory.py') 49SimObject('AddrMapper.py') 50SimObject('Bridge.py') 51SimObject('DRAMCtrl.py') 52SimObject('ExternalMaster.py') 53SimObject('ExternalSlave.py') 54SimObject('MemObject.py') 55SimObject('SimpleMemory.py') 56SimObject('XBar.py') 57SimObject('HMCController.py') 58SimObject('SerialLink.py') 59SimObject('MemDelay.py') 60 61Source('abstract_mem.cc') 62Source('addr_mapper.cc') 63Source('atomic_protocol.cc') 64Source('bridge.cc') 65Source('coherent_xbar.cc') 66Source('drampower.cc') 67Source('dram_ctrl.cc') 68Source('external_master.cc') 69Source('external_slave.cc') 70Source('functional_protocol.cc') 71Source('mem_object.cc') 72Source('mport.cc') 73Source('noncoherent_xbar.cc') 74Source('packet.cc') 75Source('port.cc') 76Source('packet_queue.cc') 77Source('port_proxy.cc') 78Source('physical.cc') 79Source('secure_port_proxy.cc') 80Source('timing_protocol.cc') 81Source('simple_mem.cc') 82Source('snoop_filter.cc') 83Source('stack_dist_calc.cc') 84Source('tport.cc') 85Source('xbar.cc') 86Source('hmc_controller.cc') 87Source('serial_link.cc') 88Source('mem_delay.cc') 89 90if env['TARGET_ISA'] != 'null': 91 Source('fs_translating_port_proxy.cc') 92 Source('se_translating_port_proxy.cc') 93 Source('page_table.cc') 94 95if env['HAVE_DRAMSIM']: 96 SimObject('DRAMSim2.py') 97 Source('dramsim2_wrapper.cc') 98 Source('dramsim2.cc') 99 100SimObject('MemChecker.py') 101Source('mem_checker.cc') 102Source('mem_checker_monitor.cc') 103 104DebugFlag('AddrRanges') 105DebugFlag('BaseXBar') 106DebugFlag('CoherentXBar') 107DebugFlag('NoncoherentXBar') 108DebugFlag('SnoopFilter') 109CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar', 110 'SnoopFilter']) 111 112DebugFlag('Bridge') 113DebugFlag('CommMonitor') 114DebugFlag('DRAM') 115DebugFlag('DRAMPower') 116DebugFlag('DRAMState') 117DebugFlag('ExternalPort') 118DebugFlag('LLSC') 119DebugFlag('MMU') 120DebugFlag('MemoryAccess') 121DebugFlag('PacketQueue') 122DebugFlag('StackDist') 123DebugFlag("DRAMSim2") 124DebugFlag('HMCController') 125DebugFlag('SerialLink') 126 127DebugFlag("MemChecker") 128DebugFlag("MemCheckerMonitor") 129DebugFlag("QOS") 130