SConscript revision 10996:d48fda705f4d
1# -*- mode:python -*- 2 3# Copyright (c) 2006 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright 9# notice, this list of conditions and the following disclaimer; 10# redistributions in binary form must reproduce the above copyright 11# notice, this list of conditions and the following disclaimer in the 12# documentation and/or other materials provided with the distribution; 13# neither the name of the copyright holders nor the names of its 14# contributors may be used to endorse or promote products derived from 15# this software without specific prior written permission. 16# 17# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 20# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 21# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28# 29# Authors: Nathan Binkert 30 31Import('*') 32 33SimObject('CommMonitor.py') 34Source('comm_monitor.cc') 35 36SimObject('AbstractMemory.py') 37SimObject('AddrMapper.py') 38SimObject('Bridge.py') 39SimObject('DRAMCtrl.py') 40SimObject('ExternalMaster.py') 41SimObject('ExternalSlave.py') 42SimObject('MemObject.py') 43SimObject('SimpleMemory.py') 44SimObject('XBar.py') 45 46Source('abstract_mem.cc') 47Source('addr_mapper.cc') 48Source('bridge.cc') 49Source('coherent_xbar.cc') 50Source('drampower.cc') 51Source('dram_ctrl.cc') 52Source('external_master.cc') 53Source('external_slave.cc') 54Source('mem_object.cc') 55Source('mport.cc') 56Source('noncoherent_xbar.cc') 57Source('packet.cc') 58Source('port.cc') 59Source('packet_queue.cc') 60Source('port_proxy.cc') 61Source('physical.cc') 62Source('simple_mem.cc') 63Source('snoop_filter.cc') 64Source('stack_dist_calc.cc') 65Source('tport.cc') 66Source('xbar.cc') 67 68if env['TARGET_ISA'] != 'null': 69 Source('fs_translating_port_proxy.cc') 70 Source('se_translating_port_proxy.cc') 71 Source('page_table.cc') 72if env['TARGET_ISA'] == 'x86': 73 Source('multi_level_page_table.cc') 74 75if env['HAVE_DRAMSIM']: 76 SimObject('DRAMSim2.py') 77 Source('dramsim2_wrapper.cc') 78 Source('dramsim2.cc') 79 80SimObject('MemChecker.py') 81Source('mem_checker.cc') 82Source('mem_checker_monitor.cc') 83 84DebugFlag('AddrRanges') 85DebugFlag('BaseXBar') 86DebugFlag('CoherentXBar') 87DebugFlag('NoncoherentXBar') 88DebugFlag('SnoopFilter') 89CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar', 90 'SnoopFilter']) 91 92DebugFlag('Bridge') 93DebugFlag('CommMonitor') 94DebugFlag('DRAM') 95DebugFlag('DRAMPower') 96DebugFlag('DRAMState') 97DebugFlag('ExternalPort') 98DebugFlag('LLSC') 99DebugFlag('MMU') 100DebugFlag('MemoryAccess') 101DebugFlag('PacketQueue') 102DebugFlag('StackDist') 103DebugFlag("DRAMSim2") 104 105DebugFlag("MemChecker") 106DebugFlag("MemCheckerMonitor") 107