SConscript revision 14007
1955SN/A# -*- mode:python -*-
2955SN/A#
31762SN/A# Copyright (c) 2018 ARM Limited
4955SN/A# All rights reserved
5955SN/A#
6955SN/A# The license below extends only to copyright in the software and shall
7955SN/A# not be construed as granting a license to any other intellectual
8955SN/A# property including but not limited to intellectual property relating
9955SN/A# to a hardware implementation of the functionality of the software
10955SN/A# licensed hereunder.  You may use the software subject to the license
11955SN/A# terms below provided that you ensure that this notice is replicated
12955SN/A# unmodified and in its entirety in all distributions of the software,
13955SN/A# modified or unmodified, in source code or in binary form.
14955SN/A#
15955SN/A# Copyright (c) 2006 The Regents of The University of Michigan
16955SN/A# All rights reserved.
17955SN/A#
18955SN/A# Redistribution and use in source and binary forms, with or without
19955SN/A# modification, are permitted provided that the following conditions are
20955SN/A# met: redistributions of source code must retain the above copyright
21955SN/A# notice, this list of conditions and the following disclaimer;
22955SN/A# redistributions in binary form must reproduce the above copyright
23955SN/A# notice, this list of conditions and the following disclaimer in the
24955SN/A# documentation and/or other materials provided with the distribution;
25955SN/A# neither the name of the copyright holders nor the names of its
26955SN/A# contributors may be used to endorse or promote products derived from
27955SN/A# this software without specific prior written permission.
282665Ssaidi@eecs.umich.edu#
292665Ssaidi@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30955SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31955SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32955SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33955SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34955SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
352632Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
362632Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
372632Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
382632Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39955SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
402632Sstever@eecs.umich.edu#
412632Sstever@eecs.umich.edu# Authors: Nathan Binkert
422761Sstever@eecs.umich.edu
432632Sstever@eecs.umich.eduImport('*')
442632Sstever@eecs.umich.edu
452632Sstever@eecs.umich.eduSimObject('CommMonitor.py')
462761Sstever@eecs.umich.eduSource('comm_monitor.cc')
472761Sstever@eecs.umich.edu
482761Sstever@eecs.umich.eduSimObject('AbstractMemory.py')
492632Sstever@eecs.umich.eduSimObject('AddrMapper.py')
502632Sstever@eecs.umich.eduSimObject('Bridge.py')
512761Sstever@eecs.umich.eduSimObject('DRAMCtrl.py')
522761Sstever@eecs.umich.eduSimObject('ExternalMaster.py')
532761Sstever@eecs.umich.eduSimObject('ExternalSlave.py')
542761Sstever@eecs.umich.eduSimObject('MemObject.py')
552761Sstever@eecs.umich.eduSimObject('SimpleMemory.py')
562632Sstever@eecs.umich.eduSimObject('XBar.py')
572632Sstever@eecs.umich.eduSimObject('HMCController.py')
582632Sstever@eecs.umich.eduSimObject('SerialLink.py')
592632Sstever@eecs.umich.eduSimObject('MemDelay.py')
602632Sstever@eecs.umich.edu
612632Sstever@eecs.umich.eduSource('abstract_mem.cc')
622632Sstever@eecs.umich.eduSource('addr_mapper.cc')
63955SN/ASource('bridge.cc')
64955SN/ASource('coherent_xbar.cc')
65955SN/ASource('drampower.cc')
66955SN/ASource('dram_ctrl.cc')
67955SN/ASource('external_master.cc')
683918Ssaidi@eecs.umich.eduSource('external_slave.cc')
694202Sbinkertn@umich.eduSource('mem_object.cc')
704678Snate@binkert.orgSource('mport.cc')
71955SN/ASource('noncoherent_xbar.cc')
722656Sstever@eecs.umich.eduSource('packet.cc')
732656Sstever@eecs.umich.eduSource('port.cc')
742656Sstever@eecs.umich.eduSource('packet_queue.cc')
752656Sstever@eecs.umich.eduSource('port_proxy.cc')
762656Sstever@eecs.umich.eduSource('physical.cc')
772656Sstever@eecs.umich.eduSource('secure_port_proxy.cc')
782656Sstever@eecs.umich.eduSource('simple_mem.cc')
792653Sstever@eecs.umich.eduSource('snoop_filter.cc')
802653Sstever@eecs.umich.eduSource('stack_dist_calc.cc')
812653Sstever@eecs.umich.eduSource('tport.cc')
822653Sstever@eecs.umich.eduSource('xbar.cc')
832653Sstever@eecs.umich.eduSource('hmc_controller.cc')
842653Sstever@eecs.umich.eduSource('serial_link.cc')
852653Sstever@eecs.umich.eduSource('mem_delay.cc')
862653Sstever@eecs.umich.edu
872653Sstever@eecs.umich.eduif env['TARGET_ISA'] != 'null':
882653Sstever@eecs.umich.edu    Source('fs_translating_port_proxy.cc')
892653Sstever@eecs.umich.edu    Source('se_translating_port_proxy.cc')
901852SN/A    Source('page_table.cc')
91955SN/A
92955SN/Aif env['HAVE_DRAMSIM']:
93955SN/A    SimObject('DRAMSim2.py')
943717Sstever@eecs.umich.edu    Source('dramsim2_wrapper.cc')
953716Sstever@eecs.umich.edu    Source('dramsim2.cc')
96955SN/A
971533SN/ASimObject('MemChecker.py')
983716Sstever@eecs.umich.eduSource('mem_checker.cc')
991533SN/ASource('mem_checker_monitor.cc')
1004678Snate@binkert.org
1014678Snate@binkert.orgDebugFlag('AddrRanges')
1024678Snate@binkert.orgDebugFlag('BaseXBar')
1034678Snate@binkert.orgDebugFlag('CoherentXBar')
1044678Snate@binkert.orgDebugFlag('NoncoherentXBar')
1054678Snate@binkert.orgDebugFlag('SnoopFilter')
1064678Snate@binkert.orgCompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar',
1074678Snate@binkert.org                      'SnoopFilter'])
1084678Snate@binkert.org
1094678Snate@binkert.orgDebugFlag('Bridge')
1104678Snate@binkert.orgDebugFlag('CommMonitor')
1114678Snate@binkert.orgDebugFlag('DRAM')
1124678Snate@binkert.orgDebugFlag('DRAMPower')
1134678Snate@binkert.orgDebugFlag('DRAMState')
1144678Snate@binkert.orgDebugFlag('ExternalPort')
1154678Snate@binkert.orgDebugFlag('LLSC')
1164678Snate@binkert.orgDebugFlag('MMU')
1174678Snate@binkert.orgDebugFlag('MemoryAccess')
1184678Snate@binkert.orgDebugFlag('PacketQueue')
1194678Snate@binkert.orgDebugFlag('StackDist')
1204678Snate@binkert.orgDebugFlag("DRAMSim2")
1214678Snate@binkert.orgDebugFlag('HMCController')
1224678Snate@binkert.orgDebugFlag('SerialLink')
1234678Snate@binkert.org
1244678Snate@binkert.orgDebugFlag("MemChecker")
1254678Snate@binkert.orgDebugFlag("MemCheckerMonitor")
1264678Snate@binkert.orgDebugFlag("QOS")
1274678Snate@binkert.org