SConscript revision 14007
11689SN/A# -*- mode:python -*- 210333Smitch.hayenga@arm.com# 39920Syasuko.eckert@amd.com# Copyright (c) 2018 ARM Limited 47944SGiacomo.Gabrielli@arm.com# All rights reserved 57944SGiacomo.Gabrielli@arm.com# 67944SGiacomo.Gabrielli@arm.com# The license below extends only to copyright in the software and shall 77944SGiacomo.Gabrielli@arm.com# not be construed as granting a license to any other intellectual 87944SGiacomo.Gabrielli@arm.com# property including but not limited to intellectual property relating 97944SGiacomo.Gabrielli@arm.com# to a hardware implementation of the functionality of the software 107944SGiacomo.Gabrielli@arm.com# licensed hereunder. You may use the software subject to the license 117944SGiacomo.Gabrielli@arm.com# terms below provided that you ensure that this notice is replicated 127944SGiacomo.Gabrielli@arm.com# unmodified and in its entirety in all distributions of the software, 137944SGiacomo.Gabrielli@arm.com# modified or unmodified, in source code or in binary form. 147944SGiacomo.Gabrielli@arm.com# 152326SN/A# Copyright (c) 2006 The Regents of The University of Michigan 161689SN/A# All rights reserved. 171689SN/A# 181689SN/A# Redistribution and use in source and binary forms, with or without 191689SN/A# modification, are permitted provided that the following conditions are 201689SN/A# met: redistributions of source code must retain the above copyright 211689SN/A# notice, this list of conditions and the following disclaimer; 221689SN/A# redistributions in binary form must reproduce the above copyright 231689SN/A# notice, this list of conditions and the following disclaimer in the 241689SN/A# documentation and/or other materials provided with the distribution; 251689SN/A# neither the name of the copyright holders nor the names of its 261689SN/A# contributors may be used to endorse or promote products derived from 271689SN/A# this software without specific prior written permission. 281689SN/A# 291689SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu# 412665Ssaidi@eecs.umich.edu# Authors: Nathan Binkert 421689SN/A 431689SN/AImport('*') 442292SN/A 452292SN/ASimObject('CommMonitor.py') 461060SN/ASource('comm_monitor.cc') 471060SN/A 481061SN/ASimObject('AbstractMemory.py') 491060SN/ASimObject('AddrMapper.py') 501061SN/ASimObject('Bridge.py') 511060SN/ASimObject('DRAMCtrl.py') 521062SN/ASimObject('ExternalMaster.py') 538229Snate@binkert.orgSimObject('ExternalSlave.py') 548229Snate@binkert.orgSimObject('MemObject.py') 558229Snate@binkert.orgSimObject('SimpleMemory.py') 568229Snate@binkert.orgSimObject('XBar.py') 577813Ssteve.reinhardt@amd.comSimObject('HMCController.py') 5813561Snikos.nikoleris@arm.comSimObject('SerialLink.py') 595529Snate@binkert.orgSimObject('MemDelay.py') 601060SN/A 618737Skoansin.tan@gmail.comSource('abstract_mem.cc') 622292SN/ASource('addr_mapper.cc') 632292SN/ASource('bridge.cc') 642292SN/ASource('coherent_xbar.cc') 651060SN/ASource('drampower.cc') 661689SN/ASource('dram_ctrl.cc') 671689SN/ASource('external_master.cc') 681689SN/ASource('external_slave.cc') 691689SN/ASource('mem_object.cc') 701060SN/ASource('mport.cc') 711060SN/ASource('noncoherent_xbar.cc') 721060SN/ASource('packet.cc') 732292SN/ASource('port.cc') 742292SN/ASource('packet_queue.cc') 752292SN/ASource('port_proxy.cc') 762292SN/ASource('physical.cc') 772292SN/ASource('secure_port_proxy.cc') 782292SN/ASource('simple_mem.cc') 792292SN/ASource('snoop_filter.cc') 802292SN/ASource('stack_dist_calc.cc') 811060SN/ASource('tport.cc') 821061SN/ASource('xbar.cc') 831060SN/ASource('hmc_controller.cc') 841060SN/ASource('serial_link.cc') 851060SN/ASource('mem_delay.cc') 861060SN/A 872733Sktlim@umich.eduif env['TARGET_ISA'] != 'null': 881061SN/A Source('fs_translating_port_proxy.cc') 891060SN/A Source('se_translating_port_proxy.cc') 902292SN/A Source('page_table.cc') 911061SN/A 921061SN/Aif env['HAVE_DRAMSIM']: 931061SN/A SimObject('DRAMSim2.py') 941060SN/A Source('dramsim2_wrapper.cc') 952292SN/A Source('dramsim2.cc') 961061SN/A 971060SN/ASimObject('MemChecker.py') 982292SN/ASource('mem_checker.cc') 992292SN/ASource('mem_checker_monitor.cc') 1002292SN/A 1012292SN/ADebugFlag('AddrRanges') 1022292SN/ADebugFlag('BaseXBar') 1032292SN/ADebugFlag('CoherentXBar') 1042292SN/ADebugFlag('NoncoherentXBar') 1052292SN/ADebugFlag('SnoopFilter') 1062292SN/ACompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar', 1072292SN/A 'SnoopFilter']) 1082292SN/A 1092292SN/ADebugFlag('Bridge') 1102348SN/ADebugFlag('CommMonitor') 1112348SN/ADebugFlag('DRAM') 1122348SN/ADebugFlag('DRAMPower') 1132326SN/ADebugFlag('DRAMState') 1142326SN/ADebugFlag('ExternalPort') 1152292SN/ADebugFlag('LLSC') 1162292SN/ADebugFlag('MMU') 11713429Srekai.gonzalezalberquilla@arm.comDebugFlag('MemoryAccess') 1182292SN/ADebugFlag('PacketQueue') 1192292SN/ADebugFlag('StackDist') 1202292SN/ADebugFlag("DRAMSim2") 1215336Shines@cs.fsu.eduDebugFlag('HMCController') 1222326SN/ADebugFlag('SerialLink') 1231060SN/A 1241060SN/ADebugFlag("MemChecker") 1252292SN/ADebugFlag("MemCheckerMonitor") 1265529Snate@binkert.orgDebugFlag("QOS") 1271061SN/A