SConscript revision 11185 
14202Sbinkertn@umich.edu# -*- mode:python -*-
24202Sbinkertn@umich.edu
34202Sbinkertn@umich.edu# Copyright (c) 2006 The Regents of The University of Michigan
44202Sbinkertn@umich.edu# All rights reserved.
54202Sbinkertn@umich.edu#
64202Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without
74202Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are
84202Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright
94202Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer;
104202Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright
114202Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the
124202Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution;
134202Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its
144202Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from
154202Sbinkertn@umich.edu# this software without specific prior written permission.
164202Sbinkertn@umich.edu#
174202Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
184202Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
194202Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
204202Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
214202Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
224202Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
234202Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
244202Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
254202Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
264202Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
274202Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
284202Sbinkertn@umich.edu#
294202Sbinkertn@umich.edu# Authors: Nathan Binkert
304202Sbinkertn@umich.edu
314202Sbinkertn@umich.eduImport('*')
324202Sbinkertn@umich.edu
334486Sbinkertn@umich.eduSimObject('CommMonitor.py')
344486Sbinkertn@umich.eduSource('comm_monitor.cc')
356165Ssanchezd@stanford.edu
366168Snate@binkert.orgSimObject('AbstractMemory.py')
374202Sbinkertn@umich.eduSimObject('AddrMapper.py')
384202Sbinkertn@umich.eduSimObject('Bridge.py')
394202Sbinkertn@umich.eduSimObject('DRAMCtrl.py')
404202Sbinkertn@umich.eduSimObject('ExternalMaster.py')
414202Sbinkertn@umich.eduSimObject('ExternalSlave.py')
424202Sbinkertn@umich.eduSimObject('MemObject.py')
435650Sgblack@eecs.umich.eduSimObject('SimpleMemory.py')
446168Snate@binkert.orgSimObject('XBar.py')
457768SAli.Saidi@ARM.comSimObject('HMCController.py')
467768SAli.Saidi@ARM.comSimObject('SerialLink.py')
477768SAli.Saidi@ARM.com
487768SAli.Saidi@ARM.comSource('abstract_mem.cc')
497768SAli.Saidi@ARM.comSource('addr_mapper.cc')
504202Sbinkertn@umich.eduSource('bridge.cc')
514202Sbinkertn@umich.eduSource('coherent_xbar.cc')
527768SAli.Saidi@ARM.comSource('drampower.cc')
534202Sbinkertn@umich.eduSource('dram_ctrl.cc')
544202Sbinkertn@umich.eduSource('external_master.cc')
555192Ssaidi@eecs.umich.eduSource('external_slave.cc')
568335Snate@binkert.orgSource('mem_object.cc')
578335Snate@binkert.orgSource('mport.cc')
588335Snate@binkert.orgSource('noncoherent_xbar.cc')
598335Snate@binkert.orgSource('packet.cc')
608335Snate@binkert.orgSource('port.cc')
618335Snate@binkert.orgSource('packet_queue.cc')
627780Snilay@cs.wisc.eduSource('port_proxy.cc')
638335Snate@binkert.orgSource('physical.cc')
648335Snate@binkert.orgSource('simple_mem.cc')
658335Snate@binkert.orgSource('snoop_filter.cc')
668335Snate@binkert.orgSource('stack_dist_calc.cc')
678335Snate@binkert.orgSource('tport.cc')
688335Snate@binkert.orgSource('xbar.cc')
698335Snate@binkert.orgSource('hmc_controller.cc')
708335Snate@binkert.orgSource('serial_link.cc')
718335Snate@binkert.org
728335Snate@binkert.orgif env['TARGET_ISA'] != 'null':
738335Snate@binkert.org    Source('fs_translating_port_proxy.cc')
747780Snilay@cs.wisc.edu    Source('se_translating_port_proxy.cc')
757780Snilay@cs.wisc.edu    Source('page_table.cc')
767780Snilay@cs.wisc.eduif env['TARGET_ISA'] == 'x86':
778161SBrad.Beckmann@amd.com    Source('multi_level_page_table.cc')
78
79if env['HAVE_DRAMSIM']:
80    SimObject('DRAMSim2.py')
81    Source('dramsim2_wrapper.cc')
82    Source('dramsim2.cc')
83
84SimObject('MemChecker.py')
85Source('mem_checker.cc')
86Source('mem_checker_monitor.cc')
87
88DebugFlag('AddrRanges')
89DebugFlag('BaseXBar')
90DebugFlag('CoherentXBar')
91DebugFlag('NoncoherentXBar')
92DebugFlag('SnoopFilter')
93CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar',
94                      'SnoopFilter'])
95
96DebugFlag('Bridge')
97DebugFlag('CommMonitor')
98DebugFlag('DRAM')
99DebugFlag('DRAMPower')
100DebugFlag('DRAMState')
101DebugFlag('ExternalPort')
102DebugFlag('LLSC')
103DebugFlag('MMU')
104DebugFlag('MemoryAccess')
105DebugFlag('PacketQueue')
106DebugFlag('StackDist')
107DebugFlag("DRAMSim2")
108DebugFlag('HMCController')
109DebugFlag('SerialLink')
110
111DebugFlag("MemChecker")
112DebugFlag("MemCheckerMonitor")
113