SConscript revision 10614 
19397Sandreas.hansson@arm.com# -*- mode:python -*-
29397Sandreas.hansson@arm.com
39397Sandreas.hansson@arm.com# Copyright (c) 2006 The Regents of The University of Michigan
49397Sandreas.hansson@arm.com# All rights reserved.
59397Sandreas.hansson@arm.com#
69397Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without
79397Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are
89397Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright
99397Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer;
109397Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright
119397Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the
129397Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution;
139397Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its
149397Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from
159397Sandreas.hansson@arm.com# this software without specific prior written permission.
169397Sandreas.hansson@arm.com#
179397Sandreas.hansson@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
189397Sandreas.hansson@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
199397Sandreas.hansson@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
209397Sandreas.hansson@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
219397Sandreas.hansson@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
229397Sandreas.hansson@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
239397Sandreas.hansson@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
249397Sandreas.hansson@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
259397Sandreas.hansson@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
269397Sandreas.hansson@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
279397Sandreas.hansson@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
289397Sandreas.hansson@arm.com#
299397Sandreas.hansson@arm.com# Authors: Nathan Binkert
309397Sandreas.hansson@arm.com
319397Sandreas.hansson@arm.comImport('*')
329397Sandreas.hansson@arm.com
339397Sandreas.hansson@arm.com# Only build the communication if we have support for protobuf as the
349397Sandreas.hansson@arm.com# tracing relies on it
359397Sandreas.hansson@arm.comif env['HAVE_PROTOBUF']:
369397Sandreas.hansson@arm.com    SimObject('CommMonitor.py')
379397Sandreas.hansson@arm.com    Source('comm_monitor.cc')
389397Sandreas.hansson@arm.com
399397Sandreas.hansson@arm.comSimObject('AbstractMemory.py')
409397Sandreas.hansson@arm.comSimObject('AddrMapper.py')
419397Sandreas.hansson@arm.comSimObject('Bridge.py')
429397Sandreas.hansson@arm.comSimObject('DRAMCtrl.py')
439397Sandreas.hansson@arm.comSimObject('ExternalMaster.py')
449398Sandreas.hansson@arm.comSimObject('ExternalSlave.py')
459397Sandreas.hansson@arm.comSimObject('MemObject.py')
46SimObject('SimpleMemory.py')
47SimObject('StackDistCalc.py')
48SimObject('XBar.py')
49
50Source('abstract_mem.cc')
51Source('addr_mapper.cc')
52Source('bridge.cc')
53Source('coherent_xbar.cc')
54Source('drampower.cc')
55Source('dram_ctrl.cc')
56Source('external_master.cc')
57Source('external_slave.cc')
58Source('mem_object.cc')
59Source('mport.cc')
60Source('noncoherent_xbar.cc')
61Source('packet.cc')
62Source('port.cc')
63Source('packet_queue.cc')
64Source('port_proxy.cc')
65Source('physical.cc')
66Source('simple_mem.cc')
67Source('snoop_filter.cc')
68Source('stack_dist_calc.cc')
69Source('tport.cc')
70Source('xbar.cc')
71
72if env['TARGET_ISA'] != 'null':
73    Source('fs_translating_port_proxy.cc')
74    Source('se_translating_port_proxy.cc')
75    Source('page_table.cc')
76if env['TARGET_ISA'] == 'x86':
77    Source('multi_level_page_table.cc')
78
79if env['HAVE_DRAMSIM']:
80    SimObject('DRAMSim2.py')
81    Source('dramsim2_wrapper.cc')
82    Source('dramsim2.cc')
83
84SimObject('MemChecker.py')
85Source('mem_checker.cc')
86Source('mem_checker_monitor.cc')
87
88DebugFlag('AddrRanges')
89DebugFlag('BaseXBar')
90DebugFlag('CoherentXBar')
91DebugFlag('NoncoherentXBar')
92DebugFlag('SnoopFilter')
93CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar',
94                      'SnoopFilter'])
95
96DebugFlag('Bridge')
97DebugFlag('CommMonitor')
98DebugFlag('DRAM')
99DebugFlag('DRAMPower')
100DebugFlag('DRAMState')
101DebugFlag('ExternalPort')
102DebugFlag('LLSC')
103DebugFlag('MMU')
104DebugFlag('MemoryAccess')
105DebugFlag('PacketQueue')
106DebugFlag('StackDist')
107DebugFlag("DRAMSim2")
108
109DebugFlag("MemChecker")
110DebugFlag("MemCheckerMonitor")
111