pc.cc revision 5643
13985Sgblack@eecs.umich.edu/*
22632Sstever@eecs.umich.edu * Copyright (c) 2008 The Regents of The University of Michigan
32632Sstever@eecs.umich.edu * All rights reserved.
42632Sstever@eecs.umich.edu *
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62632Sstever@eecs.umich.edu * modification, are permitted provided that the following conditions are
72632Sstever@eecs.umich.edu * met: redistributions of source code must retain the above copyright
82632Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer;
92632Sstever@eecs.umich.edu * redistributions in binary form must reproduce the above copyright
102632Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the
112632Sstever@eecs.umich.edu * documentation and/or other materials provided with the distribution;
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132632Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from
142632Sstever@eecs.umich.edu * this software without specific prior written permission.
152632Sstever@eecs.umich.edu *
162632Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172632Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182632Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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252632Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262632Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272632Sstever@eecs.umich.edu *
282632Sstever@eecs.umich.edu * Authors: Gabe Black
292632Sstever@eecs.umich.edu */
302022SN/A
312022SN/A/** @file
322022SN/A * Implementation of PC platform.
332022SN/A */
342022SN/A
352022SN/A#include <deque>
362022SN/A#include <string>
372516SN/A#include <vector>
382022SN/A
392022SN/A#include "arch/x86/x86_traits.hh"
402022SN/A#include "cpu/intr_control.hh"
412224SN/A#include "dev/terminal.hh"
422224SN/A#include "dev/x86/i82094aa.hh"
434253Sgblack@eecs.umich.edu#include "dev/x86/i8254.hh"
442224SN/A#include "dev/x86/pc.hh"
452224SN/A#include "dev/x86/south_bridge.hh"
462224SN/A#include "sim/system.hh"
472022SN/A
482224SN/Ausing namespace std;
492224SN/Ausing namespace TheISA;
502022SN/A
512516SN/APc::Pc(const Params *p)
522516SN/A    : Platform(p), system(p->system)
532516SN/A{
542516SN/A    southBridge = NULL;
552516SN/A    // set the back pointer from the system to myself
562516SN/A    system->platform = this;
572516SN/A}
582516SN/A
594253Sgblack@eecs.umich.eduvoid
602516SN/APc::init()
612516SN/A{
622516SN/A    assert(southBridge);
632516SN/A
642516SN/A    /*
652516SN/A     * Initialize the timer.
662516SN/A     */
672516SN/A    I8254 & timer = *southBridge->pit;
682516SN/A    //Timer 0, mode 2, no bcd, 16 bit count
692516SN/A    timer.writeControl(0x34);
702516SN/A    //Timer 0, latch command
712516SN/A    timer.writeControl(0x00);
722944Sgblack@eecs.umich.edu    //Write a 16 bit count of 0
732516SN/A    timer.writeCounter(0, 0);
742944Sgblack@eecs.umich.edu    timer.writeCounter(0, 0);
752944Sgblack@eecs.umich.edu
762516SN/A    /*
772516SN/A     * Initialize the I/O APIC.
782516SN/A     */
794253Sgblack@eecs.umich.edu    I82094AA & ioApic = *southBridge->ioApic;
802516SN/A    I82094AA::RedirTableEntry entry = 0;
812516SN/A    entry.deliveryMode = 0x7;
822516SN/A    entry.vector = 0x20;
833273Sgblack@eecs.umich.edu    ioApic.writeReg(0x10, entry.bottomDW);
842516SN/A    ioApic.writeReg(0x11, entry.topDW);
852516SN/A}
862516SN/A
872516SN/ATick
882516SN/APc::intrFrequency()
892516SN/A{
902516SN/A    panic("Need implementation\n");
912516SN/A    M5_DUMMY_RETURN
922516SN/A}
932516SN/A
944253Sgblack@eecs.umich.eduvoid
952516SN/APc::postConsoleInt()
962516SN/A{
972516SN/A    warn_once("Don't know what interrupt to post for console.\n");
983273Sgblack@eecs.umich.edu    //panic("Need implementation\n");
992516SN/A}
1002516SN/A
1012516SN/Avoid
1022516SN/APc::clearConsoleInt()
1032516SN/A{
1042516SN/A    warn_once("Don't know what interrupt to clear for console.\n");
1052516SN/A    //panic("Need implementation\n");
1062516SN/A}
1072516SN/A
1082516SN/Avoid
1092516SN/APc::postPciInt(int line)
1104253Sgblack@eecs.umich.edu{
1113273Sgblack@eecs.umich.edu    panic("Need implementation\n");
1122516SN/A}
1132516SN/A
1142516SN/Avoid
1152516SN/APc::clearPciInt(int line)
1162516SN/A{
1172516SN/A    panic("Need implementation\n");
1182516SN/A}
1192516SN/A
1202022SN/AAddr
1212022SN/APc::pciToDma(Addr pciAddr) const
1222022SN/A{
1232944Sgblack@eecs.umich.edu    panic("Need implementation\n");
1242944Sgblack@eecs.umich.edu    M5_DUMMY_RETURN
1252944Sgblack@eecs.umich.edu}
1262944Sgblack@eecs.umich.edu
1272944Sgblack@eecs.umich.edu
1282944Sgblack@eecs.umich.eduAddr
1292944Sgblack@eecs.umich.eduPc::calcConfigAddr(int bus, int dev, int func)
1307741Sgblack@eecs.umich.edu{
1317741Sgblack@eecs.umich.edu    assert(func < 8);
1327741Sgblack@eecs.umich.edu    assert(dev < 32);
1337741Sgblack@eecs.umich.edu    assert(bus == 0);
1347741Sgblack@eecs.umich.edu    return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11));
1357741Sgblack@eecs.umich.edu}
1367741Sgblack@eecs.umich.edu
1377741Sgblack@eecs.umich.eduPc *
1387741Sgblack@eecs.umich.eduPcParams::create()
1397741Sgblack@eecs.umich.edu{
1407741Sgblack@eecs.umich.edu    return new Pc(this);
1417741Sgblack@eecs.umich.edu}
1427741Sgblack@eecs.umich.edu