pc.cc revision 5643
1/* 2 * Copyright (c) 2008 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31/** @file 32 * Implementation of PC platform. 33 */ 34 35#include <deque> 36#include <string> 37#include <vector> 38 39#include "arch/x86/x86_traits.hh" 40#include "cpu/intr_control.hh" 41#include "dev/terminal.hh" 42#include "dev/x86/i82094aa.hh" 43#include "dev/x86/i8254.hh" 44#include "dev/x86/pc.hh" 45#include "dev/x86/south_bridge.hh" 46#include "sim/system.hh" 47 48using namespace std; 49using namespace TheISA; 50 51Pc::Pc(const Params *p) 52 : Platform(p), system(p->system) 53{ 54 southBridge = NULL; 55 // set the back pointer from the system to myself 56 system->platform = this; 57} 58 59void 60Pc::init() 61{ 62 assert(southBridge); 63 64 /* 65 * Initialize the timer. 66 */ 67 I8254 & timer = *southBridge->pit; 68 //Timer 0, mode 2, no bcd, 16 bit count 69 timer.writeControl(0x34); 70 //Timer 0, latch command 71 timer.writeControl(0x00); 72 //Write a 16 bit count of 0 73 timer.writeCounter(0, 0); 74 timer.writeCounter(0, 0); 75 76 /* 77 * Initialize the I/O APIC. 78 */ 79 I82094AA & ioApic = *southBridge->ioApic; 80 I82094AA::RedirTableEntry entry = 0; 81 entry.deliveryMode = 0x7; 82 entry.vector = 0x20; 83 ioApic.writeReg(0x10, entry.bottomDW); 84 ioApic.writeReg(0x11, entry.topDW); 85} 86 87Tick 88Pc::intrFrequency() 89{ 90 panic("Need implementation\n"); 91 M5_DUMMY_RETURN 92} 93 94void 95Pc::postConsoleInt() 96{ 97 warn_once("Don't know what interrupt to post for console.\n"); 98 //panic("Need implementation\n"); 99} 100 101void 102Pc::clearConsoleInt() 103{ 104 warn_once("Don't know what interrupt to clear for console.\n"); 105 //panic("Need implementation\n"); 106} 107 108void 109Pc::postPciInt(int line) 110{ 111 panic("Need implementation\n"); 112} 113 114void 115Pc::clearPciInt(int line) 116{ 117 panic("Need implementation\n"); 118} 119 120Addr 121Pc::pciToDma(Addr pciAddr) const 122{ 123 panic("Need implementation\n"); 124 M5_DUMMY_RETURN 125} 126 127 128Addr 129Pc::calcConfigAddr(int bus, int dev, int func) 130{ 131 assert(func < 8); 132 assert(dev < 32); 133 assert(bus == 0); 134 return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11)); 135} 136 137Pc * 138PcParams::create() 139{ 140 return new Pc(this); 141} 142