ide_ctrl.hh revision 864
12SN/A/* 212109SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2003 The Regents of The University of Michigan 39920Syasuko.eckert@amd.com * All rights reserved. 48733Sgeoffrey.blake@arm.com * 58733Sgeoffrey.blake@arm.com * Redistribution and use in source and binary forms, with or without 68733Sgeoffrey.blake@arm.com * modification, are permitted provided that the following conditions are 78733Sgeoffrey.blake@arm.com * met: redistributions of source code must retain the above copyright 88733Sgeoffrey.blake@arm.com * notice, this list of conditions and the following disclaimer; 98733Sgeoffrey.blake@arm.com * redistributions in binary form must reproduce the above copyright 108733Sgeoffrey.blake@arm.com * notice, this list of conditions and the following disclaimer in the 118733Sgeoffrey.blake@arm.com * documentation and/or other materials provided with the distribution; 128733Sgeoffrey.blake@arm.com * neither the name of the copyright holders nor the names of its 138733Sgeoffrey.blake@arm.com * contributors may be used to endorse or promote products derived from 148733Sgeoffrey.blake@arm.com * this software without specific prior written permission. 152188SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A */ 282SN/A 292SN/A/** @file 302SN/A * Simple PCI IDE controller with bus mastering capability and UDMA 312SN/A * modeled after controller in the Intel PIIX4 chip 322SN/A */ 332SN/A 342SN/A#ifndef __IDE_CTRL_HH__ 352SN/A#define __IDE_CTRL_HH__ 362SN/A 372SN/A#include "dev/pcidev.hh" 382SN/A#include "dev/pcireg.h" 392SN/A#include "dev/io_device.hh" 402665SN/A 412665SN/A#define BMIC0 0x0 // Bus master IDE command register 422665SN/A#define BMIS0 0x2 // Bus master IDE status register 432SN/A#define BMIDTP0 0x4 // Bus master IDE descriptor table pointer register 442SN/A#define BMIC1 0x8 // Bus master IDE command register 452683Sktlim@umich.edu#define BMIS1 0xa // Bus master IDE status register 462683Sktlim@umich.edu#define BMIDTP1 0xc // Bus master IDE descriptor table pointer register 472SN/A 489020Sgblack@eecs.umich.edu// Bus master IDE command register bit fields 4912406Sgabeblack@google.com#define RWCON 0x08 // Bus master read/write control 506313Sgblack@eecs.umich.edu#define SSBM 0x01 // Start/stop bus master 512190SN/A 526329Sgblack@eecs.umich.edu// Bus master IDE status register bit fields 536316Sgblack@eecs.umich.edu#define DMA1CAP 0x40 // Drive 1 DMA capable 546216Snate@binkert.org#define DMA0CAP 0x20 // Drive 0 DMA capable 556658Snate@binkert.org#define IDEINTS 0x04 // IDE Interrupt Status 562680SN/A#define IDEDMAE 0x02 // IDE DMA error 572683Sktlim@umich.edu#define BMIDEA 0x01 // Bus master IDE active 589920Syasuko.eckert@amd.com 598232Snate@binkert.org// IDE Command byte fields 608232Snate@binkert.org#define IDE_SELECT_OFFSET (6) 6112109SRekai.GonzalezAlberquilla@arm.com#define IDE_SELECT_DEV_BIT 0x10 628777Sgblack@eecs.umich.edu 632395SN/A#define IDE_FEATURE_OFFSET IDE_ERROR_OFFSET 642190SN/A#define IDE_COMMAND_OFFSET IDE_STATUS_OFFSET 652188SN/A 668777Sgblack@eecs.umich.edu// PCI device specific register byte offsets 67217SN/A#define PCI_IDE_TIMING 0x40 688777Sgblack@eecs.umich.edu#define PCI_SLAVE_TIMING 0x44 692SN/A#define PCI_UDMA33_CTRL 0x48 702SN/A#define PCI_UDMA33_TIMING 0x4a 718887Sgeoffrey.blake@arm.com 721070SN/A#define IDETIM (0) 731917SN/A#define SIDETIM (4) 741917SN/A#define UDMACTL (5) 752521SN/A#define UDMATIM (6) 763548Sgblack@eecs.umich.edu 773548Sgblack@eecs.umich.edu// PCI Command bit fields 783548Sgblack@eecs.umich.edu#define BME 0x04 // Bus master function enable 798902Sandreas.hansson@arm.com#define IOSE 0x01 // I/O space enable 808902Sandreas.hansson@arm.com 812330SN/Atypedef enum RegType { 822683Sktlim@umich.edu COMMAND_BLOCK = 0, 832683Sktlim@umich.edu CONTROL_BLOCK, 842683Sktlim@umich.edu BMI_BLOCK 852683Sktlim@umich.edu} RegType_t; 862683Sktlim@umich.edu 872683Sktlim@umich.educlass IdeDisk; 882683Sktlim@umich.educlass IntrControl; 892683Sktlim@umich.educlass PciConfigAll; 902683Sktlim@umich.educlass Tsunami; 912683Sktlim@umich.educlass PhysicalMemory; 922683Sktlim@umich.educlass BaseInterface; 932683Sktlim@umich.educlass HierParams; 942683Sktlim@umich.educlass Bus; 952683Sktlim@umich.edu 962683Sktlim@umich.edu/** 972SN/A * Device model for an Intel PIIX4 IDE controller 982683Sktlim@umich.edu */ 992SN/A 1002107SN/Aclass IdeController : public PciDev 1012107SN/A{ 1022159SN/A private: 1032455SN/A /** Primary command block registers */ 1042455SN/A Addr pri_cmd_addr; 1059920Syasuko.eckert@amd.com Addr pri_cmd_size; 10612109SRekai.GonzalezAlberquilla@arm.com /** Primary control block registers */ 10712109SRekai.GonzalezAlberquilla@arm.com Addr pri_ctrl_addr; 1082SN/A Addr pri_ctrl_size; 1092680SN/A /** Secondary command block registers */ 1102SN/A Addr sec_cmd_addr; 1112190SN/A Addr sec_cmd_size; 1126315Sgblack@eecs.umich.edu /** Secondary control block registers */ 1136315Sgblack@eecs.umich.edu Addr sec_ctrl_addr; 1146315Sgblack@eecs.umich.edu Addr sec_ctrl_size; 1156315Sgblack@eecs.umich.edu /** Bus master interface (BMI) registers */ 1166316Sgblack@eecs.umich.edu Addr bmi_addr; 11712109SRekai.GonzalezAlberquilla@arm.com Addr bmi_size; 1189920Syasuko.eckert@amd.com 1199920Syasuko.eckert@amd.com private: 1209920Syasuko.eckert@amd.com /** Registers used for bus master interface */ 1219384SAndreas.Sandberg@arm.com uint8_t bmi_regs[16]; 1222SN/A /** Shadows of the device select bit */ 1237720Sgblack@eecs.umich.edu uint8_t dev[2]; 1246324Sgblack@eecs.umich.edu /** Registers used in PCI configuration */ 1257597Sminkyu.jeong@arm.com uint8_t pci_regs[8]; 1267597Sminkyu.jeong@arm.com 1277597Sminkyu.jeong@arm.com // Internal management variables 1282190SN/A bool io_enabled; 1298357Sksewell@umich.edu bool bm_enabled; 1308357Sksewell@umich.edu bool cmd_in_progress[4]; 1318735Sandreas.hanson@arm.com 1328357Sksewell@umich.edu public: 1338357Sksewell@umich.edu /** Pointer to the chipset */ 1342683Sktlim@umich.edu Tsunami *tsunami; 1352188SN/A 1362378SN/A private: 1372400SN/A /** IDE disks connected to controller */ 13812406Sgabeblack@google.com IdeDisk *disks[4]; 13912406Sgabeblack@google.com 1402SN/A private: 1419020Sgblack@eecs.umich.edu /** Parse the access address to pass on to device */ 1428541Sgblack@eecs.umich.edu void parseAddr(const Addr &addr, Addr &offset, bool &primary, 1432683Sktlim@umich.edu RegType_t &type); 1448793Sgblack@eecs.umich.edu 1452683Sktlim@umich.edu /** Select the disk based on the channel and device bit */ 14612406Sgabeblack@google.com int getDisk(bool primary); 1472683Sktlim@umich.edu 1488793Sgblack@eecs.umich.edu /** Select the disk based on a pointer */ 1498820Sgblack@eecs.umich.edu int getDisk(IdeDisk *diskPtr); 15012406Sgabeblack@google.com 1519384SAndreas.Sandberg@arm.com public: 1522862Sktlim@umich.edu /** 1532683Sktlim@umich.edu * Constructs and initializes this controller. 1542SN/A * @param name The name of this controller. 1552680SN/A * @param ic The interrupt controller. 156180SN/A * @param mmu The memory controller 1572SN/A * @param cf PCI config space 1582SN/A * @param cd PCI config data 1592862Sktlim@umich.edu * @param bus_num The PCI bus number 1602862Sktlim@umich.edu * @param dev_num The PCI device number 16111168Sandreas.hansson@arm.com * @param func_num The PCI function number 16211168Sandreas.hansson@arm.com * @param host_bus The host bus to connect to 1639461Snilay@cs.wisc.edu * @param hier The hierarchy parameters 164217SN/A */ 1652683Sktlim@umich.edu IdeController(const std::string &name, IntrControl *ic, 1662683Sktlim@umich.edu const std::vector<IdeDisk *> &new_disks, 1675891Sgblack@eecs.umich.edu MemoryController *mmu, PciConfigAll *cf, 1682683Sktlim@umich.edu PciConfigData *cd, Tsunami *t, 1692190SN/A uint32_t bus_num, uint32_t dev_num, uint32_t func_num, 1702683Sktlim@umich.edu Bus *host_bus, HierParams *hier); 1712683Sktlim@umich.edu 1722683Sktlim@umich.edu /** 1732683Sktlim@umich.edu * Deletes the connected devices. 1742680SN/A */ 1752190SN/A ~IdeController(); 1765358Sgblack@eecs.umich.edu 1775358Sgblack@eecs.umich.edu virtual void WriteConfig(int offset, int size, uint32_t data); 1785358Sgblack@eecs.umich.edu virtual void ReadConfig(int offset, int size, uint8_t *data); 1795358Sgblack@eecs.umich.edu 1805358Sgblack@eecs.umich.edu void intrPost(); 1815358Sgblack@eecs.umich.edu void intrClear(); 1825358Sgblack@eecs.umich.edu 1835358Sgblack@eecs.umich.edu void setDmaComplete(IdeDisk *disk); 1845358Sgblack@eecs.umich.edu 1855358Sgblack@eecs.umich.edu /** 1865358Sgblack@eecs.umich.edu * Read a done field for a given target. 1875358Sgblack@eecs.umich.edu * @param req Contains the address of the field to read. 1885358Sgblack@eecs.umich.edu * @param data Return the field read. 1895358Sgblack@eecs.umich.edu * @return The fault condition of the access. 1905358Sgblack@eecs.umich.edu */ 1915358Sgblack@eecs.umich.edu virtual Fault read(MemReqPtr &req, uint8_t *data); 1922683Sktlim@umich.edu 1932521SN/A /** 1945702Ssaidi@eecs.umich.edu * Write to the mmapped I/O control registers. 1955702Ssaidi@eecs.umich.edu * @param req Contains the address to write to. 1965702Ssaidi@eecs.umich.edu * @param data The data to write. 1975702Ssaidi@eecs.umich.edu * @return The fault condition of the access. 1982683Sktlim@umich.edu */ 1992683Sktlim@umich.edu virtual Fault write(MemReqPtr &req, const uint8_t *data); 2002683Sktlim@umich.edu 2012683Sktlim@umich.edu /** 2028735Sandreas.hanson@arm.com * Cache access timing specific to device 2032683Sktlim@umich.edu * @param req Memory request 20412406Sgabeblack@google.com */ 2052683Sktlim@umich.edu Tick cacheAccess(MemReqPtr &req); 20612406Sgabeblack@google.com 2072683Sktlim@umich.edu /** 2088887Sgeoffrey.blake@arm.com * Serialize this object to the given output stream. 2098733Sgeoffrey.blake@arm.com * @param os The stream to serialize to. 2109020Sgblack@eecs.umich.edu */ 2118541Sgblack@eecs.umich.edu virtual void serialize(std::ostream &os); 2124997Sgblack@eecs.umich.edu 2134997Sgblack@eecs.umich.edu /** 2142683Sktlim@umich.edu * Reconstruct the state of this object from a checkpoint. 2152683Sktlim@umich.edu * @param cp The checkpoint use. 2162683Sktlim@umich.edu * @param section The section name of this object 2172683Sktlim@umich.edu */ 21810407Smitch.hayenga@arm.com virtual void unserialize(Checkpoint *cp, const std::string §ion); 21910407Smitch.hayenga@arm.com 2202683Sktlim@umich.edu}; 2212683Sktlim@umich.edu#endif // __IDE_CTRL_HH_ 2222683Sktlim@umich.edu