ide_ctrl.hh revision 864
12SN/A/* 210033SAli.Saidi@ARM.com * Copyright (c) 2003 The Regents of The University of Michigan 39920Syasuko.eckert@amd.com * All rights reserved. 48733Sgeoffrey.blake@arm.com * 58733Sgeoffrey.blake@arm.com * Redistribution and use in source and binary forms, with or without 68733Sgeoffrey.blake@arm.com * modification, are permitted provided that the following conditions are 78733Sgeoffrey.blake@arm.com * met: redistributions of source code must retain the above copyright 88733Sgeoffrey.blake@arm.com * notice, this list of conditions and the following disclaimer; 98733Sgeoffrey.blake@arm.com * redistributions in binary form must reproduce the above copyright 108733Sgeoffrey.blake@arm.com * notice, this list of conditions and the following disclaimer in the 118733Sgeoffrey.blake@arm.com * documentation and/or other materials provided with the distribution; 128733Sgeoffrey.blake@arm.com * neither the name of the copyright holders nor the names of its 138733Sgeoffrey.blake@arm.com * contributors may be used to endorse or promote products derived from 148733Sgeoffrey.blake@arm.com * this software without specific prior written permission. 152188SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A */ 282SN/A 292SN/A/** @file 302SN/A * Simple PCI IDE controller with bus mastering capability and UDMA 312SN/A * modeled after controller in the Intel PIIX4 chip 322SN/A */ 332SN/A 342SN/A#ifndef __IDE_CTRL_HH__ 352SN/A#define __IDE_CTRL_HH__ 362SN/A 372SN/A#include "dev/pcidev.hh" 382SN/A#include "dev/pcireg.h" 392SN/A#include "dev/io_device.hh" 402665SN/A 412665SN/A#define BMIC0 0x0 // Bus master IDE command register 422665SN/A#define BMIS0 0x2 // Bus master IDE status register 432SN/A#define BMIDTP0 0x4 // Bus master IDE descriptor table pointer register 442SN/A#define BMIC1 0x8 // Bus master IDE command register 452683Sktlim@umich.edu#define BMIS1 0xa // Bus master IDE status register 462683Sktlim@umich.edu#define BMIDTP1 0xc // Bus master IDE descriptor table pointer register 472SN/A 489020Sgblack@eecs.umich.edu// Bus master IDE command register bit fields 496313Sgblack@eecs.umich.edu#define RWCON 0x08 // Bus master read/write control 502190SN/A#define SSBM 0x01 // Start/stop bus master 516329Sgblack@eecs.umich.edu 524997Sgblack@eecs.umich.edu// Bus master IDE status register bit fields 536316Sgblack@eecs.umich.edu#define DMA1CAP 0x40 // Drive 1 DMA capable 546216Snate@binkert.org#define DMA0CAP 0x20 // Drive 0 DMA capable 556658Snate@binkert.org#define IDEINTS 0x04 // IDE Interrupt Status 562680SN/A#define IDEDMAE 0x02 // IDE DMA error 572683Sktlim@umich.edu#define BMIDEA 0x01 // Bus master IDE active 589920Syasuko.eckert@amd.com 598232Snate@binkert.org// IDE Command byte fields 608232Snate@binkert.org#define IDE_SELECT_OFFSET (6) 618777Sgblack@eecs.umich.edu#define IDE_SELECT_DEV_BIT 0x10 622395SN/A 632190SN/A#define IDE_FEATURE_OFFSET IDE_ERROR_OFFSET 642188SN/A#define IDE_COMMAND_OFFSET IDE_STATUS_OFFSET 658777Sgblack@eecs.umich.edu 66217SN/A// PCI device specific register byte offsets 678777Sgblack@eecs.umich.edu#define PCI_IDE_TIMING 0x40 682SN/A#define PCI_SLAVE_TIMING 0x44 692SN/A#define PCI_UDMA33_CTRL 0x48 708887Sgeoffrey.blake@arm.com#define PCI_UDMA33_TIMING 0x4a 711070SN/A 721917SN/A#define IDETIM (0) 731917SN/A#define SIDETIM (4) 742521SN/A#define UDMACTL (5) 753548Sgblack@eecs.umich.edu#define UDMATIM (6) 763548Sgblack@eecs.umich.edu 773548Sgblack@eecs.umich.edu// PCI Command bit fields 788902Sandreas.hansson@arm.com#define BME 0x04 // Bus master function enable 798902Sandreas.hansson@arm.com#define IOSE 0x01 // I/O space enable 802330SN/A 812683Sktlim@umich.edutypedef enum RegType { 822683Sktlim@umich.edu COMMAND_BLOCK = 0, 832683Sktlim@umich.edu CONTROL_BLOCK, 842683Sktlim@umich.edu BMI_BLOCK 852683Sktlim@umich.edu} RegType_t; 862683Sktlim@umich.edu 872683Sktlim@umich.educlass IdeDisk; 882683Sktlim@umich.educlass IntrControl; 892683Sktlim@umich.educlass PciConfigAll; 902683Sktlim@umich.educlass Tsunami; 912683Sktlim@umich.educlass PhysicalMemory; 922683Sktlim@umich.educlass BaseInterface; 932683Sktlim@umich.educlass HierParams; 942683Sktlim@umich.educlass Bus; 952683Sktlim@umich.edu 962SN/A/** 972683Sktlim@umich.edu * Device model for an Intel PIIX4 IDE controller 982SN/A */ 992107SN/A 1002107SN/Aclass IdeController : public PciDev 1012159SN/A{ 1022455SN/A private: 1032455SN/A /** Primary command block registers */ 1049920Syasuko.eckert@amd.com Addr pri_cmd_addr; 1052SN/A Addr pri_cmd_size; 1062680SN/A /** Primary control block registers */ 1072SN/A Addr pri_ctrl_addr; 1082190SN/A Addr pri_ctrl_size; 1096315Sgblack@eecs.umich.edu /** Secondary command block registers */ 1106315Sgblack@eecs.umich.edu Addr sec_cmd_addr; 1116315Sgblack@eecs.umich.edu Addr sec_cmd_size; 1126315Sgblack@eecs.umich.edu /** Secondary control block registers */ 1136316Sgblack@eecs.umich.edu Addr sec_ctrl_addr; 1149920Syasuko.eckert@amd.com Addr sec_ctrl_size; 1159920Syasuko.eckert@amd.com /** Bus master interface (BMI) registers */ 1169920Syasuko.eckert@amd.com Addr bmi_addr; 1179384SAndreas.Sandberg@arm.com Addr bmi_size; 1182SN/A 1197720Sgblack@eecs.umich.edu private: 1206324Sgblack@eecs.umich.edu /** Registers used for bus master interface */ 1217597Sminkyu.jeong@arm.com uint8_t bmi_regs[16]; 1227597Sminkyu.jeong@arm.com /** Shadows of the device select bit */ 1237597Sminkyu.jeong@arm.com uint8_t dev[2]; 1242190SN/A /** Registers used in PCI configuration */ 1258357Sksewell@umich.edu uint8_t pci_regs[8]; 1268357Sksewell@umich.edu 1278735Sandreas.hanson@arm.com // Internal management variables 1288357Sksewell@umich.edu bool io_enabled; 1298357Sksewell@umich.edu bool bm_enabled; 1302683Sktlim@umich.edu bool cmd_in_progress[4]; 1312188SN/A 1322378SN/A public: 1332400SN/A /** Pointer to the chipset */ 1346022Sgblack@eecs.umich.edu Tsunami *tsunami; 1356022Sgblack@eecs.umich.edu 1362SN/A private: 1379020Sgblack@eecs.umich.edu /** IDE disks connected to controller */ 1388541Sgblack@eecs.umich.edu IdeDisk *disks[4]; 1392683Sktlim@umich.edu 1408793Sgblack@eecs.umich.edu private: 1412683Sktlim@umich.edu /** Parse the access address to pass on to device */ 1429384SAndreas.Sandberg@arm.com void parseAddr(const Addr &addr, Addr &offset, bool &primary, 1432683Sktlim@umich.edu RegType_t &type); 1448793Sgblack@eecs.umich.edu 1458820Sgblack@eecs.umich.edu /** Select the disk based on the channel and device bit */ 1469384SAndreas.Sandberg@arm.com int getDisk(bool primary); 1479384SAndreas.Sandberg@arm.com 1482862Sktlim@umich.edu /** Select the disk based on a pointer */ 1492683Sktlim@umich.edu int getDisk(IdeDisk *diskPtr); 1502SN/A 1512680SN/A public: 152180SN/A /** 1532SN/A * Constructs and initializes this controller. 1542SN/A * @param name The name of this controller. 1552862Sktlim@umich.edu * @param ic The interrupt controller. 1562862Sktlim@umich.edu * @param mmu The memory controller 15711168Sandreas.hansson@arm.com * @param cf PCI config space 15811168Sandreas.hansson@arm.com * @param cd PCI config data 1599461Snilay@cs.wisc.edu * @param bus_num The PCI bus number 160217SN/A * @param dev_num The PCI device number 1612683Sktlim@umich.edu * @param func_num The PCI function number 1622683Sktlim@umich.edu * @param host_bus The host bus to connect to 1635891Sgblack@eecs.umich.edu * @param hier The hierarchy parameters 1642683Sktlim@umich.edu */ 1652190SN/A IdeController(const std::string &name, IntrControl *ic, 1662683Sktlim@umich.edu const std::vector<IdeDisk *> &new_disks, 1672683Sktlim@umich.edu MemoryController *mmu, PciConfigAll *cf, 1682683Sktlim@umich.edu PciConfigData *cd, Tsunami *t, 1692683Sktlim@umich.edu uint32_t bus_num, uint32_t dev_num, uint32_t func_num, 1702680SN/A Bus *host_bus, HierParams *hier); 1712190SN/A 1725358Sgblack@eecs.umich.edu /** 1735358Sgblack@eecs.umich.edu * Deletes the connected devices. 1745358Sgblack@eecs.umich.edu */ 1755358Sgblack@eecs.umich.edu ~IdeController(); 1765358Sgblack@eecs.umich.edu 1775358Sgblack@eecs.umich.edu virtual void WriteConfig(int offset, int size, uint32_t data); 1785358Sgblack@eecs.umich.edu virtual void ReadConfig(int offset, int size, uint8_t *data); 1795358Sgblack@eecs.umich.edu 1805358Sgblack@eecs.umich.edu void intrPost(); 1815358Sgblack@eecs.umich.edu void intrClear(); 1825358Sgblack@eecs.umich.edu 1835358Sgblack@eecs.umich.edu void setDmaComplete(IdeDisk *disk); 1845358Sgblack@eecs.umich.edu 1855358Sgblack@eecs.umich.edu /** 1865358Sgblack@eecs.umich.edu * Read a done field for a given target. 1875358Sgblack@eecs.umich.edu * @param req Contains the address of the field to read. 1882683Sktlim@umich.edu * @param data Return the field read. 1892521SN/A * @return The fault condition of the access. 1905702Ssaidi@eecs.umich.edu */ 1915702Ssaidi@eecs.umich.edu virtual Fault read(MemReqPtr &req, uint8_t *data); 1925702Ssaidi@eecs.umich.edu 1935702Ssaidi@eecs.umich.edu /** 1942683Sktlim@umich.edu * Write to the mmapped I/O control registers. 1952683Sktlim@umich.edu * @param req Contains the address to write to. 1962683Sktlim@umich.edu * @param data The data to write. 1972683Sktlim@umich.edu * @return The fault condition of the access. 1988735Sandreas.hanson@arm.com */ 1992683Sktlim@umich.edu virtual Fault write(MemReqPtr &req, const uint8_t *data); 2006022Sgblack@eecs.umich.edu 2012683Sktlim@umich.edu /** 2026022Sgblack@eecs.umich.edu * Cache access timing specific to device 2032683Sktlim@umich.edu * @param req Memory request 2048887Sgeoffrey.blake@arm.com */ 2058733Sgeoffrey.blake@arm.com Tick cacheAccess(MemReqPtr &req); 2069020Sgblack@eecs.umich.edu 2078541Sgblack@eecs.umich.edu /** 2084997Sgblack@eecs.umich.edu * Serialize this object to the given output stream. 2094997Sgblack@eecs.umich.edu * @param os The stream to serialize to. 2102683Sktlim@umich.edu */ 2112683Sktlim@umich.edu virtual void serialize(std::ostream &os); 2122683Sktlim@umich.edu 2132683Sktlim@umich.edu /** 21410407Smitch.hayenga@arm.com * Reconstruct the state of this object from a checkpoint. 21510407Smitch.hayenga@arm.com * @param cp The checkpoint use. 2162683Sktlim@umich.edu * @param section The section name of this object 2172683Sktlim@umich.edu */ 2182683Sktlim@umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 2192683Sktlim@umich.edu 2202683Sktlim@umich.edu}; 2212683Sktlim@umich.edu#endif // __IDE_CTRL_HH_ 2222683Sktlim@umich.edu