t1000.cc revision 4762:c94e103c83ad
110259SAndrew.Bardsley@arm.com/*
210259SAndrew.Bardsley@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan
310259SAndrew.Bardsley@arm.com * All rights reserved.
410259SAndrew.Bardsley@arm.com *
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610259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are
710259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright
810259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer;
910259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright
1010259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the
1110259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution;
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1410259SAndrew.Bardsley@arm.com * this software without specific prior written permission.
1510259SAndrew.Bardsley@arm.com *
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1710259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
1810259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
1910259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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2610259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2710259SAndrew.Bardsley@arm.com *
2810259SAndrew.Bardsley@arm.com * Authors: Ali Saidi
2910259SAndrew.Bardsley@arm.com */
3010259SAndrew.Bardsley@arm.com
3110259SAndrew.Bardsley@arm.com/** @file
3210259SAndrew.Bardsley@arm.com * Implementation of T1000 platform.
3310259SAndrew.Bardsley@arm.com */
3410259SAndrew.Bardsley@arm.com
3510259SAndrew.Bardsley@arm.com#include <deque>
3610259SAndrew.Bardsley@arm.com#include <string>
3710259SAndrew.Bardsley@arm.com#include <vector>
3810259SAndrew.Bardsley@arm.com
3910259SAndrew.Bardsley@arm.com#include "cpu/intr_control.hh"
4010259SAndrew.Bardsley@arm.com#include "dev/simconsole.hh"
4110259SAndrew.Bardsley@arm.com#include "dev/sparc/t1000.hh"
4210259SAndrew.Bardsley@arm.com#include "params/T1000.hh"
4310259SAndrew.Bardsley@arm.com#include "sim/system.hh"
4410259SAndrew.Bardsley@arm.com
4510259SAndrew.Bardsley@arm.comusing namespace std;
4610259SAndrew.Bardsley@arm.com//Should this be AlphaISA?
4710259SAndrew.Bardsley@arm.comusing namespace TheISA;
4810259SAndrew.Bardsley@arm.com
4910259SAndrew.Bardsley@arm.comT1000::T1000(const string &name, System *s, IntrControl *ic)
5010259SAndrew.Bardsley@arm.com    : Platform(name, ic), system(s)
5110259SAndrew.Bardsley@arm.com{
5210259SAndrew.Bardsley@arm.com    // set the back pointer from the system to myself
5310259SAndrew.Bardsley@arm.com    system->platform = this;
5410259SAndrew.Bardsley@arm.com}
5510259SAndrew.Bardsley@arm.com
5610259SAndrew.Bardsley@arm.comTick
5710259SAndrew.Bardsley@arm.comT1000::intrFrequency()
5810259SAndrew.Bardsley@arm.com{
5910259SAndrew.Bardsley@arm.com    panic("Need implementation\n");
6010259SAndrew.Bardsley@arm.com    M5_DUMMY_RETURN
6110259SAndrew.Bardsley@arm.com}
6210259SAndrew.Bardsley@arm.com
6310259SAndrew.Bardsley@arm.comvoid
6410259SAndrew.Bardsley@arm.comT1000::postConsoleInt()
6510259SAndrew.Bardsley@arm.com{
6610259SAndrew.Bardsley@arm.com    warn_once("Don't know what interrupt to post for console.\n");
6710259SAndrew.Bardsley@arm.com    //panic("Need implementation\n");
6810259SAndrew.Bardsley@arm.com}
6910259SAndrew.Bardsley@arm.com
7010259SAndrew.Bardsley@arm.comvoid
7110259SAndrew.Bardsley@arm.comT1000::clearConsoleInt()
7210259SAndrew.Bardsley@arm.com{
7310259SAndrew.Bardsley@arm.com    warn_once("Don't know what interrupt to clear for console.\n");
7410259SAndrew.Bardsley@arm.com    //panic("Need implementation\n");
7510259SAndrew.Bardsley@arm.com}
7610259SAndrew.Bardsley@arm.com
7710259SAndrew.Bardsley@arm.comvoid
7810259SAndrew.Bardsley@arm.comT1000::postPciInt(int line)
7910259SAndrew.Bardsley@arm.com{
8010259SAndrew.Bardsley@arm.com    panic("Need implementation\n");
8110259SAndrew.Bardsley@arm.com}
8210259SAndrew.Bardsley@arm.com
8310259SAndrew.Bardsley@arm.comvoid
8410259SAndrew.Bardsley@arm.comT1000::clearPciInt(int line)
8510259SAndrew.Bardsley@arm.com{
8610259SAndrew.Bardsley@arm.com    panic("Need implementation\n");
8710259SAndrew.Bardsley@arm.com}
8810259SAndrew.Bardsley@arm.com
8910259SAndrew.Bardsley@arm.comAddr
9010259SAndrew.Bardsley@arm.comT1000::pciToDma(Addr pciAddr) const
9110259SAndrew.Bardsley@arm.com{
9210259SAndrew.Bardsley@arm.com    panic("Need implementation\n");
9310259SAndrew.Bardsley@arm.com    M5_DUMMY_RETURN
9410259SAndrew.Bardsley@arm.com}
9510259SAndrew.Bardsley@arm.com
9610259SAndrew.Bardsley@arm.com
9710259SAndrew.Bardsley@arm.comAddr
9810259SAndrew.Bardsley@arm.comT1000::calcConfigAddr(int bus, int dev, int func)
9910259SAndrew.Bardsley@arm.com{
10010259SAndrew.Bardsley@arm.com    panic("Need implementation\n");
10110259SAndrew.Bardsley@arm.com    M5_DUMMY_RETURN
10210259SAndrew.Bardsley@arm.com}
10310259SAndrew.Bardsley@arm.com
10410259SAndrew.Bardsley@arm.comT1000 *
10510259SAndrew.Bardsley@arm.comT1000Params::create()
10610259SAndrew.Bardsley@arm.com{
10710259SAndrew.Bardsley@arm.com    return new T1000(name, system, intrctrl);
10810259SAndrew.Bardsley@arm.com}
10910259SAndrew.Bardsley@arm.com