t1000.cc revision 11793:ef606668d247 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31/** @file
32 * Implementation of T1000 platform.
33 */
34
35#include "dev/sparc/t1000.hh"
36
37#include <deque>
38#include <string>
39#include <vector>
40
41#include "config/the_isa.hh"
42#include "cpu/intr_control.hh"
43#include "dev/terminal.hh"
44#include "sim/system.hh"
45
46using namespace std;
47//Should this be AlphaISA?
48using namespace TheISA;
49
50T1000::T1000(const Params *p)
51    : Platform(p), system(p->system)
52{}
53
54void
55T1000::postConsoleInt()
56{
57    warn_once("Don't know what interrupt to post for console.\n");
58    //panic("Need implementation\n");
59}
60
61void
62T1000::clearConsoleInt()
63{
64    warn_once("Don't know what interrupt to clear for console.\n");
65    //panic("Need implementation\n");
66}
67
68void
69T1000::postPciInt(int line)
70{
71    panic("Need implementation\n");
72}
73
74void
75T1000::clearPciInt(int line)
76{
77    panic("Need implementation\n");
78}
79
80Addr
81T1000::pciToDma(Addr pciAddr) const
82{
83    panic("Need implementation\n");
84    M5_DUMMY_RETURN
85}
86
87
88Addr
89T1000::calcPciConfigAddr(int bus, int dev, int func)
90{
91    panic("Need implementation\n");
92    M5_DUMMY_RETURN
93}
94
95Addr
96T1000::calcPciIOAddr(Addr addr)
97{
98    panic("Need implementation\n");
99    M5_DUMMY_RETURN
100}
101
102Addr
103T1000::calcPciMemAddr(Addr addr)
104{
105    panic("Need implementation\n");
106    M5_DUMMY_RETURN
107}
108
109T1000 *
110T1000Params::create()
111{
112    return new T1000(this);
113}
114