T1000.py revision 3898 
16157Snate@binkert.orgfrom m5.params import *
26157Snate@binkert.orgfrom m5.proxy import *
36157Snate@binkert.orgfrom Device import BasicPioDevice, IsaFake, BadAddr
46157Snate@binkert.orgfrom Uart import Uart8250
56157Snate@binkert.orgfrom Platform import Platform
66157Snate@binkert.orgfrom SimConsole import SimConsole, ConsoleListener
76157Snate@binkert.org
86157Snate@binkert.org
96157Snate@binkert.orgclass MmDisk(BasicPioDevice):
106157Snate@binkert.org    type = 'MmDisk'
116157Snate@binkert.org    image = Param.DiskImage("Disk Image")
126157Snate@binkert.org    pio_addr = 0x1F40000000
136157Snate@binkert.org
146157Snate@binkert.orgclass T1000(Platform):
156157Snate@binkert.org    type = 'T1000'
166157Snate@binkert.org    system = Param.System(Parent.any, "system")
176157Snate@binkert.org
186157Snate@binkert.org    fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000,
196157Snate@binkert.org            warn_access="Accessing Clock Unit -- Unimplemented!")
206157Snate@binkert.org
216157Snate@binkert.org    fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384,
226157Snate@binkert.org            ret_data64=0x0000000000000000, update_data=False,
236157Snate@binkert.org            warn_access="Accessing Memory Banks -- Unimplemented!")
246157Snate@binkert.org
256157Snate@binkert.org    fake_iob = IsaFake(pio_addr=0x9800000000, pio_size=0x100000000,
266157Snate@binkert.org            warn_access="Accessing IOB -- Unimplemented!")
276157Snate@binkert.org
286157Snate@binkert.org    fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000,
296157Snate@binkert.org            warn_access="Accessing JBI -- Unimplemented!")
306157Snate@binkert.org
316157Snate@binkert.org    fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8,
326157Snate@binkert.org            ret_data64=0x0000000000000001, update_data=True,
336157Snate@binkert.org            warn_access="Accessing L2 Cache Banks -- Unimplemented!")
346157Snate@binkert.org
356157Snate@binkert.org    fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8,
366157Snate@binkert.org            ret_data64=0x0000000000000001, update_data=True,
376157Snate@binkert.org            warn_access="Accessing L2 Cache Banks -- Unimplemented!")
386157Snate@binkert.org
396157Snate@binkert.org    fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8,
407768SAli.Saidi@ARM.com            ret_data64=0x0000000000000001, update_data=True,
417768SAli.Saidi@ARM.com            warn_access="Accessing L2 Cache Banks -- Unimplemented!")
427768SAli.Saidi@ARM.com
436168Snate@binkert.org    fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8,
446168Snate@binkert.org            ret_data64=0x0000000000000001, update_data=True,
456168Snate@binkert.org            warn_access="Accessing L2 Cache Banks -- Unimplemented!")
466157Snate@binkert.org
476157Snate@binkert.org    fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8,
486157Snate@binkert.org            ret_data64=0x0000000000000000, update_data=True,
496157Snate@binkert.org            warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
506157Snate@binkert.org
516157Snate@binkert.org    fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8,
526157Snate@binkert.org            ret_data64=0x0000000000000000, update_data=True,
536157Snate@binkert.org            warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
546157Snate@binkert.org
556157Snate@binkert.org    fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8,
566157Snate@binkert.org            ret_data64=0x0000000000000000, update_data=True,
576157Snate@binkert.org            warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
586157Snate@binkert.org
596157Snate@binkert.org    fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8,
606157Snate@binkert.org            ret_data64=0x0000000000000000, update_data=True,
616157Snate@binkert.org            warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
626157Snate@binkert.org
636157Snate@binkert.org    fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000,
646157Snate@binkert.org            warn_access="Accessing SSI -- Unimplemented!")
656157Snate@binkert.org
666157Snate@binkert.org    hvuart = Uart8250(pio_addr=0xfff0c2c000)
676157Snate@binkert.org    puart0 = Uart8250(pio_addr=0x1f10000000)
686157Snate@binkert.org    console = SimConsole(listener = ConsoleListener())
696157Snate@binkert.org
706157Snate@binkert.org    # Attach I/O devices to specified bus object.  Can't do this
716157Snate@binkert.org    # earlier, since the bus object itself is typically defined at the
726157Snate@binkert.org    # System level.
736157Snate@binkert.org    def attachIO(self, bus):
746157Snate@binkert.org        self.fake_clk.pio = bus.port
756157Snate@binkert.org        self.fake_membnks.pio = bus.port
766157Snate@binkert.org        self.fake_iob.pio = bus.port
776157Snate@binkert.org        self.fake_jbi.pio = bus.port
786157Snate@binkert.org        self.fake_l2_1.pio = bus.port
796157Snate@binkert.org        self.fake_l2_2.pio = bus.port
806157Snate@binkert.org        self.fake_l2_3.pio = bus.port
816157Snate@binkert.org        self.fake_l2_4.pio = bus.port
826157Snate@binkert.org        self.fake_l2esr_1.pio = bus.port
836157Snate@binkert.org        self.fake_l2esr_2.pio = bus.port
846157Snate@binkert.org        self.fake_l2esr_3.pio = bus.port
856157Snate@binkert.org        self.fake_l2esr_4.pio = bus.port
866157Snate@binkert.org        self.fake_ssi.pio = bus.port
876157Snate@binkert.org        self.puart0.pio = bus.port
886157Snate@binkert.org        self.hvuart.pio = bus.port
896157Snate@binkert.org