T1000.py revision 3825 
1from m5.params import *
2from m5.proxy import *
3from Device import BasicPioDevice, IsaFake, BadAddr
4from Uart import Uart8250
5from Platform import Platform
6from SimConsole import SimConsole, ConsoleListener
7
8class T1000(Platform):
9    type = 'T1000'
10    system = Param.System(Parent.any, "system")
11
12    fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000,
13            warn_access="Accessing Clock Unit -- Unimplemented!")
14
15    fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384,
16            ret_data64=0x0000000000000000, update_data=False,
17            warn_access="Accessing Memory Banks -- Unimplemented!")
18
19    fake_iob = IsaFake(pio_addr=0x9800000000, pio_size=0x100000000,
20            warn_access="Accessing IOB -- Unimplemented!")
21
22    fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000,
23            warn_access="Accessing JBI -- Unimplemented!")
24
25    fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8,
26            ret_data64=0x0000000000000001, update_data=True,
27            warn_access="Accessing L2 Cache Banks -- Unimplemented!")
28
29    fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8,
30            ret_data64=0x0000000000000001, update_data=True,
31            warn_access="Accessing L2 Cache Banks -- Unimplemented!")
32
33    fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8,
34            ret_data64=0x0000000000000001, update_data=True,
35            warn_access="Accessing L2 Cache Banks -- Unimplemented!")
36
37    fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8,
38            ret_data64=0x0000000000000001, update_data=True,
39            warn_access="Accessing L2 Cache Banks -- Unimplemented!")
40
41    fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8,
42            ret_data64=0x0000000000000000, update_data=True,
43            warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
44
45    fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8,
46            ret_data64=0x0000000000000000, update_data=True,
47            warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
48
49    fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8,
50            ret_data64=0x0000000000000000, update_data=True,
51            warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
52
53    fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8,
54            ret_data64=0x0000000000000000, update_data=True,
55            warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
56
57    fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000,
58            warn_access="Accessing SSI -- Unimplemented!")
59
60    hvuart = Uart8250(pio_addr=0xfff0c2c000)
61    puart0 = Uart8250(pio_addr=0x1f10000000)
62    console = SimConsole(listener = ConsoleListener())
63
64    # Attach I/O devices to specified bus object.  Can't do this
65    # earlier, since the bus object itself is typically defined at the
66    # System level.
67    def attachIO(self, bus):
68        self.fake_clk.pio = bus.port
69        self.fake_membnks.pio = bus.port
70        self.fake_iob.pio = bus.port
71        self.fake_jbi.pio = bus.port
72        self.fake_l2_1.pio = bus.port
73        self.fake_l2_2.pio = bus.port
74        self.fake_l2_3.pio = bus.port
75        self.fake_l2_4.pio = bus.port
76        self.fake_l2esr_1.pio = bus.port
77        self.fake_l2esr_2.pio = bus.port
78        self.fake_l2esr_3.pio = bus.port
79        self.fake_l2esr_4.pio = bus.port
80        self.fake_ssi.pio = bus.port
81        self.puart0.pio = bus.port
82        self.hvuart.pio = bus.port
83