platform.hh revision 11244
1807SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 3807SN/A * All rights reserved. 4807SN/A * 5807SN/A * Redistribution and use in source and binary forms, with or without 6807SN/A * modification, are permitted provided that the following conditions are 7807SN/A * met: redistributions of source code must retain the above copyright 8807SN/A * notice, this list of conditions and the following disclaimer; 9807SN/A * redistributions in binary form must reproduce the above copyright 10807SN/A * notice, this list of conditions and the following disclaimer in the 11807SN/A * documentation and/or other materials provided with the distribution; 12807SN/A * neither the name of the copyright holders nor the names of its 13807SN/A * contributors may be used to endorse or promote products derived from 14807SN/A * this software without specific prior written permission. 15807SN/A * 16807SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17807SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18807SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19807SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20807SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21807SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22807SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23807SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24807SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25807SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26807SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Andrew Schultz 292760Sbinkertn@umich.edu * Nathan Binkert 30807SN/A */ 31807SN/A 32807SN/A/** 33807SN/A * @file 34807SN/A * Generic interface for platforms 35807SN/A */ 36807SN/A 371634SN/A#ifndef __DEV_PLATFORM_HH__ 381634SN/A#define __DEV_PLATFORM_HH__ 39807SN/A 402846Ssaidi@eecs.umich.edu#include <bitset> 412846Ssaidi@eecs.umich.edu#include <set> 422846Ssaidi@eecs.umich.edu 438229Snate@binkert.org#include "params/Platform.hh" 44807SN/A#include "sim/sim_object.hh" 45807SN/A 46807SN/Aclass IntrControl; 475478Snate@binkert.orgclass Terminal; 48932SN/Aclass Uart; 492384SN/Aclass System; 50807SN/A 5111244Sandreas.sandberg@arm.com 52807SN/Aclass Platform : public SimObject 53807SN/A{ 54807SN/A public: 55807SN/A /** Pointer to the interrupt controller */ 56807SN/A IntrControl *intrctrl; 571634SN/A 58807SN/A public: 595034Smilesck@eecs.umich.edu typedef PlatformParams Params; 605034Smilesck@eecs.umich.edu Platform(const Params *p); 611634SN/A virtual ~Platform(); 6211244Sandreas.sandberg@arm.com 6311244Sandreas.sandberg@arm.com /** 6411244Sandreas.sandberg@arm.com * Cause the cpu to post a serial interrupt to the CPU. 6511244Sandreas.sandberg@arm.com */ 66865SN/A virtual void postConsoleInt() = 0; 6711244Sandreas.sandberg@arm.com 6811244Sandreas.sandberg@arm.com /** 6911244Sandreas.sandberg@arm.com * Clear a posted CPU interrupt 7011244Sandreas.sandberg@arm.com */ 71865SN/A virtual void clearConsoleInt() = 0; 7211244Sandreas.sandberg@arm.com 7311244Sandreas.sandberg@arm.com 7411244Sandreas.sandberg@arm.com /** 7511244Sandreas.sandberg@arm.com * Cause the chipset to post a cpi interrupt to the CPU. 7611244Sandreas.sandberg@arm.com */ 771149SN/A virtual void postPciInt(int line); 7811244Sandreas.sandberg@arm.com 7911244Sandreas.sandberg@arm.com /** 8011244Sandreas.sandberg@arm.com * Clear a posted PCI->CPU interrupt 8111244Sandreas.sandberg@arm.com */ 821149SN/A virtual void clearPciInt(int line); 83807SN/A}; 84807SN/A 851634SN/A#endif // __DEV_PLATFORM_HH__ 86