device.hh revision 845
12SN/A/* 28733Sgeoffrey.blake@arm.com * Copyright (c) 2003 The Regents of The University of Michigan 37338SAli.Saidi@ARM.com * All rights reserved. 47338SAli.Saidi@ARM.com * 57338SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67338SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77338SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87338SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97338SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107338SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117338SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127338SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137338SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 141762SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A */ 282SN/A 292SN/A/* @file 302SN/A * Interface for devices using PCI configuration 312SN/A */ 322SN/A 332SN/A#ifndef __PCI_DEV_HH__ 342SN/A#define __PCI_DEV_HH__ 352SN/A 362SN/A#include "dev/pcireg.h" 372SN/A#include "dev/io_device.hh" 382SN/A 392665Ssaidi@eecs.umich.educlass PciConfigAll; 402665Ssaidi@eecs.umich.educlass MemoryController; 412SN/A 422SN/Aclass PciConfigData : public SimObject 436216Snate@binkert.org{ 442439SN/A public: 458229Snate@binkert.org PciConfigData(const std::string &name) 466216Snate@binkert.org : SimObject(name) 47146SN/A { 48146SN/A memset(config.data, 0, sizeof(config.data)); 49146SN/A memset(BARAddrs, 0, sizeof(BARAddrs)); 50146SN/A memset(BARSize, 0, sizeof(BARSize)); 51146SN/A } 52146SN/A 536216Snate@binkert.org PCIConfig config; 546658Snate@binkert.org uint32_t BARSize[6]; 558733Sgeoffrey.blake@arm.com Addr BARAddrs[6]; 568229Snate@binkert.org}; 571717SN/A 58146SN/A/** 591977SN/A * PCI device, base implemnation is only config space. 602683Sktlim@umich.edu * Each device is connected to a PCIConfigSpace device 611717SN/A * which returns -1 for everything but the pcidevs that 62146SN/A * register with it. This object registers with the PCIConfig space 632683Sktlim@umich.edu * object. 648232Snate@binkert.org */ 658232Snate@binkert.orgclass PciDev : public DmaDevice 668232Snate@binkert.org{ 673348Sbinkertn@umich.edu protected: 686105Ssteve.reinhardt@amd.com MemoryController *MMU; 696216Snate@binkert.org PciConfigAll *ConfigSpace; 702036SN/A PciConfigData *ConfigData; 71146SN/A uint32_t BusNum; 7256SN/A uint32_t DeviceNum; 7356SN/A uint32_t FunctionNum; 74695SN/A 752901Ssaidi@eecs.umich.edu PCIConfig config; 762SN/A uint32_t BARSize[6]; 771858SN/A Addr BARAddrs[6]; 783565Sgblack@eecs.umich.edu 793565Sgblack@eecs.umich.edu public: 802171SN/A PciDev(const std::string &name, MemoryController *mmu, PciConfigAll *cf, 812170SN/A PciConfigData *cd, uint32_t bus, uint32_t dev, uint32_t func); 82146SN/A 832462SN/A virtual Fault read(MemReqPtr &req, uint8_t *data) { 84146SN/A return No_Fault; 852SN/A } 868733Sgeoffrey.blake@arm.com virtual Fault write(MemReqPtr &req, const uint8_t *data) { 878733Sgeoffrey.blake@arm.com return No_Fault; 888733Sgeoffrey.blake@arm.com } 898733Sgeoffrey.blake@arm.com 908733Sgeoffrey.blake@arm.com virtual void WriteConfig(int offset, int size, uint32_t data); 912SN/A virtual void ReadConfig(int offset, int size, uint8_t *data); 922449SN/A 931355SN/A virtual void serialize(std::ostream &os); 945529Snate@binkert.org virtual void unserialize(Checkpoint *cp, const std::string §ion); 954495Sacolyte@umich.edu}; 96224SN/A 971858SN/A#endif // __PCI_DEV_HH__ 982683Sktlim@umich.edu