ns_gige_reg.h revision 1057
12381SN/A/* 210713Sandreas.hansson@arm.com * Copyright (c) 2004 The Regents of The University of Michigan 38711SN/A * All rights reserved. 48711SN/A * 58711SN/A * Redistribution and use in source and binary forms, with or without 68711SN/A * modification, are permitted provided that the following conditions are 78711SN/A * met: redistributions of source code must retain the above copyright 88711SN/A * notice, this list of conditions and the following disclaimer; 98711SN/A * redistributions in binary form must reproduce the above copyright 108711SN/A * notice, this list of conditions and the following disclaimer in the 118711SN/A * documentation and/or other materials provided with the distribution; 128711SN/A * neither the name of the copyright holders nor the names of its 138711SN/A * contributors may be used to endorse or promote products derived from 142381SN/A * this software without specific prior written permission. 152381SN/A * 162381SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172381SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182381SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192381SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202381SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212381SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222381SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232381SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242381SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252381SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262381SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272381SN/A */ 282381SN/A 292381SN/A/* Portions of code taken from: */ 302381SN/A 312381SN/A/* ns83820.c by Benjamin LaHaise with contributions. 322381SN/A * 332381SN/A * Questions/comments/discussion to linux-ns83820@kvack.org. 342381SN/A * 352381SN/A * $Revision: 1.34.2.23 $ 362381SN/A * 372381SN/A * Copyright 2001 Benjamin LaHaise. 382381SN/A * Copyright 2001, 2002 Red Hat. 392665SN/A * 402665SN/A * Mmmm, chocolate vanilla mocha... 412772SN/A * 428715SN/A * 438922SN/A * This program is free software; you can redistribute it and/or modify 442381SN/A * it under the terms of the GNU General Public License as published by 452381SN/A * the Free Software Foundation; either version 2 of the License, or 462381SN/A * (at your option) any later version. 472982SN/A * 4810405Sandreas.hansson@arm.com * This program is distributed in the hope that it will be useful, 492381SN/A * but WITHOUT ANY WARRANTY; without even the implied warranty of 502381SN/A * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 5110405Sandreas.hansson@arm.com * GNU General Public License for more details. 5210405Sandreas.hansson@arm.com * 532381SN/A * You should have received a copy of the GNU General Public License 549291SN/A * along with this program; if not, write to the Free Software 5511168Sandreas.hansson@arm.com * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 562381SN/A */ 579235SN/A 586215SN/A/* @file 592381SN/A * Ethernet device register definitions for the National 6010888Sandreas.hansson@arm.com * Semiconductor DP83820 Ethernet controller 6110405Sandreas.hansson@arm.com */ 629712SN/A 632381SN/A#ifndef __DEV_NS_GIGE_REG_H__ 649036SN/A#define __DEV_NS_GIGE_REG_H__ 6510405Sandreas.hansson@arm.com 6610405Sandreas.hansson@arm.com/* 6710405Sandreas.hansson@arm.com * Configuration Register Map 6810405Sandreas.hansson@arm.com */ 699036SN/A#define NS_ID 0x00 /* identification register */ 7010405Sandreas.hansson@arm.com#define NS_CS 0x04 /* command and status register */ 719036SN/A#define NS_RID 0x08 /* revision ID register */ 729036SN/A#define NS_LAT 0x0C /* latency timer register */ 7310405Sandreas.hansson@arm.com#define NS_IOA 0x10 /* IO base address register */ 742381SN/A#define NS_MA 0x14 /* memory address register */ 759031SN/A#define NS_MA1 0x18 /* memory address high dword register */ 769036SN/A#define NS_SID 0x2C /* subsystem identification register */ 772381SN/A#define NS_ROM 0x30 /* boot ROM configuration register */ 789091SN/A#define NS_CAPPTR 0x34 /* number of tx descriptors */ 7910405Sandreas.hansson@arm.com#define NS_INT 0x3C /* interrupt select register */ 8010405Sandreas.hansson@arm.com#define NS_PMCAP 0x40 /* power mgmt capabilities register */ 8110405Sandreas.hansson@arm.com#define NS_PMCS 0x44 /* power mgmt control and status 8210405Sandreas.hansson@arm.com register */ 8310405Sandreas.hansson@arm.com/* Operational Register Map */ 8410405Sandreas.hansson@arm.com#define CR 0x00 859093SN/A#define CFG 0x04 869093SN/A#define MEAR 0x08 8710405Sandreas.hansson@arm.com#define PTSCR 0x0c 8810405Sandreas.hansson@arm.com#define ISR 0x10 8910405Sandreas.hansson@arm.com#define IMR 0x14 9010405Sandreas.hansson@arm.com#define IER 0x18 919091SN/A#define IHR 0x1c 929715SN/A#define TXDP 0x20 939342SN/A#define TXDP_HI 0x24 949092SN/A#define TXCFG 0x28 959091SN/A#define GPIOR 0x2c 969092SN/A#define RXDP 0x30 979092SN/A#define RXDP_HI 0x34 989092SN/A#define RXCFG 0x38 9910405Sandreas.hansson@arm.com#define PQCR 0x3c 10010405Sandreas.hansson@arm.com#define WCSR 0x40 1019092SN/A#define PCR 0x44 1029715SN/A#define RFCR 0x48 10310405Sandreas.hansson@arm.com#define RFDR 0x4c 1049092SN/A#define BRAR 0x50 1059092SN/A#define BRDR 0x54 10610405Sandreas.hansson@arm.com#define SRR 0x58 1079092SN/A#define MIBC 0x5c 1089092SN/A#define MIB_START 0x60 10910405Sandreas.hansson@arm.com#define MIB_END 0x88 1109092SN/A#define VRCR 0xbc 1119092SN/A#define VTCR 0xc0 1129092SN/A#define VDR 0xc4 1139092SN/A#define CCSR 0xcc 1149092SN/A#define TBICR 0xe0 1159092SN/A#define TBISR 0xe4 1169092SN/A#define TANAR 0xe8 11711168Sandreas.hansson@arm.com#define TANLPAR 0xec 1189092SN/A#define TANER 0xf0 1199092SN/A#define TESR 0xf4 12010405Sandreas.hansson@arm.com#define LAST 0xf4 1219092SN/A#define RESERVED 0xfc 12210405Sandreas.hansson@arm.com 1239092SN/A/* chip command register */ 1249092SN/A#define CR_TXE 0x00000001 1259092SN/A#define CR_TXD 0x00000002 12610405Sandreas.hansson@arm.com#define CR_RXE 0x00000004 1279092SN/A#define CR_RXD 0x00000008 1289612SN/A#define CR_TXR 0x00000010 1299714SN/A#define CR_RXR 0x00000020 1309092SN/A#define CR_SWI 0x00000080 1319612SN/A#define CR_RST 0x00000100 1329092SN/A 13310405Sandreas.hansson@arm.com/* configuration register */ 1349092SN/A#define CFG_LNKSTS 0x80000000 1359715SN/A#define CFG_SPDSTS 0x60000000 1369092SN/A#define CFG_SPDSTS1 0x40000000 1379092SN/A#define CFG_SPDSTS0 0x20000000 1389092SN/A#define CFG_DUPSTS 0x10000000 1399092SN/A#define CFG_TBI_EN 0x01000000 14010405Sandreas.hansson@arm.com#define CFG_RESERVED 0x0e000000 1419092SN/A#define CFG_MODE_1000 0x00400000 1429092SN/A#define CFG_AUTO_1000 0x00200000 1439092SN/A#define CFG_PINT_CTL 0x001c0000 1449092SN/A#define CFG_PINT_DUPSTS 0x00100000 1459092SN/A#define CFG_PINT_LNKSTS 0x00080000 1469092SN/A#define CFG_PINT_SPDSTS 0x00040000 1479092SN/A#define CFG_TMRTEST 0x00020000 1489092SN/A#define CFG_MRM_DIS 0x00010000 14910405Sandreas.hansson@arm.com#define CFG_MWI_DIS 0x00008000 1509092SN/A#define CFG_T64ADDR 0x00004000 1519092SN/A#define CFG_PCI64_DET 0x00002000 1529612SN/A#define CFG_DATA64_EN 0x00001000 1539092SN/A#define CFG_M64ADDR 0x00000800 1549092SN/A#define CFG_PHY_RST 0x00000400 1559715SN/A#define CFG_PHY_DIS 0x00000200 1569092SN/A#define CFG_EXTSTS_EN 0x00000100 15710405Sandreas.hansson@arm.com#define CFG_REQALG 0x00000080 1589092SN/A#define CFG_SB 0x00000040 1599092SN/A#define CFG_POW 0x00000020 1609092SN/A#define CFG_EXD 0x00000010 1619612SN/A#define CFG_PESEL 0x00000008 1629092SN/A#define CFG_BROM_DIS 0x00000004 1639092SN/A#define CFG_EXT_125 0x00000002 1649092SN/A#define CFG_BEM 0x00000001 1659092SN/A 1669092SN/A/* EEPROM access register */ 1679612SN/A#define MEAR_EEDI 0x00000001 1689092SN/A#define MEAR_EEDO 0x00000002 1699092SN/A#define MEAR_EECLK 0x00000004 1709092SN/A#define MEAR_EESEL 0x00000008 1719715SN/A#define MEAR_MDIO 0x00000010 1729092SN/A#define MEAR_MDDIR 0x00000020 1739712SN/A#define MEAR_MDC 0x00000040 1749712SN/A 1759712SN/A/* PCI test control register */ 1769712SN/A#define PTSCR_EEBIST_FAIL 0x00000001 1779712SN/A#define PTSCR_EEBIST_EN 0x00000002 17810713Sandreas.hansson@arm.com#define PTSCR_EELOAD_EN 0x00000004 17910713Sandreas.hansson@arm.com#define PTSCR_RBIST_FAIL 0x000001b8 18010713Sandreas.hansson@arm.com#define PTSCR_RBIST_DONE 0x00000200 18110713Sandreas.hansson@arm.com#define PTSCR_RBIST_EN 0x00000400 18210713Sandreas.hansson@arm.com#define PTSCR_RBIST_RST 0x00002000 18310713Sandreas.hansson@arm.com#define PTSCR_RBIST_RDONLY 0x000003f9 18410713Sandreas.hansson@arm.com 18510713Sandreas.hansson@arm.com/* interrupt status register */ 18610713Sandreas.hansson@arm.com#define ISR_RESERVE 0x80000000 18710713Sandreas.hansson@arm.com#define ISR_TXDESC3 0x40000000 1889092SN/A#define ISR_TXDESC2 0x20000000 1899092SN/A#define ISR_TXDESC1 0x10000000 1909715SN/A#define ISR_TXDESC0 0x08000000 1919715SN/A#define ISR_RXDESC3 0x04000000 1929715SN/A#define ISR_RXDESC2 0x02000000 19310405Sandreas.hansson@arm.com#define ISR_RXDESC1 0x01000000 19410405Sandreas.hansson@arm.com#define ISR_RXDESC0 0x00800000 1959092SN/A#define ISR_TXRCMP 0x00400000 1969092SN/A#define ISR_RXRCMP 0x00200000 1979092SN/A#define ISR_DPERR 0x00100000 1989092SN/A#define ISR_SSERR 0x00080000 1999092SN/A#define ISR_RMABT 0x00040000 20010405Sandreas.hansson@arm.com#define ISR_RTABT 0x00020000 20110405Sandreas.hansson@arm.com#define ISR_RXSOVR 0x00010000 20210405Sandreas.hansson@arm.com#define ISR_HIBINT 0x00008000 2039092SN/A#define ISR_PHY 0x00004000 2049092SN/A#define ISR_PME 0x00002000 20510405Sandreas.hansson@arm.com#define ISR_SWI 0x00001000 2069092SN/A#define ISR_MIB 0x00000800 20710405Sandreas.hansson@arm.com#define ISR_TXURN 0x00000400 2089612SN/A#define ISR_TXIDLE 0x00000200 20910405Sandreas.hansson@arm.com#define ISR_TXERR 0x00000100 2109092SN/A#define ISR_TXDESC 0x00000080 2119092SN/A#define ISR_TXOK 0x00000040 21210405Sandreas.hansson@arm.com#define ISR_RXORN 0x00000020 2139092SN/A#define ISR_RXIDLE 0x00000010 2149092SN/A#define ISR_RXEARLY 0x00000008 2159092SN/A#define ISR_RXERR 0x00000004 2169092SN/A#define ISR_RXDESC 0x00000002 21710405Sandreas.hansson@arm.com#define ISR_RXOK 0x00000001 2189092SN/A#define ISR_ALL 0x7FFFFFFF 2199092SN/A#define ISR_NODELAY (ISR_ALL & ~(ISR_RXOK|ISR_RXDESC|ISR_TXOK|ISR_TXDESC)) 2209092SN/A#define ISR_NOIMPL (~(ISR_SWI|ISR_TXIDLE|ISR_TXDESC|ISR_TXOK|ISR_RXORN| \ 2219612SN/A ISR_RXIDLE|ISR_RXDESC|ISR_RXOK)) 2229612SN/A 2239092SN/A/* transmit configuration register */ 2249715SN/A#define TXCFG_CSI 0x80000000 2259092SN/A#define TXCFG_HBI 0x40000000 2269092SN/A#define TXCFG_MLB 0x20000000 2279715SN/A#define TXCFG_ATP 0x10000000 2289715SN/A#define TXCFG_ECRETRY 0x00800000 2299612SN/A#define TXCFG_BRST_DIS 0x00080000 2309715SN/A#define TXCFG_MXDMA1024 0x00000000 2319612SN/A#define TXCFG_MXDMA512 0x00700000 2329612SN/A#define TXCFG_MXDMA256 0x00600000 23310405Sandreas.hansson@arm.com#define TXCFG_MXDMA128 0x00500000 2349092SN/A#define TXCFG_MXDMA64 0x00400000 2359092SN/A#define TXCFG_MXDMA32 0x00300000 2369092SN/A#define TXCFG_MXDMA16 0x00200000 2379092SN/A#define TXCFG_MXDMA8 0x00100000 2389092SN/A#define TXCFG_MXDMA 0x00700000 2399092SN/A 2409092SN/A#define TXCFG_FLTH_MASK 0x0000ff00 2419092SN/A#define TXCFG_DRTH_MASK 0x000000ff 2429712SN/A 2439712SN/A/*general purpose I/O control register */ 24410405Sandreas.hansson@arm.com#define GPIOR_GP5_OE 0x00000200 2459712SN/A#define GPIOR_GP4_OE 0x00000100 2469712SN/A#define GPIOR_GP3_OE 0x00000080 2479712SN/A#define GPIOR_GP2_OE 0x00000040 2489712SN/A#define GPIOR_GP1_OE 0x00000020 2499712SN/A#define GPIOR_GP3_OUT 0x00000004 2509092SN/A#define GPIOR_GP1_OUT 0x00000001 2519091SN/A 25210713Sandreas.hansson@arm.com/* receive configuration register */ 25310713Sandreas.hansson@arm.com#define RXCFG_AEP 0x80000000 25410713Sandreas.hansson@arm.com#define RXCFG_ARP 0x40000000 25510713Sandreas.hansson@arm.com#define RXCFG_STRIPCRC 0x20000000 25610713Sandreas.hansson@arm.com#define RXCFG_RX_FD 0x10000000 25710713Sandreas.hansson@arm.com#define RXCFG_ALP 0x08000000 25810713Sandreas.hansson@arm.com#define RXCFG_AIRL 0x04000000 25910713Sandreas.hansson@arm.com#define RXCFG_MXDMA512 0x00700000 26010713Sandreas.hansson@arm.com#define RXCFG_MXDMA 0x00700000 26110713Sandreas.hansson@arm.com#define RXCFG_DRTH 0x0000003e 26210713Sandreas.hansson@arm.com#define RXCFG_DRTH0 0x00000002 26310713Sandreas.hansson@arm.com 26410713Sandreas.hansson@arm.com/* pause control status register */ 26510713Sandreas.hansson@arm.com#define PCR_PSEN (1 << 31) 26610713Sandreas.hansson@arm.com#define PCR_PS_MCAST (1 << 30) 26710713Sandreas.hansson@arm.com#define PCR_PS_DA (1 << 29) 26810713Sandreas.hansson@arm.com#define PCR_STHI_8 (3 << 23) 26910713Sandreas.hansson@arm.com#define PCR_STLO_4 (1 << 23) 27010713Sandreas.hansson@arm.com#define PCR_FFHI_8K (3 << 21) 27110713Sandreas.hansson@arm.com#define PCR_FFLO_4K (1 << 21) 27210713Sandreas.hansson@arm.com#define PCR_PAUSE_CNT 0xFFFE 27310713Sandreas.hansson@arm.com 27410713Sandreas.hansson@arm.com/*receive filter/match control register */ 27510713Sandreas.hansson@arm.com#define RFCR_RFEN 0x80000000 27610713Sandreas.hansson@arm.com#define RFCR_AAB 0x40000000 27710713Sandreas.hansson@arm.com#define RFCR_AAM 0x20000000 27810713Sandreas.hansson@arm.com#define RFCR_AAU 0x10000000 27910713Sandreas.hansson@arm.com#define RFCR_APM 0x08000000 28010713Sandreas.hansson@arm.com#define RFCR_APAT 0x07800000 28110713Sandreas.hansson@arm.com#define RFCR_APAT3 0x04000000 28210713Sandreas.hansson@arm.com#define RFCR_APAT2 0x02000000 28310713Sandreas.hansson@arm.com#define RFCR_APAT1 0x01000000 28410713Sandreas.hansson@arm.com#define RFCR_APAT0 0x00800000 28510713Sandreas.hansson@arm.com#define RFCR_AARP 0x00400000 28610713Sandreas.hansson@arm.com#define RFCR_MHEN 0x00200000 28710713Sandreas.hansson@arm.com#define RFCR_UHEN 0x00100000 28810713Sandreas.hansson@arm.com#define RFCR_ULM 0x00080000 28910713Sandreas.hansson@arm.com#define RFCR_RFADDR 0x000003ff 29010713Sandreas.hansson@arm.com 29110713Sandreas.hansson@arm.com/* receive filter/match data register */ 29210713Sandreas.hansson@arm.com#define RFDR_BMASK 0x00030000 29310713Sandreas.hansson@arm.com#define RFDR_RFDATA0 0x000000ff 29410713Sandreas.hansson@arm.com#define RFDR_RFDATA1 0x0000ff00 29510713Sandreas.hansson@arm.com 29610713Sandreas.hansson@arm.com/* management information base control register */ 29710713Sandreas.hansson@arm.com#define MIBC_MIBS 0x00000008 29810713Sandreas.hansson@arm.com#define MIBC_ACLR 0x00000004 29910713Sandreas.hansson@arm.com#define MIBC_FRZ 0x00000002 30010713Sandreas.hansson@arm.com#define MIBC_WRN 0x00000001 30110713Sandreas.hansson@arm.com 30210713Sandreas.hansson@arm.com/* VLAN/IP receive control register */ 30310713Sandreas.hansson@arm.com#define VRCR_RUDPE 0x00000080 30410713Sandreas.hansson@arm.com#define VRCR_RTCPE 0x00000040 30510713Sandreas.hansson@arm.com#define VRCR_RIPE 0x00000020 30610713Sandreas.hansson@arm.com#define VRCR_IPEN 0x00000010 30710713Sandreas.hansson@arm.com#define VRCR_DUTF 0x00000008 30810713Sandreas.hansson@arm.com#define VRCR_DVTF 0x00000004 30910713Sandreas.hansson@arm.com#define VRCR_VTREN 0x00000002 31010719SMarco.Balboni@ARM.com#define VRCR_VTDEN 0x00000001 31110719SMarco.Balboni@ARM.com 31210719SMarco.Balboni@ARM.com/* VLAN/IP transmit control register */ 31310719SMarco.Balboni@ARM.com#define VTCR_PPCHK 0x00000008 31410719SMarco.Balboni@ARM.com#define VTCR_GCHK 0x00000004 31510719SMarco.Balboni@ARM.com#define VTCR_VPPTI 0x00000002 31610719SMarco.Balboni@ARM.com#define VTCR_VGTI 0x00000001 31710719SMarco.Balboni@ARM.com 31810719SMarco.Balboni@ARM.com/* Clockrun Control/Status Register */ 31910405Sandreas.hansson@arm.com#define CCSR_CLKRUN_EN 0x00000001 3209240SN/A 3214475SN/A/* TBI control register */ 3229235SN/A#define TBICR_MR_LOOPBACK 0x00004000 3234475SN/A#define TBICR_MR_AN_ENABLE 0x00001000 32410656Sandreas.hansson@arm.com#define TBICR_MR_RESTART_AN 0x00000200 32510656Sandreas.hansson@arm.com 32610656Sandreas.hansson@arm.com/* TBI status register */ 32710656Sandreas.hansson@arm.com#define TBISR_MR_LINK_STATUS 0x00000020 32810656Sandreas.hansson@arm.com#define TBISR_MR_AN_COMPLETE 0x00000004 32910656Sandreas.hansson@arm.com 33011168Sandreas.hansson@arm.com/* TBI auto-negotiation advertisement register */ 33110656Sandreas.hansson@arm.com#define TANAR_PS2 0x00000100 33210405Sandreas.hansson@arm.com#define TANAR_PS1 0x00000080 33310405Sandreas.hansson@arm.com#define TANAR_HALF_DUP 0x00000040 3349564SN/A#define TANAR_FULL_DUP 0x00000020 3359279SN/A 3364475SN/A/* 3378948SN/A * descriptor format currently assuming link and bufptr 33810405Sandreas.hansson@arm.com * are set for 32 bits,( may be wrong ) ASSUME32 33910405Sandreas.hansson@arm.com */ 3409032SN/Astruct ns_desc { 3419032SN/A uint32_t link; /* link field to next descriptor in linked list */ 3429032SN/A uint32_t bufptr; /* pointer to the first fragment or buffer */ 34311186Serfan.azarkhish@unibo.it uint32_t cmdsts; /* command/status field */ 3444475SN/A uint32_t extsts; /* extended status field for VLAN and IP info */ 34510405Sandreas.hansson@arm.com}; 34610405Sandreas.hansson@arm.com 34710405Sandreas.hansson@arm.com/* cmdsts flags for descriptors */ 3484475SN/A#define CMDSTS_OWN 0x80000000 3494894SN/A#define CMDSTS_MORE 0x40000000 3504475SN/A#define CMDSTS_INTR 0x20000000 3519031SN/A#define CMDSTS_ERR 0x10000000 3524475SN/A#define CMDSTS_OK 0x08000000 3534958SN/A#define CMDSTS_LEN_MASK 0x0000ffff 3544958SN/A 3554958SN/A#define CMDSTS_DEST_MASK 0x01800000 3569031SN/A#define CMDSTS_DEST_SELF 0x00800000 3579279SN/A#define CMDSTS_DEST_MULTI 0x01000000 3584958SN/A 3594958SN/A/* extended flags for descriptors */ 3604958SN/A#define EXTSTS_UDPERR 0x00400000 3614958SN/A#define EXTSTS_UDPPKT 0x00200000 3624958SN/A#define EXTSTS_TCPERR 0x00100000 3634958SN/A#define EXTSTS_TCPPKT 0x00080000 3649279SN/A#define EXTSTS_IPERR 0x00040000 3659405SN/A#define EXTSTS_IPPKT 0x00020000 3664963SN/A 3674963SN/A 3689405SN/A/* speed status */ 3694963SN/A#define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0)) 3704963SN/A 3719405SN/A#endif /* __DEV_NS_GIGE_REG_H__ */ 3724963SN/A