ns_gige_reg.h revision 1057
1/* 2 * Copyright (c) 2004 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/* Portions of code taken from: */ 30 31/* ns83820.c by Benjamin LaHaise with contributions. 32 * 33 * Questions/comments/discussion to linux-ns83820@kvack.org. 34 * 35 * $Revision: 1.34.2.23 $ 36 * 37 * Copyright 2001 Benjamin LaHaise. 38 * Copyright 2001, 2002 Red Hat. 39 * 40 * Mmmm, chocolate vanilla mocha... 41 * 42 * 43 * This program is free software; you can redistribute it and/or modify 44 * it under the terms of the GNU General Public License as published by 45 * the Free Software Foundation; either version 2 of the License, or 46 * (at your option) any later version. 47 * 48 * This program is distributed in the hope that it will be useful, 49 * but WITHOUT ANY WARRANTY; without even the implied warranty of 50 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 51 * GNU General Public License for more details. 52 * 53 * You should have received a copy of the GNU General Public License 54 * along with this program; if not, write to the Free Software 55 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 56 */ 57 58/* @file 59 * Ethernet device register definitions for the National 60 * Semiconductor DP83820 Ethernet controller 61 */ 62 63#ifndef __DEV_NS_GIGE_REG_H__ 64#define __DEV_NS_GIGE_REG_H__ 65 66/* 67 * Configuration Register Map 68 */ 69#define NS_ID 0x00 /* identification register */ 70#define NS_CS 0x04 /* command and status register */ 71#define NS_RID 0x08 /* revision ID register */ 72#define NS_LAT 0x0C /* latency timer register */ 73#define NS_IOA 0x10 /* IO base address register */ 74#define NS_MA 0x14 /* memory address register */ 75#define NS_MA1 0x18 /* memory address high dword register */ 76#define NS_SID 0x2C /* subsystem identification register */ 77#define NS_ROM 0x30 /* boot ROM configuration register */ 78#define NS_CAPPTR 0x34 /* number of tx descriptors */ 79#define NS_INT 0x3C /* interrupt select register */ 80#define NS_PMCAP 0x40 /* power mgmt capabilities register */ 81#define NS_PMCS 0x44 /* power mgmt control and status 82 register */ 83/* Operational Register Map */ 84#define CR 0x00 85#define CFG 0x04 86#define MEAR 0x08 87#define PTSCR 0x0c 88#define ISR 0x10 89#define IMR 0x14 90#define IER 0x18 91#define IHR 0x1c 92#define TXDP 0x20 93#define TXDP_HI 0x24 94#define TXCFG 0x28 95#define GPIOR 0x2c 96#define RXDP 0x30 97#define RXDP_HI 0x34 98#define RXCFG 0x38 99#define PQCR 0x3c 100#define WCSR 0x40 101#define PCR 0x44 102#define RFCR 0x48 103#define RFDR 0x4c 104#define BRAR 0x50 105#define BRDR 0x54 106#define SRR 0x58 107#define MIBC 0x5c 108#define MIB_START 0x60 109#define MIB_END 0x88 110#define VRCR 0xbc 111#define VTCR 0xc0 112#define VDR 0xc4 113#define CCSR 0xcc 114#define TBICR 0xe0 115#define TBISR 0xe4 116#define TANAR 0xe8 117#define TANLPAR 0xec 118#define TANER 0xf0 119#define TESR 0xf4 120#define LAST 0xf4 121#define RESERVED 0xfc 122 123/* chip command register */ 124#define CR_TXE 0x00000001 125#define CR_TXD 0x00000002 126#define CR_RXE 0x00000004 127#define CR_RXD 0x00000008 128#define CR_TXR 0x00000010 129#define CR_RXR 0x00000020 130#define CR_SWI 0x00000080 131#define CR_RST 0x00000100 132 133/* configuration register */ 134#define CFG_LNKSTS 0x80000000 135#define CFG_SPDSTS 0x60000000 136#define CFG_SPDSTS1 0x40000000 137#define CFG_SPDSTS0 0x20000000 138#define CFG_DUPSTS 0x10000000 139#define CFG_TBI_EN 0x01000000 140#define CFG_RESERVED 0x0e000000 141#define CFG_MODE_1000 0x00400000 142#define CFG_AUTO_1000 0x00200000 143#define CFG_PINT_CTL 0x001c0000 144#define CFG_PINT_DUPSTS 0x00100000 145#define CFG_PINT_LNKSTS 0x00080000 146#define CFG_PINT_SPDSTS 0x00040000 147#define CFG_TMRTEST 0x00020000 148#define CFG_MRM_DIS 0x00010000 149#define CFG_MWI_DIS 0x00008000 150#define CFG_T64ADDR 0x00004000 151#define CFG_PCI64_DET 0x00002000 152#define CFG_DATA64_EN 0x00001000 153#define CFG_M64ADDR 0x00000800 154#define CFG_PHY_RST 0x00000400 155#define CFG_PHY_DIS 0x00000200 156#define CFG_EXTSTS_EN 0x00000100 157#define CFG_REQALG 0x00000080 158#define CFG_SB 0x00000040 159#define CFG_POW 0x00000020 160#define CFG_EXD 0x00000010 161#define CFG_PESEL 0x00000008 162#define CFG_BROM_DIS 0x00000004 163#define CFG_EXT_125 0x00000002 164#define CFG_BEM 0x00000001 165 166/* EEPROM access register */ 167#define MEAR_EEDI 0x00000001 168#define MEAR_EEDO 0x00000002 169#define MEAR_EECLK 0x00000004 170#define MEAR_EESEL 0x00000008 171#define MEAR_MDIO 0x00000010 172#define MEAR_MDDIR 0x00000020 173#define MEAR_MDC 0x00000040 174 175/* PCI test control register */ 176#define PTSCR_EEBIST_FAIL 0x00000001 177#define PTSCR_EEBIST_EN 0x00000002 178#define PTSCR_EELOAD_EN 0x00000004 179#define PTSCR_RBIST_FAIL 0x000001b8 180#define PTSCR_RBIST_DONE 0x00000200 181#define PTSCR_RBIST_EN 0x00000400 182#define PTSCR_RBIST_RST 0x00002000 183#define PTSCR_RBIST_RDONLY 0x000003f9 184 185/* interrupt status register */ 186#define ISR_RESERVE 0x80000000 187#define ISR_TXDESC3 0x40000000 188#define ISR_TXDESC2 0x20000000 189#define ISR_TXDESC1 0x10000000 190#define ISR_TXDESC0 0x08000000 191#define ISR_RXDESC3 0x04000000 192#define ISR_RXDESC2 0x02000000 193#define ISR_RXDESC1 0x01000000 194#define ISR_RXDESC0 0x00800000 195#define ISR_TXRCMP 0x00400000 196#define ISR_RXRCMP 0x00200000 197#define ISR_DPERR 0x00100000 198#define ISR_SSERR 0x00080000 199#define ISR_RMABT 0x00040000 200#define ISR_RTABT 0x00020000 201#define ISR_RXSOVR 0x00010000 202#define ISR_HIBINT 0x00008000 203#define ISR_PHY 0x00004000 204#define ISR_PME 0x00002000 205#define ISR_SWI 0x00001000 206#define ISR_MIB 0x00000800 207#define ISR_TXURN 0x00000400 208#define ISR_TXIDLE 0x00000200 209#define ISR_TXERR 0x00000100 210#define ISR_TXDESC 0x00000080 211#define ISR_TXOK 0x00000040 212#define ISR_RXORN 0x00000020 213#define ISR_RXIDLE 0x00000010 214#define ISR_RXEARLY 0x00000008 215#define ISR_RXERR 0x00000004 216#define ISR_RXDESC 0x00000002 217#define ISR_RXOK 0x00000001 218#define ISR_ALL 0x7FFFFFFF 219#define ISR_NODELAY (ISR_ALL & ~(ISR_RXOK|ISR_RXDESC|ISR_TXOK|ISR_TXDESC)) 220#define ISR_NOIMPL (~(ISR_SWI|ISR_TXIDLE|ISR_TXDESC|ISR_TXOK|ISR_RXORN| \ 221 ISR_RXIDLE|ISR_RXDESC|ISR_RXOK)) 222 223/* transmit configuration register */ 224#define TXCFG_CSI 0x80000000 225#define TXCFG_HBI 0x40000000 226#define TXCFG_MLB 0x20000000 227#define TXCFG_ATP 0x10000000 228#define TXCFG_ECRETRY 0x00800000 229#define TXCFG_BRST_DIS 0x00080000 230#define TXCFG_MXDMA1024 0x00000000 231#define TXCFG_MXDMA512 0x00700000 232#define TXCFG_MXDMA256 0x00600000 233#define TXCFG_MXDMA128 0x00500000 234#define TXCFG_MXDMA64 0x00400000 235#define TXCFG_MXDMA32 0x00300000 236#define TXCFG_MXDMA16 0x00200000 237#define TXCFG_MXDMA8 0x00100000 238#define TXCFG_MXDMA 0x00700000 239 240#define TXCFG_FLTH_MASK 0x0000ff00 241#define TXCFG_DRTH_MASK 0x000000ff 242 243/*general purpose I/O control register */ 244#define GPIOR_GP5_OE 0x00000200 245#define GPIOR_GP4_OE 0x00000100 246#define GPIOR_GP3_OE 0x00000080 247#define GPIOR_GP2_OE 0x00000040 248#define GPIOR_GP1_OE 0x00000020 249#define GPIOR_GP3_OUT 0x00000004 250#define GPIOR_GP1_OUT 0x00000001 251 252/* receive configuration register */ 253#define RXCFG_AEP 0x80000000 254#define RXCFG_ARP 0x40000000 255#define RXCFG_STRIPCRC 0x20000000 256#define RXCFG_RX_FD 0x10000000 257#define RXCFG_ALP 0x08000000 258#define RXCFG_AIRL 0x04000000 259#define RXCFG_MXDMA512 0x00700000 260#define RXCFG_MXDMA 0x00700000 261#define RXCFG_DRTH 0x0000003e 262#define RXCFG_DRTH0 0x00000002 263 264/* pause control status register */ 265#define PCR_PSEN (1 << 31) 266#define PCR_PS_MCAST (1 << 30) 267#define PCR_PS_DA (1 << 29) 268#define PCR_STHI_8 (3 << 23) 269#define PCR_STLO_4 (1 << 23) 270#define PCR_FFHI_8K (3 << 21) 271#define PCR_FFLO_4K (1 << 21) 272#define PCR_PAUSE_CNT 0xFFFE 273 274/*receive filter/match control register */ 275#define RFCR_RFEN 0x80000000 276#define RFCR_AAB 0x40000000 277#define RFCR_AAM 0x20000000 278#define RFCR_AAU 0x10000000 279#define RFCR_APM 0x08000000 280#define RFCR_APAT 0x07800000 281#define RFCR_APAT3 0x04000000 282#define RFCR_APAT2 0x02000000 283#define RFCR_APAT1 0x01000000 284#define RFCR_APAT0 0x00800000 285#define RFCR_AARP 0x00400000 286#define RFCR_MHEN 0x00200000 287#define RFCR_UHEN 0x00100000 288#define RFCR_ULM 0x00080000 289#define RFCR_RFADDR 0x000003ff 290 291/* receive filter/match data register */ 292#define RFDR_BMASK 0x00030000 293#define RFDR_RFDATA0 0x000000ff 294#define RFDR_RFDATA1 0x0000ff00 295 296/* management information base control register */ 297#define MIBC_MIBS 0x00000008 298#define MIBC_ACLR 0x00000004 299#define MIBC_FRZ 0x00000002 300#define MIBC_WRN 0x00000001 301 302/* VLAN/IP receive control register */ 303#define VRCR_RUDPE 0x00000080 304#define VRCR_RTCPE 0x00000040 305#define VRCR_RIPE 0x00000020 306#define VRCR_IPEN 0x00000010 307#define VRCR_DUTF 0x00000008 308#define VRCR_DVTF 0x00000004 309#define VRCR_VTREN 0x00000002 310#define VRCR_VTDEN 0x00000001 311 312/* VLAN/IP transmit control register */ 313#define VTCR_PPCHK 0x00000008 314#define VTCR_GCHK 0x00000004 315#define VTCR_VPPTI 0x00000002 316#define VTCR_VGTI 0x00000001 317 318/* Clockrun Control/Status Register */ 319#define CCSR_CLKRUN_EN 0x00000001 320 321/* TBI control register */ 322#define TBICR_MR_LOOPBACK 0x00004000 323#define TBICR_MR_AN_ENABLE 0x00001000 324#define TBICR_MR_RESTART_AN 0x00000200 325 326/* TBI status register */ 327#define TBISR_MR_LINK_STATUS 0x00000020 328#define TBISR_MR_AN_COMPLETE 0x00000004 329 330/* TBI auto-negotiation advertisement register */ 331#define TANAR_PS2 0x00000100 332#define TANAR_PS1 0x00000080 333#define TANAR_HALF_DUP 0x00000040 334#define TANAR_FULL_DUP 0x00000020 335 336/* 337 * descriptor format currently assuming link and bufptr 338 * are set for 32 bits,( may be wrong ) ASSUME32 339 */ 340struct ns_desc { 341 uint32_t link; /* link field to next descriptor in linked list */ 342 uint32_t bufptr; /* pointer to the first fragment or buffer */ 343 uint32_t cmdsts; /* command/status field */ 344 uint32_t extsts; /* extended status field for VLAN and IP info */ 345}; 346 347/* cmdsts flags for descriptors */ 348#define CMDSTS_OWN 0x80000000 349#define CMDSTS_MORE 0x40000000 350#define CMDSTS_INTR 0x20000000 351#define CMDSTS_ERR 0x10000000 352#define CMDSTS_OK 0x08000000 353#define CMDSTS_LEN_MASK 0x0000ffff 354 355#define CMDSTS_DEST_MASK 0x01800000 356#define CMDSTS_DEST_SELF 0x00800000 357#define CMDSTS_DEST_MULTI 0x01000000 358 359/* extended flags for descriptors */ 360#define EXTSTS_UDPERR 0x00400000 361#define EXTSTS_UDPPKT 0x00200000 362#define EXTSTS_TCPERR 0x00100000 363#define EXTSTS_TCPPKT 0x00080000 364#define EXTSTS_IPERR 0x00040000 365#define EXTSTS_IPPKT 0x00020000 366 367 368/* speed status */ 369#define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0)) 370 371#endif /* __DEV_NS_GIGE_REG_H__ */ 372