i8254xGBe_defs.hh revision 9335
16657Snate@binkert.org/* 26657Snate@binkert.org * Copyright (c) 2006 The Regents of The University of Michigan 310972Sdavid.hashe@amd.com * All rights reserved. 46657Snate@binkert.org * 56657Snate@binkert.org * Redistribution and use in source and binary forms, with or without 66657Snate@binkert.org * modification, are permitted provided that the following conditions are 76657Snate@binkert.org * met: redistributions of source code must retain the above copyright 86657Snate@binkert.org * notice, this list of conditions and the following disclaimer; 96657Snate@binkert.org * redistributions in binary form must reproduce the above copyright 106657Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 116657Snate@binkert.org * documentation and/or other materials provided with the distribution; 126657Snate@binkert.org * neither the name of the copyright holders nor the names of its 136657Snate@binkert.org * contributors may be used to endorse or promote products derived from 146657Snate@binkert.org * this software without specific prior written permission. 156657Snate@binkert.org * 166657Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176657Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186657Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196657Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206657Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216657Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226657Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236657Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246657Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256657Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266657Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276657Snate@binkert.org * 286657Snate@binkert.org * Authors: Ali Saidi 296999Snate@binkert.org */ 306657Snate@binkert.org 316657Snate@binkert.org/* @file 326657Snate@binkert.org * Register and structure descriptions for Intel's 8254x line of gigabit ethernet controllers. 336657Snate@binkert.org */ 348189SLisa.Hsu@amd.com#include "base/bitfield.hh" 356657Snate@binkert.org 369499Snilay@cs.wisc.edunamespace iGbReg { 379499Snilay@cs.wisc.edu 389364Snilay@cs.wisc.edu 397055Snate@binkert.org// Registers used by the Intel GbE NIC 406882SBrad.Beckmann@amd.comconst uint32_t REG_CTRL = 0x00000; 416882SBrad.Beckmann@amd.comconst uint32_t REG_STATUS = 0x00008; 428191SLisa.Hsu@amd.comconst uint32_t REG_EECD = 0x00010; 436882SBrad.Beckmann@amd.comconst uint32_t REG_EERD = 0x00014; 446882SBrad.Beckmann@amd.comconst uint32_t REG_CTRL_EXT = 0x00018; 459102SNuwan.Jayasena@amd.comconst uint32_t REG_MDIC = 0x00020; 4611084Snilay@cs.wisc.educonst uint32_t REG_FCAL = 0x00028; 479366Snilay@cs.wisc.educonst uint32_t REG_FCAH = 0x0002C; 489499Snilay@cs.wisc.educonst uint32_t REG_FCT = 0x00030; 499499Snilay@cs.wisc.educonst uint32_t REG_VET = 0x00038; 509499Snilay@cs.wisc.educonst uint32_t REG_PBA = 0x01000; 516882SBrad.Beckmann@amd.comconst uint32_t REG_ICR = 0x000C0; 526657Snate@binkert.orgconst uint32_t REG_ITR = 0x000C4; 536657Snate@binkert.orgconst uint32_t REG_ICS = 0x000C8; 546657Snate@binkert.orgconst uint32_t REG_IMS = 0x000D0; 556657Snate@binkert.orgconst uint32_t REG_IMC = 0x000D8; 5610311Snilay@cs.wisc.educonst uint32_t REG_IAM = 0x000E0; 5710311Snilay@cs.wisc.educonst uint32_t REG_RCTL = 0x00100; 5810311Snilay@cs.wisc.educonst uint32_t REG_FCTTV = 0x00170; 5910311Snilay@cs.wisc.educonst uint32_t REG_TIPG = 0x00410; 606657Snate@binkert.orgconst uint32_t REG_AIFS = 0x00458; 6110311Snilay@cs.wisc.educonst uint32_t REG_LEDCTL = 0x00e00; 629366Snilay@cs.wisc.educonst uint32_t REG_EICR = 0x01580; 637839Snilay@cs.wisc.educonst uint32_t REG_IVAR0 = 0x01700; 646657Snate@binkert.orgconst uint32_t REG_FCRTL = 0x02160; 656882SBrad.Beckmann@amd.comconst uint32_t REG_FCRTH = 0x02168; 6610308Snilay@cs.wisc.educonst uint32_t REG_RDBAL = 0x02800; 6710308Snilay@cs.wisc.educonst uint32_t REG_RDBAH = 0x02804; 686882SBrad.Beckmann@amd.comconst uint32_t REG_RDLEN = 0x02808; 6910308Snilay@cs.wisc.educonst uint32_t REG_SRRCTL = 0x0280C; 7010308Snilay@cs.wisc.educonst uint32_t REG_RDH = 0x02810; 7110308Snilay@cs.wisc.educonst uint32_t REG_RDT = 0x02818; 7210308Snilay@cs.wisc.educonst uint32_t REG_RDTR = 0x02820; 7310308Snilay@cs.wisc.educonst uint32_t REG_RXDCTL = 0x02828; 749366Snilay@cs.wisc.educonst uint32_t REG_RADV = 0x0282C; 759366Snilay@cs.wisc.educonst uint32_t REG_TCTL = 0x00400; 766657Snate@binkert.orgconst uint32_t REG_TDBAL = 0x03800; 776657Snate@binkert.orgconst uint32_t REG_TDBAH = 0x03804; 786657Snate@binkert.orgconst uint32_t REG_TDLEN = 0x03808; 796657Snate@binkert.orgconst uint32_t REG_TDH = 0x03810; 809104Shestness@cs.utexas.educonst uint32_t REG_TXDCA_CTL = 0x03814; 816657Snate@binkert.orgconst uint32_t REG_TDT = 0x03818; 826657Snate@binkert.orgconst uint32_t REG_TIDV = 0x03820; 836657Snate@binkert.orgconst uint32_t REG_TXDCTL = 0x03828; 8410311Snilay@cs.wisc.educonst uint32_t REG_TADV = 0x0382C; 8510311Snilay@cs.wisc.educonst uint32_t REG_TDWBAL = 0x03838; 8610311Snilay@cs.wisc.educonst uint32_t REG_TDWBAH = 0x0383C; 8710311Snilay@cs.wisc.educonst uint32_t REG_CRCERRS = 0x04000; 886657Snate@binkert.orgconst uint32_t REG_RXCSUM = 0x05000; 897839Snilay@cs.wisc.educonst uint32_t REG_RLPML = 0x05004; 907839Snilay@cs.wisc.educonst uint32_t REG_RFCTL = 0x05008; 9110972Sdavid.hashe@amd.comconst uint32_t REG_MTA = 0x05200; 9210972Sdavid.hashe@amd.comconst uint32_t REG_RAL = 0x05400; 9310972Sdavid.hashe@amd.comconst uint32_t REG_RAH = 0x05404; 946657Snate@binkert.orgconst uint32_t REG_VFTA = 0x05600; 956657Snate@binkert.org 966657Snate@binkert.orgconst uint32_t REG_WUC = 0x05800; 976657Snate@binkert.orgconst uint32_t REG_MANC = 0x05820; 986657Snate@binkert.orgconst uint32_t REG_SWSM = 0x05B50; 996657Snate@binkert.orgconst uint32_t REG_FWSM = 0x05B54; 1006657Snate@binkert.orgconst uint32_t REG_SWFWSYNC = 0x05B5C; 1016657Snate@binkert.org 1026657Snate@binkert.orgconst uint8_t EEPROM_READ_OPCODE_SPI = 0x03; 1036657Snate@binkert.orgconst uint8_t EEPROM_RDSR_OPCODE_SPI = 0x05; 1046657Snate@binkert.orgconst uint8_t EEPROM_SIZE = 64; 1056657Snate@binkert.orgconst uint16_t EEPROM_CSUM = 0xBABA; 1066657Snate@binkert.org 1076657Snate@binkert.orgconst uint8_t VLAN_FILTER_TABLE_SIZE = 128; 1086657Snate@binkert.orgconst uint8_t RCV_ADDRESS_TABLE_SIZE = 24; 1096657Snate@binkert.orgconst uint8_t MULTICAST_TABLE_SIZE = 128; 1106657Snate@binkert.orgconst uint32_t STATS_REGS_SIZE = 0x228; 1116657Snate@binkert.org 1126779SBrad.Beckmann@amd.com 1136657Snate@binkert.org// Registers in that are accessed in the PHY 1146657Snate@binkert.orgconst uint8_t PHY_PSTATUS = 0x1; 1156657Snate@binkert.orgconst uint8_t PHY_PID = 0x2; 1166657Snate@binkert.orgconst uint8_t PHY_EPID = 0x3; 1176657Snate@binkert.orgconst uint8_t PHY_GSTATUS = 10; 1186657Snate@binkert.orgconst uint8_t PHY_EPSTATUS = 15; 1196657Snate@binkert.orgconst uint8_t PHY_AGC = 18; 1206657Snate@binkert.org 1216657Snate@binkert.org// Receive Descriptor Status Flags 12210972Sdavid.hashe@amd.comconst uint16_t RXDS_DYNINT = 0x800; 12310972Sdavid.hashe@amd.comconst uint16_t RXDS_UDPV = 0x400; 12410972Sdavid.hashe@amd.comconst uint16_t RXDS_CRCV = 0x100; 1259104Shestness@cs.utexas.educonst uint16_t RXDS_PIF = 0x080; 1269104Shestness@cs.utexas.educonst uint16_t RXDS_IPCS = 0x040; 1279104Shestness@cs.utexas.educonst uint16_t RXDS_TCPCS = 0x020; 1289104Shestness@cs.utexas.educonst uint16_t RXDS_UDPCS = 0x010; 1296657Snate@binkert.orgconst uint16_t RXDS_VP = 0x008; 1306657Snate@binkert.orgconst uint16_t RXDS_IXSM = 0x004; 1316657Snate@binkert.orgconst uint16_t RXDS_EOP = 0x002; 1326657Snate@binkert.orgconst uint16_t RXDS_DD = 0x001; 1336657Snate@binkert.org 1346657Snate@binkert.org// Receive Descriptor Error Flags 1356657Snate@binkert.orgconst uint8_t RXDE_RXE = 0x80; 1366657Snate@binkert.orgconst uint8_t RXDE_IPE = 0x40; 1376657Snate@binkert.orgconst uint8_t RXDE_TCPE = 0x20; 1386657Snate@binkert.orgconst uint8_t RXDE_SEQ = 0x04; 1396657Snate@binkert.orgconst uint8_t RXDE_SE = 0x02; 1406657Snate@binkert.orgconst uint8_t RXDE_CE = 0x01; 1416657Snate@binkert.org 14210307Snilay@cs.wisc.edu// Receive Descriptor Extended Error Flags 1436657Snate@binkert.orgconst uint16_t RXDEE_HBO = 0x008; 1446657Snate@binkert.orgconst uint16_t RXDEE_CE = 0x010; 1457839Snilay@cs.wisc.educonst uint16_t RXDEE_LE = 0x020; 1467839Snilay@cs.wisc.educonst uint16_t RXDEE_PE = 0x080; 1477839Snilay@cs.wisc.educonst uint16_t RXDEE_OSE = 0x100; 1487839Snilay@cs.wisc.educonst uint16_t RXDEE_USE = 0x200; 1497839Snilay@cs.wisc.educonst uint16_t RXDEE_TCPE = 0x400; 1507839Snilay@cs.wisc.educonst uint16_t RXDEE_IPE = 0x800; 1517839Snilay@cs.wisc.edu 1527839Snilay@cs.wisc.edu 1537839Snilay@cs.wisc.edu// Receive Descriptor Types 1547839Snilay@cs.wisc.educonst uint8_t RXDT_LEGACY = 0x00; 15510968Sdavid.hashe@amd.comconst uint8_t RXDT_ADV_ONEBUF = 0x01; 15610968Sdavid.hashe@amd.comconst uint8_t RXDT_ADV_SPLIT_A = 0x05; 15710968Sdavid.hashe@amd.com 15810968Sdavid.hashe@amd.com// Receive Descriptor Packet Types 15910968Sdavid.hashe@amd.comconst uint16_t RXDP_IPV4 = 0x001; 16010968Sdavid.hashe@amd.comconst uint16_t RXDP_IPV4E = 0x002; 16110968Sdavid.hashe@amd.comconst uint16_t RXDP_IPV6 = 0x004; 1627839Snilay@cs.wisc.educonst uint16_t RXDP_IPV6E = 0x008; 1636657Snate@binkert.orgconst uint16_t RXDP_TCP = 0x010; 1646657Snate@binkert.orgconst uint16_t RXDP_UDP = 0x020; 1656657Snate@binkert.orgconst uint16_t RXDP_SCTP = 0x040; 1666657Snate@binkert.orgconst uint16_t RXDP_NFS = 0x080; 1676657Snate@binkert.org 1686657Snate@binkert.org// Interrupt types 1696657Snate@binkert.orgenum IntTypes 1706657Snate@binkert.org{ 1716657Snate@binkert.org IT_NONE = 0x00000, //dummy value 1726657Snate@binkert.org IT_TXDW = 0x00001, 1736657Snate@binkert.org IT_TXQE = 0x00002, 1746657Snate@binkert.org IT_LSC = 0x00004, 1756657Snate@binkert.org IT_RXSEQ = 0x00008, 1766657Snate@binkert.org IT_RXDMT = 0x00010, 1776657Snate@binkert.org IT_RXO = 0x00040, 1786657Snate@binkert.org IT_RXT = 0x00080, 1796657Snate@binkert.org IT_MADC = 0x00200, 1806657Snate@binkert.org IT_RXCFG = 0x00400, 1816657Snate@binkert.org IT_GPI0 = 0x02000, 1826657Snate@binkert.org IT_GPI1 = 0x04000, 1836657Snate@binkert.org IT_TXDLOW = 0x08000, 1846657Snate@binkert.org IT_SRPD = 0x10000, 1856657Snate@binkert.org IT_ACK = 0x20000 1866657Snate@binkert.org}; 1876657Snate@binkert.org 1886657Snate@binkert.org// Receive Descriptor struct 1896657Snate@binkert.orgstruct RxDesc { 1906657Snate@binkert.org union { 1916657Snate@binkert.org struct { 1926657Snate@binkert.org Addr buf; 19310963Sdavid.hashe@amd.com uint16_t len; 19410963Sdavid.hashe@amd.com uint16_t csum; 19510963Sdavid.hashe@amd.com uint8_t status; 19610963Sdavid.hashe@amd.com uint8_t errors; 19710963Sdavid.hashe@amd.com uint16_t vlan; 19810963Sdavid.hashe@amd.com } legacy; 19911095Snilay@cs.wisc.edu struct { 20010963Sdavid.hashe@amd.com Addr pkt; 20110963Sdavid.hashe@amd.com Addr hdr; 20210963Sdavid.hashe@amd.com } adv_read; 20310963Sdavid.hashe@amd.com struct { 20410963Sdavid.hashe@amd.com uint16_t rss_type:4; 20510963Sdavid.hashe@amd.com uint16_t pkt_type:12; 20610963Sdavid.hashe@amd.com uint16_t __reserved1:5; 20710963Sdavid.hashe@amd.com uint16_t header_len:10; 2089219Spower.jg@gmail.com uint16_t sph:1; 2096877Ssteve.reinhardt@amd.com union { 2106657Snate@binkert.org struct { 2119219Spower.jg@gmail.com uint16_t id; 2126657Snate@binkert.org uint16_t csum; 2139219Spower.jg@gmail.com }; 2146657Snate@binkert.org uint32_t rss_hash; 2156877Ssteve.reinhardt@amd.com }; 2166999Snate@binkert.org uint32_t status:20; 2176877Ssteve.reinhardt@amd.com uint32_t errors:12; 21810308Snilay@cs.wisc.edu uint16_t pkt_len; 2196877Ssteve.reinhardt@amd.com uint16_t vlan_tag; 2206877Ssteve.reinhardt@amd.com } adv_wb ; 22110308Snilay@cs.wisc.edu }; 2226877Ssteve.reinhardt@amd.com}; 2236877Ssteve.reinhardt@amd.com 2246877Ssteve.reinhardt@amd.comstruct TxDesc { 2256877Ssteve.reinhardt@amd.com uint64_t d1; 2266877Ssteve.reinhardt@amd.com uint64_t d2; 2276877Ssteve.reinhardt@amd.com}; 2286877Ssteve.reinhardt@amd.com 2299338SAndreas.Sandberg@arm.comnamespace TxdOp { 2306877Ssteve.reinhardt@amd.comconst uint8_t TXD_CNXT = 0x0; 2316877Ssteve.reinhardt@amd.comconst uint8_t TXD_DATA = 0x1; 2326877Ssteve.reinhardt@amd.comconst uint8_t TXD_ADVCNXT = 0x2; 2336877Ssteve.reinhardt@amd.comconst uint8_t TXD_ADVDATA = 0x3; 23410308Snilay@cs.wisc.edu 23510308Snilay@cs.wisc.eduinline bool isLegacy(TxDesc *d) { return !bits(d->d2,29,29); } 23610308Snilay@cs.wisc.eduinline uint8_t getType(TxDesc *d) { return bits(d->d2, 23,20); } 23710308Snilay@cs.wisc.eduinline bool isType(TxDesc *d, uint8_t type) { return getType(d) == type; } 23811084Snilay@cs.wisc.eduinline bool isTypes(TxDesc *d, uint8_t t1, uint8_t t2) { return isType(d, t1) || isType(d, t2); } 2396882SBrad.Beckmann@amd.cominline bool isAdvDesc(TxDesc *d) { return !isLegacy(d) && isTypes(d, TXD_ADVDATA,TXD_ADVCNXT); } 24010308Snilay@cs.wisc.eduinline bool isContext(TxDesc *d) { return !isLegacy(d) && isTypes(d,TXD_CNXT, TXD_ADVCNXT); } 24110308Snilay@cs.wisc.eduinline bool isData(TxDesc *d) { return !isLegacy(d) && isTypes(d, TXD_DATA, TXD_ADVDATA); } 2426882SBrad.Beckmann@amd.com 2436882SBrad.Beckmann@amd.cominline Addr getBuf(TxDesc *d) { assert(isLegacy(d) || isData(d)); return d->d1; } 2446882SBrad.Beckmann@amd.cominline Addr getLen(TxDesc *d) { if (isLegacy(d)) return bits(d->d2,15,0); else return bits(d->d2, 19,0); } 2456882SBrad.Beckmann@amd.cominline void setDd(TxDesc *d) { replaceBits(d->d2, 35, 32, ULL(1)); } 24611021Sjthestness@gmail.com 2476877Ssteve.reinhardt@amd.cominline bool ide(TxDesc *d) { return bits(d->d2, 31,31) && (getType(d) == TXD_DATA || isLegacy(d)); } 2486877Ssteve.reinhardt@amd.cominline bool vle(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 30,30); } 24910917Sbrandon.potter@amd.cominline bool rs(TxDesc *d) { return bits(d->d2, 27,27); } 2506877Ssteve.reinhardt@amd.cominline bool ic(TxDesc *d) { assert(isLegacy(d) || isData(d)); return isLegacy(d) && bits(d->d2, 26,26); } 2516657Snate@binkert.orginline bool tse(TxDesc *d) { 2526657Snate@binkert.org if (isTypes(d, TXD_CNXT, TXD_DATA)) 2536999Snate@binkert.org return bits(d->d2, 26,26); 2546657Snate@binkert.org if (isType(d, TXD_ADVDATA)) 2556657Snate@binkert.org return bits(d->d2, 31, 31); 2566657Snate@binkert.org return false; 2576657Snate@binkert.org} 2587007Snate@binkert.org 2596657Snate@binkert.orginline bool ifcs(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 25,25); } 2606657Snate@binkert.orginline bool eop(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 24,24); } 2616657Snate@binkert.orginline bool ip(TxDesc *d) { assert(isContext(d)); return bits(d->d2, 25,25); } 2626657Snate@binkert.orginline bool tcp(TxDesc *d) { assert(isContext(d)); return bits(d->d2, 24,24); } 2636657Snate@binkert.org 2647007Snate@binkert.orginline uint8_t getCso(TxDesc *d) { assert(isLegacy(d)); return bits(d->d2, 23,16); } 2657007Snate@binkert.orginline uint8_t getCss(TxDesc *d) { assert(isLegacy(d)); return bits(d->d2, 47,40); } 2666657Snate@binkert.org 2677002Snate@binkert.orginline bool ixsm(TxDesc *d) { return isData(d) && bits(d->d2, 40,40); } 2687002Snate@binkert.orginline bool txsm(TxDesc *d) { return isData(d) && bits(d->d2, 41,41); } 2697002Snate@binkert.org 2707002Snate@binkert.orginline int tucse(TxDesc *d) { assert(isContext(d)); return bits(d->d1,63,48); } 2716657Snate@binkert.orginline int tucso(TxDesc *d) { assert(isContext(d)); return bits(d->d1,47,40); } 2726657Snate@binkert.orginline int tucss(TxDesc *d) { assert(isContext(d)); return bits(d->d1,39,32); } 2738229Snate@binkert.orginline int ipcse(TxDesc *d) { assert(isContext(d)); return bits(d->d1,31,16); } 2748229Snate@binkert.orginline int ipcso(TxDesc *d) { assert(isContext(d)); return bits(d->d1,15,8); } 2758229Snate@binkert.orginline int ipcss(TxDesc *d) { assert(isContext(d)); return bits(d->d1,7,0); } 27610972Sdavid.hashe@amd.cominline int mss(TxDesc *d) { assert(isContext(d)); return bits(d->d2,63,48); } 2776657Snate@binkert.orginline int hdrlen(TxDesc *d) { 2786657Snate@binkert.org assert(isContext(d)); 2796657Snate@binkert.org if (!isAdvDesc(d)) 2806657Snate@binkert.org return bits(d->d2,47,40); 2816793SBrad.Beckmann@amd.com return bits(d->d2, 47,40) + bits(d->d1, 8,0) + bits(d->d1, 15, 9); 2826657Snate@binkert.org} 28310311Snilay@cs.wisc.edu 2846657Snate@binkert.orginline int getTsoLen(TxDesc *d) { assert(isType(d, TXD_ADVDATA)); return bits(d->d2, 63,46); } 2856657Snate@binkert.orginline int utcmd(TxDesc *d) { assert(isContext(d)); return bits(d->d2,24,31); } 2866657Snate@binkert.org} // namespace TxdOp 2877002Snate@binkert.org 2886657Snate@binkert.org 2897007Snate@binkert.org#define ADD_FIELD32(NAME, OFFSET, BITS) \ 2907007Snate@binkert.org inline uint32_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \ 2919271Snilay@cs.wisc.edu inline void NAME(uint32_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); } 2926877Ssteve.reinhardt@amd.com 2936877Ssteve.reinhardt@amd.com#define ADD_FIELD64(NAME, OFFSET, BITS) \ 2946657Snate@binkert.org inline uint64_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \ 2956877Ssteve.reinhardt@amd.com inline void NAME(uint64_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); } 29610311Snilay@cs.wisc.edu 29711084Snilay@cs.wisc.edustruct Regs { 29811084Snilay@cs.wisc.edu template<class T> 29911021Sjthestness@gmail.com struct Reg { 3009745Snilay@cs.wisc.edu T _data; 3017002Snate@binkert.org T operator()() { return _data; } 3026657Snate@binkert.org const Reg<T> &operator=(T d) { _data = d; return *this;} 30310012Snilay@cs.wisc.edu bool operator==(T d) { return d == _data; } 3049745Snilay@cs.wisc.edu void operator()(T d) { _data = d; } 3059745Snilay@cs.wisc.edu Reg() { _data = 0; } 3069745Snilay@cs.wisc.edu void serialize(std::ostream &os) 3078683Snilay@cs.wisc.edu { 3088683Snilay@cs.wisc.edu SERIALIZE_SCALAR(_data); 3097007Snate@binkert.org } 31010524Snilay@cs.wisc.edu void unserialize(Checkpoint *cp, const std::string §ion) 3119302Snilay@cs.wisc.edu { 3129745Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(_data); 3139745Snilay@cs.wisc.edu } 31411061Snilay@cs.wisc.edu }; 3159745Snilay@cs.wisc.edu 31611061Snilay@cs.wisc.edu struct CTRL : public Reg<uint32_t> { // 0x0000 CTRL Register 3179745Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 3186657Snate@binkert.org ADD_FIELD32(fd,0,1); // full duplex 3196657Snate@binkert.org ADD_FIELD32(bem,1,1); // big endian mode 3206657Snate@binkert.org ADD_FIELD32(pcipr,2,1); // PCI priority 3216657Snate@binkert.org ADD_FIELD32(lrst,3,1); // link reset 3226657Snate@binkert.org ADD_FIELD32(tme,4,1); // test mode enable 3236657Snate@binkert.org ADD_FIELD32(asde,5,1); // Auto-speed detection 3246882SBrad.Beckmann@amd.com ADD_FIELD32(slu,6,1); // Set link up 3256882SBrad.Beckmann@amd.com ADD_FIELD32(ilos,7,1); // invert los-of-signal 3266882SBrad.Beckmann@amd.com ADD_FIELD32(speed,8,2); // speed selection bits 3276882SBrad.Beckmann@amd.com ADD_FIELD32(be32,10,1); // big endian mode 32 3286657Snate@binkert.org ADD_FIELD32(frcspd,11,1); // force speed 3296657Snate@binkert.org ADD_FIELD32(frcdpx,12,1); // force duplex 3307007Snate@binkert.org ADD_FIELD32(duden,13,1); // dock/undock enable 3317839Snilay@cs.wisc.edu ADD_FIELD32(dudpol,14,1); // dock/undock polarity 3327839Snilay@cs.wisc.edu ADD_FIELD32(fphyrst,15,1); // force phy reset 3337839Snilay@cs.wisc.edu ADD_FIELD32(extlen,16,1); // external link status enable 3347839Snilay@cs.wisc.edu ADD_FIELD32(rsvd,17,1); // reserved 3357839Snilay@cs.wisc.edu ADD_FIELD32(sdp0d,18,1); // software controlled pin data 3367839Snilay@cs.wisc.edu ADD_FIELD32(sdp1d,19,1); // software controlled pin data 3377839Snilay@cs.wisc.edu ADD_FIELD32(sdp2d,20,1); // software controlled pin data 3387839Snilay@cs.wisc.edu ADD_FIELD32(sdp3d,21,1); // software controlled pin data 3397839Snilay@cs.wisc.edu ADD_FIELD32(sdp0i,22,1); // software controlled pin dir 3407839Snilay@cs.wisc.edu ADD_FIELD32(sdp1i,23,1); // software controlled pin dir 3417839Snilay@cs.wisc.edu ADD_FIELD32(sdp2i,24,1); // software controlled pin dir 3427839Snilay@cs.wisc.edu ADD_FIELD32(sdp3i,25,1); // software controlled pin dir 34311025Snilay@cs.wisc.edu ADD_FIELD32(rst,26,1); // reset 3447007Snate@binkert.org ADD_FIELD32(rfce,27,1); // receive flow control enable 3457007Snate@binkert.org ADD_FIELD32(tfce,28,1); // transmit flow control enable 3467007Snate@binkert.org ADD_FIELD32(rte,29,1); // routing tag enable 3477007Snate@binkert.org ADD_FIELD32(vme,30,1); // vlan enable 3487839Snilay@cs.wisc.edu ADD_FIELD32(phyrst,31,1); // phy reset 3497839Snilay@cs.wisc.edu }; 3507839Snilay@cs.wisc.edu CTRL ctrl; 3517839Snilay@cs.wisc.edu 3527839Snilay@cs.wisc.edu struct STATUS : public Reg<uint32_t> { // 0x0008 STATUS Register 3537839Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 3547839Snilay@cs.wisc.edu ADD_FIELD32(fd,0,1); // full duplex 3557839Snilay@cs.wisc.edu ADD_FIELD32(lu,1,1); // link up 3567839Snilay@cs.wisc.edu ADD_FIELD32(func,2,2); // function id 3577839Snilay@cs.wisc.edu ADD_FIELD32(txoff,4,1); // transmission paused 3587839Snilay@cs.wisc.edu ADD_FIELD32(tbimode,5,1); // tbi mode 3597839Snilay@cs.wisc.edu ADD_FIELD32(speed,6,2); // link speed 36011025Snilay@cs.wisc.edu ADD_FIELD32(asdv,8,2); // auto speed detection value 3617007Snate@binkert.org ADD_FIELD32(mtxckok,10,1); // mtx clock running ok 3629745Snilay@cs.wisc.edu ADD_FIELD32(pci66,11,1); // In 66Mhz pci slot 3639745Snilay@cs.wisc.edu ADD_FIELD32(bus64,12,1); // in 64 bit slot 3649745Snilay@cs.wisc.edu ADD_FIELD32(pcix,13,1); // Pci mode 3659745Snilay@cs.wisc.edu ADD_FIELD32(pcixspd,14,2); // pci x speed 3669745Snilay@cs.wisc.edu }; 3679745Snilay@cs.wisc.edu STATUS sts; 3686657Snate@binkert.org 3697007Snate@binkert.org struct EECD : public Reg<uint32_t> { // 0x0010 EECD Register 3706657Snate@binkert.org using Reg<uint32_t>::operator=; 3716657Snate@binkert.org ADD_FIELD32(sk,0,1); // clack input to the eeprom 3726657Snate@binkert.org ADD_FIELD32(cs,1,1); // chip select to eeprom 3736657Snate@binkert.org ADD_FIELD32(din,2,1); // data input to eeprom 3746657Snate@binkert.org ADD_FIELD32(dout,3,1); // data output bit 3756657Snate@binkert.org ADD_FIELD32(fwe,4,2); // flash write enable 3766657Snate@binkert.org ADD_FIELD32(ee_req,6,1); // request eeprom access 3776657Snate@binkert.org ADD_FIELD32(ee_gnt,7,1); // grant eeprom access 3787839Snilay@cs.wisc.edu ADD_FIELD32(ee_pres,8,1); // eeprom present 3797839Snilay@cs.wisc.edu ADD_FIELD32(ee_size,9,1); // eeprom size 3807839Snilay@cs.wisc.edu ADD_FIELD32(ee_sz1,10,1); // eeprom size 3817839Snilay@cs.wisc.edu ADD_FIELD32(rsvd,11,2); // reserved 3827839Snilay@cs.wisc.edu ADD_FIELD32(ee_type,13,1); // type of eeprom 3837839Snilay@cs.wisc.edu } ; 3847839Snilay@cs.wisc.edu EECD eecd; 3857839Snilay@cs.wisc.edu 3867839Snilay@cs.wisc.edu struct EERD : public Reg<uint32_t> { // 0x0014 EERD Register 3877839Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 3887839Snilay@cs.wisc.edu ADD_FIELD32(start,0,1); // start read 3897839Snilay@cs.wisc.edu ADD_FIELD32(done,1,1); // done read 3907839Snilay@cs.wisc.edu ADD_FIELD32(addr,2,14); // address 3917839Snilay@cs.wisc.edu ADD_FIELD32(data,16,16); // data 3927839Snilay@cs.wisc.edu }; 3937839Snilay@cs.wisc.edu EERD eerd; 39410121Snilay@cs.wisc.edu 3956657Snate@binkert.org struct CTRL_EXT : public Reg<uint32_t> { // 0x0018 CTRL_EXT Register 3966657Snate@binkert.org using Reg<uint32_t>::operator=; 3976657Snate@binkert.org ADD_FIELD32(gpi_en,0,4); // enable interrupts from gpio 3986657Snate@binkert.org ADD_FIELD32(phyint,5,1); // reads the phy internal int status 3997839Snilay@cs.wisc.edu ADD_FIELD32(sdp2_data,6,1); // data from gpio sdp 4007839Snilay@cs.wisc.edu ADD_FIELD32(spd3_data,7,1); // data frmo gpio sdp 4017839Snilay@cs.wisc.edu ADD_FIELD32(spd2_iodir,10,1); // direction of sdp2 40210121Snilay@cs.wisc.edu ADD_FIELD32(spd3_iodir,11,1); // direction of sdp2 40310121Snilay@cs.wisc.edu ADD_FIELD32(asdchk,12,1); // initiate auto-speed-detection 40411025Snilay@cs.wisc.edu ADD_FIELD32(eerst,13,1); // reset the eeprom 4057839Snilay@cs.wisc.edu ADD_FIELD32(spd_byps,15,1); // bypass speed select 4067839Snilay@cs.wisc.edu ADD_FIELD32(ro_dis,17,1); // disable relaxed memory ordering 4077839Snilay@cs.wisc.edu ADD_FIELD32(vreg,21,1); // power down the voltage regulator 40810121Snilay@cs.wisc.edu ADD_FIELD32(link_mode,22,2); // interface to talk to the link 40911025Snilay@cs.wisc.edu ADD_FIELD32(iame, 27,1); // interrupt acknowledge auto-mask ?? 4107839Snilay@cs.wisc.edu ADD_FIELD32(drv_loaded, 28,1);// driver is loaded and incharge of device 4117839Snilay@cs.wisc.edu ADD_FIELD32(timer_clr, 29,1); // clear interrupt timers after IMS clear ?? 4127839Snilay@cs.wisc.edu }; 41310121Snilay@cs.wisc.edu CTRL_EXT ctrl_ext; 41411025Snilay@cs.wisc.edu 4157839Snilay@cs.wisc.edu struct MDIC : public Reg<uint32_t> { // 0x0020 MDIC Register 4167839Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 4177839Snilay@cs.wisc.edu ADD_FIELD32(data,0,16); // data 41811025Snilay@cs.wisc.edu ADD_FIELD32(regadd,16,5); // register address 4196657Snate@binkert.org ADD_FIELD32(phyadd,21,5); // phy addresses 4206657Snate@binkert.org ADD_FIELD32(op,26,2); // opcode 4216657Snate@binkert.org ADD_FIELD32(r,28,1); // ready 4226657Snate@binkert.org ADD_FIELD32(i,29,1); // interrupt 4237007Snate@binkert.org ADD_FIELD32(e,30,1); // error 4246657Snate@binkert.org }; 4256657Snate@binkert.org MDIC mdic; 4269273Snilay@cs.wisc.edu 42710305Snilay@cs.wisc.edu struct ICR : public Reg<uint32_t> { // 0x00C0 ICR Register 4286657Snate@binkert.org using Reg<uint32_t>::operator=; 4296657Snate@binkert.org ADD_FIELD32(txdw,0,1) // tx descr witten back 4306657Snate@binkert.org ADD_FIELD32(txqe,1,1) // tx queue empty 4317007Snate@binkert.org ADD_FIELD32(lsc,2,1) // link status change 4326657Snate@binkert.org ADD_FIELD32(rxseq,3,1) // rcv sequence error 4336657Snate@binkert.org ADD_FIELD32(rxdmt0,4,1) // rcv descriptor min thresh 4349219Spower.jg@gmail.com ADD_FIELD32(rsvd1,5,1) // reserved 4356657Snate@binkert.org ADD_FIELD32(rxo,6,1) // receive overrunn 4366657Snate@binkert.org ADD_FIELD32(rxt0,7,1) // receiver timer interrupt 4376999Snate@binkert.org ADD_FIELD32(mdac,9,1) // mdi/o access complete 4386657Snate@binkert.org ADD_FIELD32(rxcfg,10,1) // recv /c/ ordered sets 4396657Snate@binkert.org ADD_FIELD32(phyint,12,1) // phy interrupt 4406657Snate@binkert.org ADD_FIELD32(gpi1,13,1) // gpi int 1 4416657Snate@binkert.org ADD_FIELD32(gpi2,14,1) // gpi int 2 4427007Snate@binkert.org ADD_FIELD32(txdlow,15,1) // transmit desc low thresh 4436657Snate@binkert.org ADD_FIELD32(srpd,16,1) // small receive packet detected 4446657Snate@binkert.org ADD_FIELD32(ack,17,1); // receive ack frame 4456657Snate@binkert.org ADD_FIELD32(int_assert, 31,1); // interrupt caused a system interrupt 4466657Snate@binkert.org }; 4476657Snate@binkert.org ICR icr; 4488946Sandreas.hansson@arm.com 4498946Sandreas.hansson@arm.com uint32_t imr; // register that contains the current interrupt mask 4508946Sandreas.hansson@arm.com 4517832Snate@binkert.org struct ITR : public Reg<uint32_t> { // 0x00C4 ITR Register 4527002Snate@binkert.org using Reg<uint32_t>::operator=; 4537002Snate@binkert.org ADD_FIELD32(interval, 0,16); // minimum inter-interrutp inteval 45410972Sdavid.hashe@amd.com // specified in 256ns interrupts 4557002Snate@binkert.org }; 4568641Snate@binkert.org ITR itr; 4577056Snate@binkert.org 45810972Sdavid.hashe@amd.com // When CTRL_EXT.IAME and the ICR.INT_ASSERT is 1 an ICR read or write 45910972Sdavid.hashe@amd.com // causes the IAM register contents to be written into the IMC 46010972Sdavid.hashe@amd.com // automatically clearing all interrupts that have a bit in the IAM set 46110972Sdavid.hashe@amd.com uint32_t iam; 46210972Sdavid.hashe@amd.com 4636657Snate@binkert.org struct RCTL : public Reg<uint32_t> { // 0x0100 RCTL Register 4648229Snate@binkert.org using Reg<uint32_t>::operator=; 4656657Snate@binkert.org ADD_FIELD32(rst,0,1); // Reset 4666657Snate@binkert.org ADD_FIELD32(en,1,1); // Enable 46711108Sdavid.hashe@amd.com ADD_FIELD32(sbp,2,1); // Store bad packets 46810972Sdavid.hashe@amd.com ADD_FIELD32(upe,3,1); // Unicast Promiscuous enabled 4699219Spower.jg@gmail.com ADD_FIELD32(mpe,4,1); // Multicast promiscuous enabled 4709219Spower.jg@gmail.com ADD_FIELD32(lpe,5,1); // long packet reception enabled 4719219Spower.jg@gmail.com ADD_FIELD32(lbm,6,2); // 4729219Spower.jg@gmail.com ADD_FIELD32(rdmts,8,2); // 4739219Spower.jg@gmail.com ADD_FIELD32(mo,12,2); // 4747002Snate@binkert.org ADD_FIELD32(mdr,14,1); // 4757002Snate@binkert.org ADD_FIELD32(bam,15,1); // 4766657Snate@binkert.org ADD_FIELD32(bsize,16,2); // 4776657Snate@binkert.org ADD_FIELD32(vfe,18,1); // 4786657Snate@binkert.org ADD_FIELD32(cfien,19,1); // 4796657Snate@binkert.org ADD_FIELD32(cfi,20,1); // 4806657Snate@binkert.org ADD_FIELD32(dpf,22,1); // discard pause frames 4816793SBrad.Beckmann@amd.com ADD_FIELD32(pmcf,23,1); // pass mac control frames 4826657Snate@binkert.org ADD_FIELD32(bsex,25,1); // buffer size extension 4836657Snate@binkert.org ADD_FIELD32(secrc,26,1); // strip ethernet crc from incoming packet 4846657Snate@binkert.org unsigned descSize() 48510121Snilay@cs.wisc.edu { 48610121Snilay@cs.wisc.edu switch(bsize()) { 4876657Snate@binkert.org case 0: return bsex() == 0 ? 2048 : 0; 4886877Ssteve.reinhardt@amd.com case 1: return bsex() == 0 ? 1024 : 16384; 4896877Ssteve.reinhardt@amd.com case 2: return bsex() == 0 ? 512 : 8192; 4906877Ssteve.reinhardt@amd.com case 3: return bsex() == 0 ? 256 : 4096; 4916877Ssteve.reinhardt@amd.com default: 4926877Ssteve.reinhardt@amd.com return 0; 4936877Ssteve.reinhardt@amd.com } 4946657Snate@binkert.org } 4959745Snilay@cs.wisc.edu }; 4969745Snilay@cs.wisc.edu RCTL rctl; 4976657Snate@binkert.org 4987007Snate@binkert.org struct FCTTV : public Reg<uint32_t> { // 0x0170 FCTTV 4996657Snate@binkert.org using Reg<uint32_t>::operator=; 5009801Snilay@cs.wisc.edu ADD_FIELD32(ttv,0,16); // Transmit Timer Value 5019801Snilay@cs.wisc.edu }; 5026657Snate@binkert.org FCTTV fcttv; 5039801Snilay@cs.wisc.edu 5049801Snilay@cs.wisc.edu struct TCTL : public Reg<uint32_t> { // 0x0400 TCTL Register 5059801Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 5067007Snate@binkert.org ADD_FIELD32(rst,0,1); // Reset 5076657Snate@binkert.org ADD_FIELD32(en,1,1); // Enable 5086877Ssteve.reinhardt@amd.com ADD_FIELD32(bce,2,1); // busy check enable 5096877Ssteve.reinhardt@amd.com ADD_FIELD32(psp,3,1); // pad short packets 5106657Snate@binkert.org ADD_FIELD32(ct,4,8); // collision threshold 51110078Snilay@cs.wisc.edu ADD_FIELD32(cold,12,10); // collision distance 51210078Snilay@cs.wisc.edu ADD_FIELD32(swxoff,22,1); // software xoff transmission 51310121Snilay@cs.wisc.edu ADD_FIELD32(pbe,23,1); // packet burst enable 51410121Snilay@cs.wisc.edu ADD_FIELD32(rtlc,24,1); // retransmit late collisions 51510121Snilay@cs.wisc.edu ADD_FIELD32(nrtu,25,1); // on underrun no TX 5166657Snate@binkert.org ADD_FIELD32(mulr,26,1); // multiple request 5176657Snate@binkert.org }; 5186882SBrad.Beckmann@amd.com TCTL tctl; 5196882SBrad.Beckmann@amd.com 5206882SBrad.Beckmann@amd.com struct PBA : public Reg<uint32_t> { // 0x1000 PBA Register 52110121Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 52210121Snilay@cs.wisc.edu ADD_FIELD32(rxa,0,16); 5236882SBrad.Beckmann@amd.com ADD_FIELD32(txa,16,16); 5246877Ssteve.reinhardt@amd.com }; 5256882SBrad.Beckmann@amd.com PBA pba; 52610308Snilay@cs.wisc.edu 5276882SBrad.Beckmann@amd.com struct FCRTL : public Reg<uint32_t> { // 0x2160 FCRTL Register 52810308Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 52910311Snilay@cs.wisc.edu ADD_FIELD32(rtl,3,28); // make this bigger than the spec so we can have 53010308Snilay@cs.wisc.edu // a larger buffer 53110308Snilay@cs.wisc.edu ADD_FIELD32(xone, 31,1); 53210917Sbrandon.potter@amd.com }; 5339595Snilay@cs.wisc.edu FCRTL fcrtl; 5349745Snilay@cs.wisc.edu 5359745Snilay@cs.wisc.edu struct FCRTH : public Reg<uint32_t> { // 0x2168 FCRTL Register 5369745Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 5379745Snilay@cs.wisc.edu ADD_FIELD32(rth,3,13); // make this bigger than the spec so we can have 5389745Snilay@cs.wisc.edu //a larger buffer 5399745Snilay@cs.wisc.edu ADD_FIELD32(xfce, 31,1); 5409745Snilay@cs.wisc.edu }; 5419745Snilay@cs.wisc.edu FCRTH fcrth; 5429745Snilay@cs.wisc.edu 5439745Snilay@cs.wisc.edu struct RDBA : public Reg<uint64_t> { // 0x2800 RDBA Register 5449595Snilay@cs.wisc.edu using Reg<uint64_t>::operator=; 5456657Snate@binkert.org ADD_FIELD64(rdbal,0,32); // base address of rx descriptor ring 5466657Snate@binkert.org ADD_FIELD64(rdbah,32,32); // base address of rx descriptor ring 5476657Snate@binkert.org }; 5486657Snate@binkert.org RDBA rdba; 5497007Snate@binkert.org 55011021Sjthestness@gmail.com struct RDLEN : public Reg<uint32_t> { // 0x2808 RDLEN Register 55110311Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 55210311Snilay@cs.wisc.edu ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer 55310311Snilay@cs.wisc.edu }; 55410311Snilay@cs.wisc.edu RDLEN rdlen; 55510311Snilay@cs.wisc.edu 55610311Snilay@cs.wisc.edu struct SRRCTL : public Reg<uint32_t> { // 0x280C SRRCTL Register 55710311Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 55810311Snilay@cs.wisc.edu ADD_FIELD32(pktlen, 0, 8); 55910311Snilay@cs.wisc.edu ADD_FIELD32(hdrlen, 8, 8); // guess based on header, not documented 56010311Snilay@cs.wisc.edu ADD_FIELD32(desctype, 25,3); // type of descriptor 000 legacy, 001 adv, 56110311Snilay@cs.wisc.edu //101 hdr split 56210311Snilay@cs.wisc.edu unsigned bufLen() { return pktlen() << 10; } 56310311Snilay@cs.wisc.edu unsigned hdrLen() { return hdrlen() << 6; } 56411084Snilay@cs.wisc.edu }; 56510311Snilay@cs.wisc.edu SRRCTL srrctl; 56610311Snilay@cs.wisc.edu 56711021Sjthestness@gmail.com struct RDH : public Reg<uint32_t> { // 0x2810 RDH Register 56811021Sjthestness@gmail.com using Reg<uint32_t>::operator=; 56910311Snilay@cs.wisc.edu ADD_FIELD32(rdh,0,16); // head of the descriptor ring 57010311Snilay@cs.wisc.edu }; 57110311Snilay@cs.wisc.edu RDH rdh; 57210311Snilay@cs.wisc.edu 57310311Snilay@cs.wisc.edu struct RDT : public Reg<uint32_t> { // 0x2818 RDT Register 57410311Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 57510311Snilay@cs.wisc.edu ADD_FIELD32(rdt,0,16); // tail of the descriptor ring 57610311Snilay@cs.wisc.edu }; 57710311Snilay@cs.wisc.edu RDT rdt; 57810311Snilay@cs.wisc.edu 57910311Snilay@cs.wisc.edu struct RDTR : public Reg<uint32_t> { // 0x2820 RDTR Register 58011021Sjthestness@gmail.com using Reg<uint32_t>::operator=; 58111021Sjthestness@gmail.com ADD_FIELD32(delay,0,16); // receive delay timer 58210311Snilay@cs.wisc.edu ADD_FIELD32(fpd, 31,1); // flush partial descriptor block ?? 58310311Snilay@cs.wisc.edu }; 58410311Snilay@cs.wisc.edu RDTR rdtr; 58510311Snilay@cs.wisc.edu 58610311Snilay@cs.wisc.edu struct RXDCTL : public Reg<uint32_t> { // 0x2828 RXDCTL Register 58710311Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 58810311Snilay@cs.wisc.edu ADD_FIELD32(pthresh,0,6); // prefetch threshold, less that this 58910311Snilay@cs.wisc.edu // consider prefetch 59010311Snilay@cs.wisc.edu ADD_FIELD32(hthresh,8,6); // number of descriptors in host mem to 59110311Snilay@cs.wisc.edu // consider prefetch 5927007Snate@binkert.org ADD_FIELD32(wthresh,16,6); // writeback threshold 5936657Snate@binkert.org ADD_FIELD32(gran,24,1); // granularity 0 = desc, 1 = cacheline 5947007Snate@binkert.org }; 59511021Sjthestness@gmail.com RXDCTL rxdctl; 5966657Snate@binkert.org 5976657Snate@binkert.org struct RADV : public Reg<uint32_t> { // 0x282C RADV Register 5986657Snate@binkert.org using Reg<uint32_t>::operator=; 59910311Snilay@cs.wisc.edu ADD_FIELD32(idv,0,16); // absolute interrupt delay 6006657Snate@binkert.org }; 6016657Snate@binkert.org RADV radv; 60210305Snilay@cs.wisc.edu 6036657Snate@binkert.org struct RSRPD : public Reg<uint32_t> { // 0x2C00 RSRPD Register 6046657Snate@binkert.org using Reg<uint32_t>::operator=; 6056657Snate@binkert.org ADD_FIELD32(idv,0,12); // size to interrutp on small packets 6066657Snate@binkert.org }; 6076657Snate@binkert.org RSRPD rsrpd; 6086657Snate@binkert.org 6096657Snate@binkert.org struct TDBA : public Reg<uint64_t> { // 0x3800 TDBAL Register 6106657Snate@binkert.org using Reg<uint64_t>::operator=; 61111084Snilay@cs.wisc.edu ADD_FIELD64(tdbal,0,32); // base address of transmit descriptor ring 61211084Snilay@cs.wisc.edu ADD_FIELD64(tdbah,32,32); // base address of transmit descriptor ring 61311084Snilay@cs.wisc.edu }; 61411084Snilay@cs.wisc.edu TDBA tdba; 61511084Snilay@cs.wisc.edu 6166657Snate@binkert.org struct TDLEN : public Reg<uint32_t> { // 0x3808 TDLEN Register 61711084Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 6186657Snate@binkert.org ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer 6196657Snate@binkert.org }; 6206657Snate@binkert.org TDLEN tdlen; 6217007Snate@binkert.org 6226657Snate@binkert.org struct TDH : public Reg<uint32_t> { // 0x3810 TDH Register 6237007Snate@binkert.org using Reg<uint32_t>::operator=; 6247007Snate@binkert.org ADD_FIELD32(tdh,0,16); // head of the descriptor ring 6256657Snate@binkert.org }; 6269366Snilay@cs.wisc.edu TDH tdh; 6279366Snilay@cs.wisc.edu 6289366Snilay@cs.wisc.edu struct TXDCA_CTL : public Reg<uint32_t> { // 0x3814 TXDCA_CTL Register 6299366Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 6307566SBrad.Beckmann@amd.com ADD_FIELD32(cpu_mask, 0, 5); 6317672Snate@binkert.org ADD_FIELD32(enabled, 5,1); 6326657Snate@binkert.org ADD_FIELD32(relax_ordering, 6, 1); 6339465Snilay@cs.wisc.edu }; 6346657Snate@binkert.org TXDCA_CTL txdca_ctl; 6356657Snate@binkert.org 6366657Snate@binkert.org struct TDT : public Reg<uint32_t> { // 0x3818 TDT Register 6377672Snate@binkert.org using Reg<uint32_t>::operator=; 6386657Snate@binkert.org ADD_FIELD32(tdt,0,16); // tail of the descriptor ring 6396657Snate@binkert.org }; 6406657Snate@binkert.org TDT tdt; 6416657Snate@binkert.org 6426657Snate@binkert.org struct TIDV : public Reg<uint32_t> { // 0x3820 TIDV Register 6436657Snate@binkert.org using Reg<uint32_t>::operator=; 6446657Snate@binkert.org ADD_FIELD32(idv,0,16); // interrupt delay 6456657Snate@binkert.org }; 6466657Snate@binkert.org TIDV tidv; 6476657Snate@binkert.org 6486657Snate@binkert.org struct TXDCTL : public Reg<uint32_t> { // 0x3828 TXDCTL Register 6499745Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 6506657Snate@binkert.org ADD_FIELD32(pthresh, 0,6); // if number of descriptors control has is 6516657Snate@binkert.org // below this number, a prefetch is considered 6529496Snilay@cs.wisc.edu ADD_FIELD32(hthresh,8,8); // number of valid descriptors is host memory 6539496Snilay@cs.wisc.edu // before a prefetch is considered 65410012Snilay@cs.wisc.edu ADD_FIELD32(wthresh,16,6); // number of descriptors to keep until 6559496Snilay@cs.wisc.edu // writeback is considered 6569496Snilay@cs.wisc.edu ADD_FIELD32(gran, 24,1); // granulatiry of above values (0 = cacheline, 6576657Snate@binkert.org // 1 == desscriptor) 65810121Snilay@cs.wisc.edu ADD_FIELD32(lwthresh,25,7); // xmit descriptor low thresh, interrupt 6596657Snate@binkert.org // below this level 6606657Snate@binkert.org }; 66110305Snilay@cs.wisc.edu TXDCTL txdctl; 6626657Snate@binkert.org 66311021Sjthestness@gmail.com struct TADV : public Reg<uint32_t> { // 0x382C TADV Register 66411021Sjthestness@gmail.com using Reg<uint32_t>::operator=; 66511021Sjthestness@gmail.com ADD_FIELD32(idv,0,16); // absolute interrupt delay 66611021Sjthestness@gmail.com }; 66711021Sjthestness@gmail.com TADV tadv; 6688683Snilay@cs.wisc.edu/* 6698683Snilay@cs.wisc.edu struct TDWBA : public Reg<uint64_t> { // 0x3838 TDWBA Register 67010308Snilay@cs.wisc.edu using Reg<uint64_t>::operator=; 6718683Snilay@cs.wisc.edu ADD_FIELD64(en,0,1); // enable transmit description ring address writeback 67210308Snilay@cs.wisc.edu ADD_FIELD64(tdwbal,2,32); // base address of transmit descriptor ring address writeback 6738683Snilay@cs.wisc.edu ADD_FIELD64(tdwbah,32,32); // base address of transmit descriptor ring 6746657Snate@binkert.org }; 6759745Snilay@cs.wisc.edu TDWBA tdwba;*/ 6769745Snilay@cs.wisc.edu uint64_t tdwba; 6779745Snilay@cs.wisc.edu 6789745Snilay@cs.wisc.edu struct RXCSUM : public Reg<uint32_t> { // 0x5000 RXCSUM Register 67910012Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 68010012Snilay@cs.wisc.edu ADD_FIELD32(pcss,0,8); 6819745Snilay@cs.wisc.edu ADD_FIELD32(ipofld,8,1); 6829745Snilay@cs.wisc.edu ADD_FIELD32(tuofld,9,1); 6839745Snilay@cs.wisc.edu ADD_FIELD32(pcsd, 13,1); 6849745Snilay@cs.wisc.edu }; 6859745Snilay@cs.wisc.edu RXCSUM rxcsum; 68610919Sbrandon.potter@amd.com 68710012Snilay@cs.wisc.edu uint32_t rlpml; // 0x5004 RLPML probably maximum accepted packet size 6889745Snilay@cs.wisc.edu 6899745Snilay@cs.wisc.edu struct RFCTL : public Reg<uint32_t> { // 0x5008 RFCTL Register 6909745Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 6919745Snilay@cs.wisc.edu ADD_FIELD32(iscsi_dis,0,1); 6929745Snilay@cs.wisc.edu ADD_FIELD32(iscsi_dwc,1,5); 6939745Snilay@cs.wisc.edu ADD_FIELD32(nfsw_dis,6,1); 6949745Snilay@cs.wisc.edu ADD_FIELD32(nfsr_dis,7,1); 6959745Snilay@cs.wisc.edu ADD_FIELD32(nfs_ver,8,2); 6969745Snilay@cs.wisc.edu ADD_FIELD32(ipv6_dis,10,1); 6979745Snilay@cs.wisc.edu ADD_FIELD32(ipv6xsum_dis,11,1); 6989745Snilay@cs.wisc.edu ADD_FIELD32(ackdis,13,1); 6999745Snilay@cs.wisc.edu ADD_FIELD32(ipfrsp_dis,14,1); 7009745Snilay@cs.wisc.edu ADD_FIELD32(exsten,15,1); 7019745Snilay@cs.wisc.edu }; 7029745Snilay@cs.wisc.edu RFCTL rfctl; 7039745Snilay@cs.wisc.edu 70410919Sbrandon.potter@amd.com struct MANC : public Reg<uint32_t> { // 0x5820 MANC Register 70510012Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 7069745Snilay@cs.wisc.edu ADD_FIELD32(smbus,0,1); // SMBus enabled ##### 7079745Snilay@cs.wisc.edu ADD_FIELD32(asf,1,1); // ASF enabled ##### 7089745Snilay@cs.wisc.edu ADD_FIELD32(ronforce,2,1); // reset of force 7099745Snilay@cs.wisc.edu ADD_FIELD32(rsvd,3,5); // reserved 7109745Snilay@cs.wisc.edu ADD_FIELD32(rmcp1,8,1); // rcmp1 filtering 7119745Snilay@cs.wisc.edu ADD_FIELD32(rmcp2,9,1); // rcmp2 filtering 7129745Snilay@cs.wisc.edu ADD_FIELD32(ipv4,10,1); // enable ipv4 7139745Snilay@cs.wisc.edu ADD_FIELD32(ipv6,11,1); // enable ipv6 7149745Snilay@cs.wisc.edu ADD_FIELD32(snap,12,1); // accept snap 7159745Snilay@cs.wisc.edu ADD_FIELD32(arp,13,1); // filter arp ##### 7169745Snilay@cs.wisc.edu ADD_FIELD32(neighbor,14,1); // neighbor discovery 7179745Snilay@cs.wisc.edu ADD_FIELD32(arp_resp,15,1); // arp response 7189745Snilay@cs.wisc.edu ADD_FIELD32(tcorst,16,1); // tco reset happened 7199745Snilay@cs.wisc.edu ADD_FIELD32(rcvtco,17,1); // receive tco enabled ###### 7209745Snilay@cs.wisc.edu ADD_FIELD32(blkphyrst,18,1);// block phy resets ######## 7219745Snilay@cs.wisc.edu ADD_FIELD32(rcvall,19,1); // receive all 72210920Sbrandon.potter@amd.com ADD_FIELD32(macaddrfltr,20,1); // mac address filtering ###### 7239745Snilay@cs.wisc.edu ADD_FIELD32(mng2host,21,1); // mng2 host packets ####### 72410920Sbrandon.potter@amd.com ADD_FIELD32(ipaddrfltr,22,1); // ip address filtering 72510920Sbrandon.potter@amd.com ADD_FIELD32(xsumfilter,23,1); // checksum filtering 7269745Snilay@cs.wisc.edu ADD_FIELD32(brfilter,24,1); // broadcast filtering 7279745Snilay@cs.wisc.edu ADD_FIELD32(smbreq,25,1); // smb request 7289745Snilay@cs.wisc.edu ADD_FIELD32(smbgnt,26,1); // smb grant 7299745Snilay@cs.wisc.edu ADD_FIELD32(smbclkin,27,1); // smbclkin 7309745Snilay@cs.wisc.edu ADD_FIELD32(smbdatain,28,1); // smbdatain 7319745Snilay@cs.wisc.edu ADD_FIELD32(smbdataout,29,1); // smb data out 7329745Snilay@cs.wisc.edu ADD_FIELD32(smbclkout,30,1); // smb clock out 7339745Snilay@cs.wisc.edu }; 7349745Snilay@cs.wisc.edu MANC manc; 7359745Snilay@cs.wisc.edu 7369745Snilay@cs.wisc.edu struct SWSM : public Reg<uint32_t> { // 0x5B50 SWSM register 7379745Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 73810920Sbrandon.potter@amd.com ADD_FIELD32(smbi,0,1); // Semaphone bit 7399745Snilay@cs.wisc.edu ADD_FIELD32(swesmbi, 1,1); // Software eeporm semaphore 74010920Sbrandon.potter@amd.com ADD_FIELD32(wmng, 2,1); // Wake MNG clock 74110920Sbrandon.potter@amd.com ADD_FIELD32(reserved, 3, 29); 7429745Snilay@cs.wisc.edu }; 7439745Snilay@cs.wisc.edu SWSM swsm; 7449745Snilay@cs.wisc.edu 7459745Snilay@cs.wisc.edu struct FWSM : public Reg<uint32_t> { // 0x5B54 FWSM register 7469745Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 7479745Snilay@cs.wisc.edu ADD_FIELD32(eep_fw_semaphore,0,1); 7489745Snilay@cs.wisc.edu ADD_FIELD32(fw_mode, 1,3); 7499745Snilay@cs.wisc.edu ADD_FIELD32(ide, 4,1); 7509745Snilay@cs.wisc.edu ADD_FIELD32(sol, 5,1); 7519745Snilay@cs.wisc.edu ADD_FIELD32(eep_roload, 6,1); 7529745Snilay@cs.wisc.edu ADD_FIELD32(reserved, 7,8); 7539745Snilay@cs.wisc.edu ADD_FIELD32(fw_val_bit, 15, 1); 7549745Snilay@cs.wisc.edu ADD_FIELD32(reset_cnt, 16, 3); 7559745Snilay@cs.wisc.edu ADD_FIELD32(ext_err_ind, 19, 6); 7569745Snilay@cs.wisc.edu ADD_FIELD32(reserved2, 25, 7); 7579745Snilay@cs.wisc.edu }; 7589745Snilay@cs.wisc.edu FWSM fwsm; 7599745Snilay@cs.wisc.edu 7609745Snilay@cs.wisc.edu uint32_t sw_fw_sync; 7619745Snilay@cs.wisc.edu 7629745Snilay@cs.wisc.edu void serialize(std::ostream &os) 76311061Snilay@cs.wisc.edu { 7649745Snilay@cs.wisc.edu paramOut(os, "ctrl", ctrl._data); 7659745Snilay@cs.wisc.edu paramOut(os, "sts", sts._data); 7669745Snilay@cs.wisc.edu paramOut(os, "eecd", eecd._data); 7679745Snilay@cs.wisc.edu paramOut(os, "eerd", eerd._data); 7689745Snilay@cs.wisc.edu paramOut(os, "ctrl_ext", ctrl_ext._data); 7699745Snilay@cs.wisc.edu paramOut(os, "mdic", mdic._data); 7709745Snilay@cs.wisc.edu paramOut(os, "icr", icr._data); 7719745Snilay@cs.wisc.edu SERIALIZE_SCALAR(imr); 7729745Snilay@cs.wisc.edu paramOut(os, "itr", itr._data); 7739745Snilay@cs.wisc.edu SERIALIZE_SCALAR(iam); 7749745Snilay@cs.wisc.edu paramOut(os, "rctl", rctl._data); 77511061Snilay@cs.wisc.edu paramOut(os, "fcttv", fcttv._data); 7769745Snilay@cs.wisc.edu paramOut(os, "tctl", tctl._data); 7779745Snilay@cs.wisc.edu paramOut(os, "pba", pba._data); 7789745Snilay@cs.wisc.edu paramOut(os, "fcrtl", fcrtl._data); 7799745Snilay@cs.wisc.edu paramOut(os, "fcrth", fcrth._data); 7809745Snilay@cs.wisc.edu paramOut(os, "rdba", rdba._data); 7819745Snilay@cs.wisc.edu paramOut(os, "rdlen", rdlen._data); 7827007Snate@binkert.org paramOut(os, "srrctl", srrctl._data); 7837007Snate@binkert.org paramOut(os, "rdh", rdh._data); 7847007Snate@binkert.org paramOut(os, "rdt", rdt._data); 7856657Snate@binkert.org paramOut(os, "rdtr", rdtr._data); 7866657Snate@binkert.org paramOut(os, "rxdctl", rxdctl._data); 7876657Snate@binkert.org paramOut(os, "radv", radv._data); 7887007Snate@binkert.org paramOut(os, "rsrpd", rsrpd._data); 7897007Snate@binkert.org paramOut(os, "tdba", tdba._data); 7907007Snate@binkert.org paramOut(os, "tdlen", tdlen._data); 7916657Snate@binkert.org paramOut(os, "tdh", tdh._data); 7926657Snate@binkert.org paramOut(os, "txdca_ctl", txdca_ctl._data); 7936657Snate@binkert.org paramOut(os, "tdt", tdt._data); 79411021Sjthestness@gmail.com paramOut(os, "tidv", tidv._data); 79511021Sjthestness@gmail.com paramOut(os, "txdctl", txdctl._data); 79611021Sjthestness@gmail.com paramOut(os, "tadv", tadv._data); 79711021Sjthestness@gmail.com //paramOut(os, "tdwba", tdwba._data); 79811021Sjthestness@gmail.com SERIALIZE_SCALAR(tdwba); 79911021Sjthestness@gmail.com paramOut(os, "rxcsum", rxcsum._data); 8008683Snilay@cs.wisc.edu SERIALIZE_SCALAR(rlpml); 8018683Snilay@cs.wisc.edu paramOut(os, "rfctl", rfctl._data); 8028683Snilay@cs.wisc.edu paramOut(os, "manc", manc._data); 8038683Snilay@cs.wisc.edu paramOut(os, "swsm", swsm._data); 8048683Snilay@cs.wisc.edu paramOut(os, "fwsm", fwsm._data); 8058683Snilay@cs.wisc.edu SERIALIZE_SCALAR(sw_fw_sync); 8067007Snate@binkert.org } 8077007Snate@binkert.org 8087007Snate@binkert.org void unserialize(Checkpoint *cp, const std::string §ion) 8097007Snate@binkert.org { 8107007Snate@binkert.org paramIn(cp, section, "ctrl", ctrl._data); 8116657Snate@binkert.org paramIn(cp, section, "sts", sts._data); 81210012Snilay@cs.wisc.edu paramIn(cp, section, "eecd", eecd._data); 8139745Snilay@cs.wisc.edu paramIn(cp, section, "eerd", eerd._data); 8149745Snilay@cs.wisc.edu paramIn(cp, section, "ctrl_ext", ctrl_ext._data); 8159745Snilay@cs.wisc.edu paramIn(cp, section, "mdic", mdic._data); 8169745Snilay@cs.wisc.edu paramIn(cp, section, "icr", icr._data); 8179745Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(imr); 8189745Snilay@cs.wisc.edu paramIn(cp, section, "itr", itr._data); 8196902SBrad.Beckmann@amd.com UNSERIALIZE_SCALAR(iam); 8209745Snilay@cs.wisc.edu paramIn(cp, section, "rctl", rctl._data); 8219745Snilay@cs.wisc.edu paramIn(cp, section, "fcttv", fcttv._data); 8229745Snilay@cs.wisc.edu paramIn(cp, section, "tctl", tctl._data); 8239745Snilay@cs.wisc.edu paramIn(cp, section, "pba", pba._data); 82410012Snilay@cs.wisc.edu paramIn(cp, section, "fcrtl", fcrtl._data); 8256902SBrad.Beckmann@amd.com paramIn(cp, section, "fcrth", fcrth._data); 8267839Snilay@cs.wisc.edu paramIn(cp, section, "rdba", rdba._data); 8277839Snilay@cs.wisc.edu paramIn(cp, section, "rdlen", rdlen._data); 8287839Snilay@cs.wisc.edu paramIn(cp, section, "srrctl", srrctl._data); 8297839Snilay@cs.wisc.edu paramIn(cp, section, "rdh", rdh._data); 8307839Snilay@cs.wisc.edu paramIn(cp, section, "rdt", rdt._data); 8317839Snilay@cs.wisc.edu paramIn(cp, section, "rdtr", rdtr._data); 8327839Snilay@cs.wisc.edu paramIn(cp, section, "rxdctl", rxdctl._data); 8337839Snilay@cs.wisc.edu paramIn(cp, section, "radv", radv._data); 8347839Snilay@cs.wisc.edu paramIn(cp, section, "rsrpd", rsrpd._data); 8357839Snilay@cs.wisc.edu paramIn(cp, section, "tdba", tdba._data); 8367839Snilay@cs.wisc.edu paramIn(cp, section, "tdlen", tdlen._data); 8377839Snilay@cs.wisc.edu paramIn(cp, section, "tdh", tdh._data); 8387839Snilay@cs.wisc.edu paramIn(cp, section, "txdca_ctl", txdca_ctl._data); 8397839Snilay@cs.wisc.edu paramIn(cp, section, "tdt", tdt._data); 8407839Snilay@cs.wisc.edu paramIn(cp, section, "tidv", tidv._data); 8417839Snilay@cs.wisc.edu paramIn(cp, section, "txdctl", txdctl._data); 8427839Snilay@cs.wisc.edu paramIn(cp, section, "tadv", tadv._data); 8437839Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(tdwba); 8447839Snilay@cs.wisc.edu //paramIn(cp, section, "tdwba", tdwba._data); 8457839Snilay@cs.wisc.edu paramIn(cp, section, "rxcsum", rxcsum._data); 8467839Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(rlpml); 8477839Snilay@cs.wisc.edu paramIn(cp, section, "rfctl", rfctl._data); 8487839Snilay@cs.wisc.edu paramIn(cp, section, "manc", manc._data); 8497839Snilay@cs.wisc.edu paramIn(cp, section, "swsm", swsm._data); 8507839Snilay@cs.wisc.edu paramIn(cp, section, "fwsm", fwsm._data); 8517839Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(sw_fw_sync); 8527839Snilay@cs.wisc.edu } 8537839Snilay@cs.wisc.edu}; 8547839Snilay@cs.wisc.edu} // namespace iGbReg 8557839Snilay@cs.wisc.edu