i8254xGBe_defs.hh revision 4294
16019Shines@cs.fsu.edu/* 26019Shines@cs.fsu.edu * Copyright (c) 2006 The Regents of The University of Michigan 37178Sgblack@eecs.umich.edu * All rights reserved. 47178Sgblack@eecs.umich.edu * 57178Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 67178Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 77178Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 87178Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 97178Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 107178Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 117178Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 127178Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 137178Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 147178Sgblack@eecs.umich.edu * this software without specific prior written permission. 156019Shines@cs.fsu.edu * 166019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * Authors: Ali Saidi 296019Shines@cs.fsu.edu */ 306019Shines@cs.fsu.edu 316019Shines@cs.fsu.edu/* @file 326019Shines@cs.fsu.edu * Register and structure descriptions for Intel's 8254x line of gigabit ethernet controllers. 336019Shines@cs.fsu.edu */ 346019Shines@cs.fsu.edu#include "base/bitfield.hh" 356019Shines@cs.fsu.edu 366019Shines@cs.fsu.edunamespace iGbReg { 376019Shines@cs.fsu.edu 386019Shines@cs.fsu.edu 396019Shines@cs.fsu.edu// Registers used by the Intel GbE NIC 406019Shines@cs.fsu.educonst uint32_t REG_CTRL = 0x00000; 416019Shines@cs.fsu.educonst uint32_t REG_STATUS = 0x00008; 426019Shines@cs.fsu.educonst uint32_t REG_EECD = 0x00010; 436019Shines@cs.fsu.educonst uint32_t REG_EERD = 0x00014; 446019Shines@cs.fsu.educonst uint32_t REG_CTRL_EXT = 0x00018; 456019Shines@cs.fsu.educonst uint32_t REG_MDIC = 0x00020; 466019Shines@cs.fsu.educonst uint32_t REG_FCAL = 0x00028; 476019Shines@cs.fsu.educonst uint32_t REG_FCAH = 0x0002C; 487639Sgblack@eecs.umich.educonst uint32_t REG_FCT = 0x00030; 497639Sgblack@eecs.umich.educonst uint32_t REG_VET = 0x00038; 507639Sgblack@eecs.umich.educonst uint32_t REG_PBA = 0x01000; 517639Sgblack@eecs.umich.educonst uint32_t REG_ICR = 0x000C0; 527639Sgblack@eecs.umich.educonst uint32_t REG_ITR = 0x000C4; 537639Sgblack@eecs.umich.educonst uint32_t REG_ICS = 0x000C8; 547639Sgblack@eecs.umich.educonst uint32_t REG_IMS = 0x000D0; 557639Sgblack@eecs.umich.educonst uint32_t REG_IMC = 0x000D8; 567639Sgblack@eecs.umich.educonst uint32_t REG_IAM = 0x000E0; 577639Sgblack@eecs.umich.educonst uint32_t REG_RCTL = 0x00100; 587639Sgblack@eecs.umich.educonst uint32_t REG_FCTTV = 0x00170; 597639Sgblack@eecs.umich.educonst uint32_t REG_TIPG = 0x00410; 607639Sgblack@eecs.umich.educonst uint32_t REG_AIFS = 0x00458; 617639Sgblack@eecs.umich.educonst uint32_t REG_LEDCTL = 0x00e00; 627639Sgblack@eecs.umich.educonst uint32_t REG_FCRTL = 0x02160; 637639Sgblack@eecs.umich.educonst uint32_t REG_FCRTH = 0x02168; 647639Sgblack@eecs.umich.educonst uint32_t REG_RDBAL = 0x02800; 657639Sgblack@eecs.umich.educonst uint32_t REG_RDBAH = 0x02804; 667639Sgblack@eecs.umich.educonst uint32_t REG_RDLEN = 0x02808; 677639Sgblack@eecs.umich.educonst uint32_t REG_RDH = 0x02810; 687639Sgblack@eecs.umich.educonst uint32_t REG_RDT = 0x02818; 697639Sgblack@eecs.umich.educonst uint32_t REG_RDTR = 0x02820; 707639Sgblack@eecs.umich.educonst uint32_t REG_RXDCTL = 0x02828; 717639Sgblack@eecs.umich.educonst uint32_t REG_RADV = 0x0282C; 727639Sgblack@eecs.umich.educonst uint32_t REG_TCTL = 0x00400; 737639Sgblack@eecs.umich.educonst uint32_t REG_TDBAL = 0x03800; 747639Sgblack@eecs.umich.educonst uint32_t REG_TDBAH = 0x03804; 757639Sgblack@eecs.umich.educonst uint32_t REG_TDLEN = 0x03808; 767639Sgblack@eecs.umich.educonst uint32_t REG_TDH = 0x03810; 777639Sgblack@eecs.umich.educonst uint32_t REG_TDT = 0x03818; 787639Sgblack@eecs.umich.educonst uint32_t REG_TIDV = 0x03820; 797639Sgblack@eecs.umich.educonst uint32_t REG_TXDCTL = 0x03828; 807639Sgblack@eecs.umich.educonst uint32_t REG_TADV = 0x0382C; 817639Sgblack@eecs.umich.educonst uint32_t REG_CRCERRS = 0x04000; 827639Sgblack@eecs.umich.educonst uint32_t REG_RXCSUM = 0x05000; 837639Sgblack@eecs.umich.educonst uint32_t REG_MTA = 0x05200; 847639Sgblack@eecs.umich.educonst uint32_t REG_RAL = 0x05400; 857639Sgblack@eecs.umich.educonst uint32_t REG_RAH = 0x05404; 867639Sgblack@eecs.umich.educonst uint32_t REG_VFTA = 0x05600; 877639Sgblack@eecs.umich.edu 887639Sgblack@eecs.umich.educonst uint32_t REG_WUC = 0x05800; 897639Sgblack@eecs.umich.educonst uint32_t REG_MANC = 0x05820; 907639Sgblack@eecs.umich.edu 917639Sgblack@eecs.umich.educonst uint8_t EEPROM_READ_OPCODE_SPI = 0x03; 927639Sgblack@eecs.umich.educonst uint8_t EEPROM_RDSR_OPCODE_SPI = 0x05; 937639Sgblack@eecs.umich.educonst uint8_t EEPROM_SIZE = 64; 947356Sgblack@eecs.umich.educonst uint16_t EEPROM_CSUM = 0xBABA; 957356Sgblack@eecs.umich.edu 967356Sgblack@eecs.umich.educonst uint8_t VLAN_FILTER_TABLE_SIZE = 128; 977435Sgblack@eecs.umich.educonst uint8_t RCV_ADDRESS_TABLE_SIZE = 16; 987435Sgblack@eecs.umich.educonst uint8_t MULTICAST_TABLE_SIZE = 128; 997435Sgblack@eecs.umich.educonst uint32_t STATS_REGS_SIZE = 0x124; 1007435Sgblack@eecs.umich.edu 1017435Sgblack@eecs.umich.edu 1027435Sgblack@eecs.umich.edu// Registers in that are accessed in the PHY 1037435Sgblack@eecs.umich.educonst uint8_t PHY_PSTATUS = 0x1; 1047435Sgblack@eecs.umich.educonst uint8_t PHY_PID = 0x2; 1057435Sgblack@eecs.umich.educonst uint8_t PHY_EPID = 0x3; 1067435Sgblack@eecs.umich.educonst uint8_t PHY_GSTATUS = 10; 1077435Sgblack@eecs.umich.educonst uint8_t PHY_EPSTATUS = 15; 1087639Sgblack@eecs.umich.educonst uint8_t PHY_AGC = 18; 1097639Sgblack@eecs.umich.edu 1107639Sgblack@eecs.umich.edu// Receive Descriptor Status Flags 1117435Sgblack@eecs.umich.educonst uint8_t RXDS_PIF = 0x80; 1127639Sgblack@eecs.umich.educonst uint8_t RXDS_IPCS = 0x40; 1137639Sgblack@eecs.umich.educonst uint8_t RXDS_TCPCS = 0x20; 1147639Sgblack@eecs.umich.educonst uint8_t RXDS_UDPCS = 0x10; 1157639Sgblack@eecs.umich.educonst uint8_t RXDS_VP = 0x08; 1167639Sgblack@eecs.umich.educonst uint8_t RXDS_IXSM = 0x04; 1177639Sgblack@eecs.umich.educonst uint8_t RXDS_EOP = 0x02; 1187639Sgblack@eecs.umich.educonst uint8_t RXDS_DD = 0x01; 1197639Sgblack@eecs.umich.edu 1207639Sgblack@eecs.umich.edu// Receive Descriptor Error Flags 1217639Sgblack@eecs.umich.educonst uint8_t RXDE_RXE = 0x80; 1227639Sgblack@eecs.umich.educonst uint8_t RXDE_IPE = 0x40; 1237639Sgblack@eecs.umich.educonst uint8_t RXDE_TCPE = 0x20; 1247639Sgblack@eecs.umich.educonst uint8_t RXDE_SEQ = 0x04; 1257639Sgblack@eecs.umich.educonst uint8_t RXDE_SE = 0x02; 1267639Sgblack@eecs.umich.educonst uint8_t RXDE_CE = 0x01; 1277639Sgblack@eecs.umich.edu 1287639Sgblack@eecs.umich.edu// Interrupt types 1297639Sgblack@eecs.umich.eduenum IntTypes 1307639Sgblack@eecs.umich.edu{ 1317639Sgblack@eecs.umich.edu IT_NONE = 0x00000, //dummy value 1327639Sgblack@eecs.umich.edu IT_TXDW = 0x00001, 1337639Sgblack@eecs.umich.edu IT_TXQE = 0x00002, 1347639Sgblack@eecs.umich.edu IT_LSC = 0x00004, 1357639Sgblack@eecs.umich.edu IT_RXSEQ = 0x00008, 1367639Sgblack@eecs.umich.edu IT_RXDMT = 0x00010, 1377639Sgblack@eecs.umich.edu IT_RXO = 0x00040, 1387639Sgblack@eecs.umich.edu IT_RXT = 0x00080, 1397639Sgblack@eecs.umich.edu IT_MADC = 0x00200, 1407639Sgblack@eecs.umich.edu IT_RXCFG = 0x00400, 1417639Sgblack@eecs.umich.edu IT_GPI0 = 0x02000, 1427639Sgblack@eecs.umich.edu IT_GPI1 = 0x04000, 1437639Sgblack@eecs.umich.edu IT_TXDLOW = 0x08000, 1447639Sgblack@eecs.umich.edu IT_SRPD = 0x10000, 1457639Sgblack@eecs.umich.edu IT_ACK = 0x20000 1468144SAli.Saidi@ARM.com}; 1477639Sgblack@eecs.umich.edu 1487639Sgblack@eecs.umich.edu// Receive Descriptor struct 1497639Sgblack@eecs.umich.edustruct RxDesc { 1507639Sgblack@eecs.umich.edu Addr buf; 1517639Sgblack@eecs.umich.edu uint16_t len; 1527639Sgblack@eecs.umich.edu uint16_t csum; 1537639Sgblack@eecs.umich.edu uint8_t status; 1547639Sgblack@eecs.umich.edu uint8_t errors; 1557639Sgblack@eecs.umich.edu uint16_t vlan; 1567639Sgblack@eecs.umich.edu}; 1577639Sgblack@eecs.umich.edu 1587639Sgblack@eecs.umich.edustruct TxDesc { 1597639Sgblack@eecs.umich.edu uint64_t d1; 1607639Sgblack@eecs.umich.edu uint64_t d2; 1617639Sgblack@eecs.umich.edu}; 1627639Sgblack@eecs.umich.edu 1637639Sgblack@eecs.umich.edunamespace TxdOp { 1647639Sgblack@eecs.umich.educonst uint8_t TXD_CNXT = 0x0; 1657639Sgblack@eecs.umich.educonst uint8_t TXD_DATA = 0x1; 1667639Sgblack@eecs.umich.edu 1677639Sgblack@eecs.umich.edubool isLegacy(TxDesc *d) { return !bits(d->d2,29,29); } 1687639Sgblack@eecs.umich.eduuint8_t getType(TxDesc *d) { return bits(d->d2, 23,20); } 1697639Sgblack@eecs.umich.edubool isContext(TxDesc *d) { return !isLegacy(d) && getType(d) == TXD_CNXT; } 1707639Sgblack@eecs.umich.edubool isData(TxDesc *d) { return !isLegacy(d) && getType(d) == TXD_DATA; } 1717639Sgblack@eecs.umich.edu 1727639Sgblack@eecs.umich.eduAddr getBuf(TxDesc *d) { assert(isLegacy(d) || isData(d)); return d->d1; } 1737639Sgblack@eecs.umich.eduAddr getLen(TxDesc *d) { if (isLegacy(d)) return bits(d->d2,15,0); else return bits(d->d2, 19,0); } 1747639Sgblack@eecs.umich.eduvoid setDd(TxDesc *d) 1757639Sgblack@eecs.umich.edu{ 1767639Sgblack@eecs.umich.edu replaceBits(d->d2, 35, 32, ULL(1)); 1777639Sgblack@eecs.umich.edu} 1787639Sgblack@eecs.umich.edu 1797639Sgblack@eecs.umich.edubool ide(TxDesc *d) { return bits(d->d2, 31,31); } 1807639Sgblack@eecs.umich.edubool vle(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 30,30); } 1817639Sgblack@eecs.umich.edubool rs(TxDesc *d) { return bits(d->d2, 27,27); } 1827639Sgblack@eecs.umich.edubool ic(TxDesc *d) { assert(isLegacy(d) || isData(d)); return isLegacy(d) && bits(d->d2, 26,26); } 1837591SAli.Saidi@ARM.combool tse(TxDesc *d) { return (isData(d) || isContext(d)) && bits(d->d2, 26,26); } 1847639Sgblack@eecs.umich.edubool ifcs(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 25,25); } 1857435Sgblack@eecs.umich.edubool eop(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 24,24); } 1867435Sgblack@eecs.umich.edubool ip(TxDesc *d) { assert(isContext(d)); return bits(d->d2, 25,25); } 1877639Sgblack@eecs.umich.edubool tcp(TxDesc *d) { assert(isContext(d)); return bits(d->d2, 24,24); } 1887639Sgblack@eecs.umich.edu 1897639Sgblack@eecs.umich.eduuint8_t getCso(TxDesc *d) { assert(isLegacy(d)); return bits(d->d2, 23,16); } 1907639Sgblack@eecs.umich.eduuint8_t getCss(TxDesc *d) { assert(isLegacy(d)); return bits(d->d2, 47,40); } 1917639Sgblack@eecs.umich.edu 1927639Sgblack@eecs.umich.edubool ixsm(TxDesc *d) { return isData(d) && bits(d->d2, 40,40); } 1937639Sgblack@eecs.umich.edubool txsm(TxDesc *d) { return isData(d) && bits(d->d2, 41,41); } 1947639Sgblack@eecs.umich.edu 1957639Sgblack@eecs.umich.eduint tucse(TxDesc *d) { assert(isContext(d)); return bits(d->d1,63,48); } 1967639Sgblack@eecs.umich.eduint tucso(TxDesc *d) { assert(isContext(d)); return bits(d->d1,47,40); } 1977639Sgblack@eecs.umich.eduint tucss(TxDesc *d) { assert(isContext(d)); return bits(d->d1,39,32); } 1987639Sgblack@eecs.umich.eduint ipcse(TxDesc *d) { assert(isContext(d)); return bits(d->d1,31,16); } 1997639Sgblack@eecs.umich.eduint ipcso(TxDesc *d) { assert(isContext(d)); return bits(d->d1,15,8); } 2007639Sgblack@eecs.umich.eduint ipcss(TxDesc *d) { assert(isContext(d)); return bits(d->d1,7,0); } 2017639Sgblack@eecs.umich.eduint mss(TxDesc *d) { assert(isContext(d)); return bits(d->d2,63,48); } 2027639Sgblack@eecs.umich.eduint hdrlen(TxDesc *d) { assert(isContext(d)); return bits(d->d2,47,40); } 2037639Sgblack@eecs.umich.edu} // namespace TxdOp 2047639Sgblack@eecs.umich.edu 2057639Sgblack@eecs.umich.edu 2067639Sgblack@eecs.umich.edu#define ADD_FIELD32(NAME, OFFSET, BITS) \ 2077639Sgblack@eecs.umich.edu inline uint32_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \ 2087639Sgblack@eecs.umich.edu inline void NAME(uint32_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); } 2097639Sgblack@eecs.umich.edu 2107639Sgblack@eecs.umich.edu#define ADD_FIELD64(NAME, OFFSET, BITS) \ 2117639Sgblack@eecs.umich.edu inline uint64_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \ 2127639Sgblack@eecs.umich.edu inline void NAME(uint64_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); } 2137639Sgblack@eecs.umich.edu 2147639Sgblack@eecs.umich.edustruct Regs { 2157639Sgblack@eecs.umich.edu template<class T> 2167639Sgblack@eecs.umich.edu struct Reg { 2177639Sgblack@eecs.umich.edu T _data; 2187639Sgblack@eecs.umich.edu T operator()() { return _data; } 2197639Sgblack@eecs.umich.edu const Reg<T> &operator=(T d) { _data = d; return *this;} 2207639Sgblack@eecs.umich.edu bool operator==(T d) { return d == _data; } 2217639Sgblack@eecs.umich.edu void operator()(T d) { _data = d; } 2227639Sgblack@eecs.umich.edu Reg() { _data = 0; } 2237591SAli.Saidi@ARM.com void serialize(std::ostream &os) 2247591SAli.Saidi@ARM.com { 2257639Sgblack@eecs.umich.edu SERIALIZE_SCALAR(_data); 2267639Sgblack@eecs.umich.edu } 2277639Sgblack@eecs.umich.edu void unserialize(Checkpoint *cp, const std::string §ion) 2287639Sgblack@eecs.umich.edu { 2297639Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(_data); 2307639Sgblack@eecs.umich.edu } 2317639Sgblack@eecs.umich.edu }; 2327639Sgblack@eecs.umich.edu 2337639Sgblack@eecs.umich.edu struct CTRL : public Reg<uint32_t> { // 0x0000 CTRL Register 2347639Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 2357639Sgblack@eecs.umich.edu ADD_FIELD32(fd,0,1); // full duplex 2367639Sgblack@eecs.umich.edu ADD_FIELD32(bem,1,1); // big endian mode 2377639Sgblack@eecs.umich.edu ADD_FIELD32(pcipr,2,1); // PCI priority 2387639Sgblack@eecs.umich.edu ADD_FIELD32(lrst,3,1); // link reset 2397639Sgblack@eecs.umich.edu ADD_FIELD32(tme,4,1); // test mode enable 2407639Sgblack@eecs.umich.edu ADD_FIELD32(asde,5,1); // Auto-speed detection 2417639Sgblack@eecs.umich.edu ADD_FIELD32(slu,6,1); // Set link up 2427639Sgblack@eecs.umich.edu ADD_FIELD32(ilos,7,1); // invert los-of-signal 2437639Sgblack@eecs.umich.edu ADD_FIELD32(speed,8,2); // speed selection bits 2447639Sgblack@eecs.umich.edu ADD_FIELD32(be32,10,1); // big endian mode 32 2457435Sgblack@eecs.umich.edu ADD_FIELD32(frcspd,11,1); // force speed 2467435Sgblack@eecs.umich.edu ADD_FIELD32(frcdpx,12,1); // force duplex 2477639Sgblack@eecs.umich.edu ADD_FIELD32(duden,13,1); // dock/undock enable 2487639Sgblack@eecs.umich.edu ADD_FIELD32(dudpol,14,1); // dock/undock polarity 2497639Sgblack@eecs.umich.edu ADD_FIELD32(fphyrst,15,1); // force phy reset 2507639Sgblack@eecs.umich.edu ADD_FIELD32(extlen,16,1); // external link status enable 2517639Sgblack@eecs.umich.edu ADD_FIELD32(rsvd,17,1); // reserved 2527639Sgblack@eecs.umich.edu ADD_FIELD32(sdp0d,18,1); // software controlled pin data 2537639Sgblack@eecs.umich.edu ADD_FIELD32(sdp1d,19,1); // software controlled pin data 2547639Sgblack@eecs.umich.edu ADD_FIELD32(sdp2d,20,1); // software controlled pin data 2557639Sgblack@eecs.umich.edu ADD_FIELD32(sdp3d,21,1); // software controlled pin data 2567639Sgblack@eecs.umich.edu ADD_FIELD32(sdp0i,22,1); // software controlled pin dir 2577639Sgblack@eecs.umich.edu ADD_FIELD32(sdp1i,23,1); // software controlled pin dir 2587639Sgblack@eecs.umich.edu ADD_FIELD32(sdp2i,24,1); // software controlled pin dir 2597639Sgblack@eecs.umich.edu ADD_FIELD32(sdp3i,25,1); // software controlled pin dir 2607639Sgblack@eecs.umich.edu ADD_FIELD32(rst,26,1); // reset 2617639Sgblack@eecs.umich.edu ADD_FIELD32(rfce,27,1); // receive flow control enable 2627639Sgblack@eecs.umich.edu ADD_FIELD32(tfce,28,1); // transmit flow control enable 2637639Sgblack@eecs.umich.edu ADD_FIELD32(rte,29,1); // routing tag enable 2647639Sgblack@eecs.umich.edu ADD_FIELD32(vme,30,1); // vlan enable 2657639Sgblack@eecs.umich.edu ADD_FIELD32(phyrst,31,1); // phy reset 2667639Sgblack@eecs.umich.edu }; 2677639Sgblack@eecs.umich.edu CTRL ctrl; 2687639Sgblack@eecs.umich.edu 2697639Sgblack@eecs.umich.edu struct STATUS : public Reg<uint32_t> { // 0x0008 STATUS Register 2707639Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 2717639Sgblack@eecs.umich.edu ADD_FIELD32(fd,0,1); // full duplex 2727639Sgblack@eecs.umich.edu ADD_FIELD32(lu,1,1); // link up 2737639Sgblack@eecs.umich.edu ADD_FIELD32(func,2,2); // function id 2747639Sgblack@eecs.umich.edu ADD_FIELD32(txoff,4,1); // transmission paused 2757639Sgblack@eecs.umich.edu ADD_FIELD32(tbimode,5,1); // tbi mode 2767639Sgblack@eecs.umich.edu ADD_FIELD32(speed,6,2); // link speed 2777639Sgblack@eecs.umich.edu ADD_FIELD32(asdv,8,2); // auto speed detection value 2787639Sgblack@eecs.umich.edu ADD_FIELD32(mtxckok,10,1); // mtx clock running ok 2797639Sgblack@eecs.umich.edu ADD_FIELD32(pci66,11,1); // In 66Mhz pci slot 2807639Sgblack@eecs.umich.edu ADD_FIELD32(bus64,12,1); // in 64 bit slot 2817639Sgblack@eecs.umich.edu ADD_FIELD32(pcix,13,1); // Pci mode 2827639Sgblack@eecs.umich.edu ADD_FIELD32(pcixspd,14,2); // pci x speed 2837639Sgblack@eecs.umich.edu }; 2847639Sgblack@eecs.umich.edu STATUS sts; 2857639Sgblack@eecs.umich.edu 2867639Sgblack@eecs.umich.edu struct EECD : public Reg<uint32_t> { // 0x0010 EECD Register 2877639Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 2887639Sgblack@eecs.umich.edu ADD_FIELD32(sk,0,1); // clack input to the eeprom 2897639Sgblack@eecs.umich.edu ADD_FIELD32(cs,1,1); // chip select to eeprom 2907639Sgblack@eecs.umich.edu ADD_FIELD32(din,2,1); // data input to eeprom 2917639Sgblack@eecs.umich.edu ADD_FIELD32(dout,3,1); // data output bit 2927639Sgblack@eecs.umich.edu ADD_FIELD32(fwe,4,2); // flash write enable 2937639Sgblack@eecs.umich.edu ADD_FIELD32(ee_req,6,1); // request eeprom access 2947639Sgblack@eecs.umich.edu ADD_FIELD32(ee_gnt,7,1); // grant eeprom access 2957639Sgblack@eecs.umich.edu ADD_FIELD32(ee_pres,8,1); // eeprom present 2967639Sgblack@eecs.umich.edu ADD_FIELD32(ee_size,9,1); // eeprom size 2977639Sgblack@eecs.umich.edu ADD_FIELD32(ee_sz1,10,1); // eeprom size 2987639Sgblack@eecs.umich.edu ADD_FIELD32(rsvd,11,2); // reserved 2997639Sgblack@eecs.umich.edu ADD_FIELD32(ee_type,13,1); // type of eeprom 3007639Sgblack@eecs.umich.edu } ; 3017639Sgblack@eecs.umich.edu EECD eecd; 3027639Sgblack@eecs.umich.edu 3037639Sgblack@eecs.umich.edu struct EERD : public Reg<uint32_t> { // 0x0014 EERD Register 3047639Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 3057639Sgblack@eecs.umich.edu ADD_FIELD32(start,0,1); // start read 3067639Sgblack@eecs.umich.edu ADD_FIELD32(done,4,1); // done read 3077639Sgblack@eecs.umich.edu ADD_FIELD32(addr,8,8); // address 3087639Sgblack@eecs.umich.edu ADD_FIELD32(data,16,16); // data 3097639Sgblack@eecs.umich.edu }; 3107639Sgblack@eecs.umich.edu EERD eerd; 3117639Sgblack@eecs.umich.edu 3127639Sgblack@eecs.umich.edu struct CTRL_EXT : public Reg<uint32_t> { // 0x0018 CTRL_EXT Register 3137639Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 3147639Sgblack@eecs.umich.edu ADD_FIELD32(gpi_en,0,4); // enable interrupts from gpio 3157639Sgblack@eecs.umich.edu ADD_FIELD32(phyint,5,1); // reads the phy internal int status 3167639Sgblack@eecs.umich.edu ADD_FIELD32(sdp2_data,6,1); // data from gpio sdp 3177639Sgblack@eecs.umich.edu ADD_FIELD32(spd3_data,7,1); // data frmo gpio sdp 3187639Sgblack@eecs.umich.edu ADD_FIELD32(spd2_iodir,10,1); // direction of sdp2 3197639Sgblack@eecs.umich.edu ADD_FIELD32(spd3_iodir,11,1); // direction of sdp2 3207639Sgblack@eecs.umich.edu ADD_FIELD32(asdchk,12,1); // initiate auto-speed-detection 3217639Sgblack@eecs.umich.edu ADD_FIELD32(eerst,13,1); // reset the eeprom 3227639Sgblack@eecs.umich.edu ADD_FIELD32(spd_byps,15,1); // bypass speed select 3237435Sgblack@eecs.umich.edu ADD_FIELD32(ro_dis,17,1); // disable relaxed memory ordering 3247435Sgblack@eecs.umich.edu ADD_FIELD32(vreg,21,1); // power down the voltage regulator 3257639Sgblack@eecs.umich.edu ADD_FIELD32(link_mode,22,2); // interface to talk to the link 3267639Sgblack@eecs.umich.edu ADD_FIELD32(iame, 27,1); // interrupt acknowledge auto-mask ?? 3277639Sgblack@eecs.umich.edu ADD_FIELD32(drv_loaded, 28,1);// driver is loaded and incharge of device 3287591SAli.Saidi@ARM.com ADD_FIELD32(timer_clr, 29,1); // clear interrupt timers after IMS clear ?? 3297639Sgblack@eecs.umich.edu }; 3307639Sgblack@eecs.umich.edu CTRL_EXT ctrl_ext; 3317435Sgblack@eecs.umich.edu 3327435Sgblack@eecs.umich.edu struct MDIC : public Reg<uint32_t> { // 0x0020 MDIC Register 3337639Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 3347639Sgblack@eecs.umich.edu ADD_FIELD32(data,0,16); // data 3357435Sgblack@eecs.umich.edu ADD_FIELD32(regadd,16,5); // register address 3367435Sgblack@eecs.umich.edu ADD_FIELD32(phyadd,21,5); // phy addresses 3377591SAli.Saidi@ARM.com ADD_FIELD32(op,26,2); // opcode 3387435Sgblack@eecs.umich.edu ADD_FIELD32(r,28,1); // ready 3397435Sgblack@eecs.umich.edu ADD_FIELD32(i,29,1); // interrupt 3407435Sgblack@eecs.umich.edu ADD_FIELD32(e,30,1); // error 3417435Sgblack@eecs.umich.edu }; 3427435Sgblack@eecs.umich.edu MDIC mdic; 3437435Sgblack@eecs.umich.edu 3447435Sgblack@eecs.umich.edu struct ICR : public Reg<uint32_t> { // 0x00C0 ICR Register 3457435Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 3467435Sgblack@eecs.umich.edu ADD_FIELD32(txdw,0,1) // tx descr witten back 3477435Sgblack@eecs.umich.edu ADD_FIELD32(txqe,1,1) // tx queue empty 3487435Sgblack@eecs.umich.edu ADD_FIELD32(lsc,2,1) // link status change 3497639Sgblack@eecs.umich.edu ADD_FIELD32(rxseq,3,1) // rcv sequence error 3507639Sgblack@eecs.umich.edu ADD_FIELD32(rxdmt0,4,1) // rcv descriptor min thresh 3517639Sgblack@eecs.umich.edu ADD_FIELD32(rsvd1,5,1) // reserved 3527639Sgblack@eecs.umich.edu ADD_FIELD32(rxo,6,1) // receive overrunn 3537639Sgblack@eecs.umich.edu ADD_FIELD32(rxt0,7,1) // receiver timer interrupt 3547639Sgblack@eecs.umich.edu ADD_FIELD32(mdac,9,1) // mdi/o access complete 3557639Sgblack@eecs.umich.edu ADD_FIELD32(rxcfg,10,1) // recv /c/ ordered sets 3567639Sgblack@eecs.umich.edu ADD_FIELD32(phyint,12,1) // phy interrupt 3577639Sgblack@eecs.umich.edu ADD_FIELD32(gpi1,13,1) // gpi int 1 3587639Sgblack@eecs.umich.edu ADD_FIELD32(gpi2,14,1) // gpi int 2 3597639Sgblack@eecs.umich.edu ADD_FIELD32(txdlow,15,1) // transmit desc low thresh 3607639Sgblack@eecs.umich.edu ADD_FIELD32(srpd,16,1) // small receive packet detected 3617639Sgblack@eecs.umich.edu ADD_FIELD32(ack,17,1); // receive ack frame 3627435Sgblack@eecs.umich.edu ADD_FIELD32(int_assert, 31,1); // interrupt caused a system interrupt 3637435Sgblack@eecs.umich.edu }; 3647435Sgblack@eecs.umich.edu ICR icr; 3657639Sgblack@eecs.umich.edu 3667639Sgblack@eecs.umich.edu uint32_t imr; // register that contains the current interrupt mask 3677639Sgblack@eecs.umich.edu 3687435Sgblack@eecs.umich.edu struct ITR : public Reg<uint32_t> { // 0x00C4 ITR Register 3697639Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 3707639Sgblack@eecs.umich.edu ADD_FIELD32(interval, 0,16); // minimum inter-interrutp inteval 3717435Sgblack@eecs.umich.edu // specified in 256ns interrupts 3727435Sgblack@eecs.umich.edu }; 3737639Sgblack@eecs.umich.edu ITR itr; 3747639Sgblack@eecs.umich.edu 3757639Sgblack@eecs.umich.edu // When CTRL_EXT.IAME and the ICR.INT_ASSERT is 1 an ICR read or write 3767639Sgblack@eecs.umich.edu // causes the IAM register contents to be written into the IMC 3777435Sgblack@eecs.umich.edu // automatically clearing all interrupts that have a bit in the IAM set 3787435Sgblack@eecs.umich.edu uint32_t iam; 3797435Sgblack@eecs.umich.edu 3807639Sgblack@eecs.umich.edu struct RCTL : public Reg<uint32_t> { // 0x0100 RCTL Register 3817639Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 3827435Sgblack@eecs.umich.edu ADD_FIELD32(rst,0,1); // Reset 3837435Sgblack@eecs.umich.edu ADD_FIELD32(en,1,1); // Enable 3847435Sgblack@eecs.umich.edu ADD_FIELD32(sbp,2,1); // Store bad packets 3857435Sgblack@eecs.umich.edu ADD_FIELD32(upe,3,1); // Unicast Promiscuous enabled 3867639Sgblack@eecs.umich.edu ADD_FIELD32(mpe,4,1); // Multicast promiscuous enabled 3877639Sgblack@eecs.umich.edu ADD_FIELD32(lpe,5,1); // long packet reception enabled 3887639Sgblack@eecs.umich.edu ADD_FIELD32(lbm,6,2); // 3897639Sgblack@eecs.umich.edu ADD_FIELD32(rdmts,8,2); // 3907639Sgblack@eecs.umich.edu ADD_FIELD32(mo,12,2); // 3917435Sgblack@eecs.umich.edu ADD_FIELD32(mdr,14,1); // 3927639Sgblack@eecs.umich.edu ADD_FIELD32(bam,15,1); // 3937639Sgblack@eecs.umich.edu ADD_FIELD32(bsize,16,2); // 3947639Sgblack@eecs.umich.edu ADD_FIELD32(vfe,18,1); // 3957639Sgblack@eecs.umich.edu ADD_FIELD32(cfien,19,1); // 3967639Sgblack@eecs.umich.edu ADD_FIELD32(cfi,20,1); // 3977435Sgblack@eecs.umich.edu ADD_FIELD32(dpf,22,1); // discard pause frames 3987639Sgblack@eecs.umich.edu ADD_FIELD32(pmcf,23,1); // pass mac control frames 3997639Sgblack@eecs.umich.edu ADD_FIELD32(bsex,25,1); // buffer size extension 4007639Sgblack@eecs.umich.edu ADD_FIELD32(secrc,26,1); // strip ethernet crc from incoming packet 4017639Sgblack@eecs.umich.edu int descSize() 4027639Sgblack@eecs.umich.edu { 4037435Sgblack@eecs.umich.edu switch(bsize()) { 4047639Sgblack@eecs.umich.edu case 0: return bsex() == 0 ? 2048 : -1; 4057639Sgblack@eecs.umich.edu case 1: return bsex() == 0 ? 1024 : 16384; 4067639Sgblack@eecs.umich.edu case 2: return bsex() == 0 ? 512 : 8192; 4077639Sgblack@eecs.umich.edu case 3: return bsex() == 0 ? 256 : 4096; 4087639Sgblack@eecs.umich.edu default: 4097435Sgblack@eecs.umich.edu return -1; 4107435Sgblack@eecs.umich.edu } 4117435Sgblack@eecs.umich.edu } 4127435Sgblack@eecs.umich.edu }; 4137639Sgblack@eecs.umich.edu RCTL rctl; 4147639Sgblack@eecs.umich.edu 4157639Sgblack@eecs.umich.edu struct FCTTV : public Reg<uint32_t> { // 0x0170 FCTTV 4167639Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 4177639Sgblack@eecs.umich.edu ADD_FIELD32(ttv,0,16); // Transmit Timer Value 4187435Sgblack@eecs.umich.edu }; 4197639Sgblack@eecs.umich.edu FCTTV fcttv; 4207639Sgblack@eecs.umich.edu 4217639Sgblack@eecs.umich.edu struct TCTL : public Reg<uint32_t> { // 0x0400 TCTL Register 4227639Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 4237639Sgblack@eecs.umich.edu ADD_FIELD32(rst,0,1); // Reset 4247435Sgblack@eecs.umich.edu ADD_FIELD32(en,1,1); // Enable 4257639Sgblack@eecs.umich.edu ADD_FIELD32(bce,2,1); // busy check enable 4267639Sgblack@eecs.umich.edu ADD_FIELD32(psp,3,1); // pad short packets 4277639Sgblack@eecs.umich.edu ADD_FIELD32(ct,4,8); // collision threshold 4287639Sgblack@eecs.umich.edu ADD_FIELD32(cold,12,10); // collision distance 4297435Sgblack@eecs.umich.edu ADD_FIELD32(swxoff,22,1); // software xoff transmission 4307639Sgblack@eecs.umich.edu ADD_FIELD32(pbe,23,1); // packet burst enable 4317639Sgblack@eecs.umich.edu ADD_FIELD32(rtlc,24,1); // retransmit late collisions 4327639Sgblack@eecs.umich.edu ADD_FIELD32(nrtu,25,1); // on underrun no TX 4337639Sgblack@eecs.umich.edu ADD_FIELD32(mulr,26,1); // multiple request 4347639Sgblack@eecs.umich.edu }; 4357639Sgblack@eecs.umich.edu TCTL tctl; 4367639Sgblack@eecs.umich.edu 4377639Sgblack@eecs.umich.edu struct PBA : public Reg<uint32_t> { // 0x1000 PBA Register 4387639Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 4397639Sgblack@eecs.umich.edu ADD_FIELD32(rxa,0,16); 4407435Sgblack@eecs.umich.edu ADD_FIELD32(txa,16,16); 4417435Sgblack@eecs.umich.edu }; 4427435Sgblack@eecs.umich.edu PBA pba; 4437639Sgblack@eecs.umich.edu 4447639Sgblack@eecs.umich.edu struct FCRTL : public Reg<uint32_t> { // 0x2160 FCRTL Register 4457639Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 4467639Sgblack@eecs.umich.edu ADD_FIELD32(rtl,3,28); // make this bigger than the spec so we can have 4477639Sgblack@eecs.umich.edu // a larger buffer 4487639Sgblack@eecs.umich.edu ADD_FIELD32(xone, 31,1); 4497639Sgblack@eecs.umich.edu }; 4507435Sgblack@eecs.umich.edu FCRTL fcrtl; 4517435Sgblack@eecs.umich.edu 4527435Sgblack@eecs.umich.edu struct FCRTH : public Reg<uint32_t> { // 0x2168 FCRTL Register 4537435Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 4547435Sgblack@eecs.umich.edu ADD_FIELD32(rth,3,13); // make this bigger than the spec so we can have 4557639Sgblack@eecs.umich.edu //a larger buffer 4567639Sgblack@eecs.umich.edu ADD_FIELD32(xfce, 31,1); 4577639Sgblack@eecs.umich.edu }; 4587639Sgblack@eecs.umich.edu FCRTH fcrth; 4597639Sgblack@eecs.umich.edu 4607639Sgblack@eecs.umich.edu struct RDBA : public Reg<uint64_t> { // 0x2800 RDBA Register 4617639Sgblack@eecs.umich.edu using Reg<uint64_t>::operator=; 4627435Sgblack@eecs.umich.edu ADD_FIELD64(rdbal,0,32); // base address of rx descriptor ring 4637639Sgblack@eecs.umich.edu ADD_FIELD64(rdbah,32,32); // base address of rx descriptor ring 4647639Sgblack@eecs.umich.edu }; 4657639Sgblack@eecs.umich.edu RDBA rdba; 4667639Sgblack@eecs.umich.edu 4677435Sgblack@eecs.umich.edu struct RDLEN : public Reg<uint32_t> { // 0x2808 RDLEN Register 4687435Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 4697435Sgblack@eecs.umich.edu ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer 4707639Sgblack@eecs.umich.edu }; 4717639Sgblack@eecs.umich.edu RDLEN rdlen; 4727435Sgblack@eecs.umich.edu 4737639Sgblack@eecs.umich.edu struct RDH : public Reg<uint32_t> { // 0x2810 RDH Register 4747639Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 4757435Sgblack@eecs.umich.edu ADD_FIELD32(rdh,0,16); // head of the descriptor ring 4767435Sgblack@eecs.umich.edu }; 4777435Sgblack@eecs.umich.edu RDH rdh; 4787639Sgblack@eecs.umich.edu 4797639Sgblack@eecs.umich.edu struct RDT : public Reg<uint32_t> { // 0x2818 RDT Register 4807639Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 4817639Sgblack@eecs.umich.edu ADD_FIELD32(rdt,0,16); // tail of the descriptor ring 4827639Sgblack@eecs.umich.edu }; 4837639Sgblack@eecs.umich.edu RDT rdt; 4847639Sgblack@eecs.umich.edu 4857435Sgblack@eecs.umich.edu struct RDTR : public Reg<uint32_t> { // 0x2820 RDTR Register 4867639Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 4877639Sgblack@eecs.umich.edu ADD_FIELD32(delay,0,16); // receive delay timer 4887435Sgblack@eecs.umich.edu ADD_FIELD32(fpd, 31,1); // flush partial descriptor block ?? 4897435Sgblack@eecs.umich.edu }; 4907435Sgblack@eecs.umich.edu RDTR rdtr; 4917639Sgblack@eecs.umich.edu 4927639Sgblack@eecs.umich.edu struct RXDCTL : public Reg<uint32_t> { // 0x2828 RXDCTL Register 4937639Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 4947639Sgblack@eecs.umich.edu ADD_FIELD32(pthresh,0,6); // prefetch threshold, less that this 4957639Sgblack@eecs.umich.edu // consider prefetch 4967639Sgblack@eecs.umich.edu ADD_FIELD32(hthresh,8,6); // number of descriptors in host mem to 4977639Sgblack@eecs.umich.edu // consider prefetch 4987435Sgblack@eecs.umich.edu ADD_FIELD32(wthresh,16,6); // writeback threshold 4997639Sgblack@eecs.umich.edu ADD_FIELD32(gran,24,1); // granularity 0 = desc, 1 = cacheline 5007639Sgblack@eecs.umich.edu }; 5017435Sgblack@eecs.umich.edu RXDCTL rxdctl; 5027435Sgblack@eecs.umich.edu 5037435Sgblack@eecs.umich.edu struct RADV : public Reg<uint32_t> { // 0x282C RADV Register 5047639Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 5057639Sgblack@eecs.umich.edu ADD_FIELD32(idv,0,16); // absolute interrupt delay 5067435Sgblack@eecs.umich.edu }; 5077639Sgblack@eecs.umich.edu RADV radv; 5087639Sgblack@eecs.umich.edu 5097435Sgblack@eecs.umich.edu struct RSRPD : public Reg<uint32_t> { // 0x2C00 RSRPD Register 5107435Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 5117435Sgblack@eecs.umich.edu ADD_FIELD32(idv,0,12); // size to interrutp on small packets 5127639Sgblack@eecs.umich.edu }; 5137639Sgblack@eecs.umich.edu RSRPD rsrpd; 5147435Sgblack@eecs.umich.edu 5157435Sgblack@eecs.umich.edu struct TDBA : public Reg<uint64_t> { // 0x3800 TDBAL Register 5167639Sgblack@eecs.umich.edu using Reg<uint64_t>::operator=; 5177435Sgblack@eecs.umich.edu ADD_FIELD64(tdbal,0,32); // base address of transmit descriptor ring 5187435Sgblack@eecs.umich.edu ADD_FIELD64(tdbah,32,32); // base address of transmit descriptor ring 5197639Sgblack@eecs.umich.edu }; 5207639Sgblack@eecs.umich.edu TDBA tdba; 5217435Sgblack@eecs.umich.edu 5227435Sgblack@eecs.umich.edu struct TDLEN : public Reg<uint32_t> { // 0x3808 TDLEN Register 5237639Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 5247639Sgblack@eecs.umich.edu ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer 5257435Sgblack@eecs.umich.edu }; 5267435Sgblack@eecs.umich.edu TDLEN tdlen; 5277435Sgblack@eecs.umich.edu 5287435Sgblack@eecs.umich.edu struct TDH : public Reg<uint32_t> { // 0x3810 TDH Register 5297435Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 5307639Sgblack@eecs.umich.edu ADD_FIELD32(tdh,0,16); // head of the descriptor ring 5317639Sgblack@eecs.umich.edu }; 5327435Sgblack@eecs.umich.edu TDH tdh; 5337639Sgblack@eecs.umich.edu 5347639Sgblack@eecs.umich.edu struct TDT : public Reg<uint32_t> { // 0x3818 TDT Register 5357435Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 5367435Sgblack@eecs.umich.edu ADD_FIELD32(tdt,0,16); // tail of the descriptor ring 5377435Sgblack@eecs.umich.edu }; 5387639Sgblack@eecs.umich.edu TDT tdt; 5397639Sgblack@eecs.umich.edu 5407435Sgblack@eecs.umich.edu struct TIDV : public Reg<uint32_t> { // 0x3820 TIDV Register 5417639Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 5427639Sgblack@eecs.umich.edu ADD_FIELD32(idv,0,16); // interrupt delay 5437435Sgblack@eecs.umich.edu }; 5447435Sgblack@eecs.umich.edu TIDV tidv; 5457435Sgblack@eecs.umich.edu 5467435Sgblack@eecs.umich.edu struct TXDCTL : public Reg<uint32_t> { // 0x3828 TXDCTL Register 5477435Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 5487639Sgblack@eecs.umich.edu ADD_FIELD32(pthresh, 0,6); // if number of descriptors control has is 5497639Sgblack@eecs.umich.edu // below this number, a prefetch is considered 5507435Sgblack@eecs.umich.edu ADD_FIELD32(hthresh,8,8); // number of valid descriptors is host memory 5517639Sgblack@eecs.umich.edu // before a prefetch is considered 5527639Sgblack@eecs.umich.edu ADD_FIELD32(wthresh,16,6); // number of descriptors to keep until 5537435Sgblack@eecs.umich.edu // writeback is considered 5547435Sgblack@eecs.umich.edu ADD_FIELD32(gran, 24,1); // granulatiry of above values (0 = cacheline, 5557435Sgblack@eecs.umich.edu // 1 == desscriptor) 5567639Sgblack@eecs.umich.edu ADD_FIELD32(lwthresh,25,7); // xmit descriptor low thresh, interrupt 5577639Sgblack@eecs.umich.edu // below this level 5587435Sgblack@eecs.umich.edu }; 5597639Sgblack@eecs.umich.edu TXDCTL txdctl; 5607639Sgblack@eecs.umich.edu 5617435Sgblack@eecs.umich.edu struct TADV : public Reg<uint32_t> { // 0x382C TADV Register 5627435Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 5637435Sgblack@eecs.umich.edu ADD_FIELD32(idv,0,16); // absolute interrupt delay 5647435Sgblack@eecs.umich.edu }; 5657639Sgblack@eecs.umich.edu TADV tadv; 5667639Sgblack@eecs.umich.edu 5677435Sgblack@eecs.umich.edu struct RXCSUM : public Reg<uint32_t> { // 0x5000 RXCSUM Register 5687639Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 5697639Sgblack@eecs.umich.edu ADD_FIELD32(pcss,0,8); 5707435Sgblack@eecs.umich.edu ADD_FIELD32(ipofld,8,1); 5717435Sgblack@eecs.umich.edu ADD_FIELD32(tuofld,9,1); 5727435Sgblack@eecs.umich.edu }; 5737435Sgblack@eecs.umich.edu RXCSUM rxcsum; 5747435Sgblack@eecs.umich.edu 5757435Sgblack@eecs.umich.edu struct MANC : public Reg<uint32_t> { // 0x5820 MANC Register 5767639Sgblack@eecs.umich.edu using Reg<uint32_t>::operator=; 5777639Sgblack@eecs.umich.edu ADD_FIELD32(smbus,0,1); // SMBus enabled ##### 5787435Sgblack@eecs.umich.edu ADD_FIELD32(asf,1,1); // ASF enabled ##### 5797435Sgblack@eecs.umich.edu ADD_FIELD32(ronforce,2,1); // reset of force 5807435Sgblack@eecs.umich.edu ADD_FIELD32(rsvd,3,5); // reserved 5817639Sgblack@eecs.umich.edu ADD_FIELD32(rmcp1,8,1); // rcmp1 filtering 5827639Sgblack@eecs.umich.edu ADD_FIELD32(rmcp2,9,1); // rcmp2 filtering 5837435Sgblack@eecs.umich.edu ADD_FIELD32(ipv4,10,1); // enable ipv4 5847639Sgblack@eecs.umich.edu ADD_FIELD32(ipv6,11,1); // enable ipv6 5857639Sgblack@eecs.umich.edu ADD_FIELD32(snap,12,1); // accept snap 5867435Sgblack@eecs.umich.edu ADD_FIELD32(arp,13,1); // filter arp ##### 5877435Sgblack@eecs.umich.edu ADD_FIELD32(neighbor,14,1); // neighbor discovery 5887435Sgblack@eecs.umich.edu ADD_FIELD32(arp_resp,15,1); // arp response 5897435Sgblack@eecs.umich.edu ADD_FIELD32(tcorst,16,1); // tco reset happened 5907435Sgblack@eecs.umich.edu ADD_FIELD32(rcvtco,17,1); // receive tco enabled ###### 5917435Sgblack@eecs.umich.edu ADD_FIELD32(blkphyrst,18,1);// block phy resets ######## 5927435Sgblack@eecs.umich.edu ADD_FIELD32(rcvall,19,1); // receive all 5937435Sgblack@eecs.umich.edu ADD_FIELD32(macaddrfltr,20,1); // mac address filtering ###### 5947639Sgblack@eecs.umich.edu ADD_FIELD32(mng2host,21,1); // mng2 host packets ####### 5957639Sgblack@eecs.umich.edu ADD_FIELD32(ipaddrfltr,22,1); // ip address filtering 5967639Sgblack@eecs.umich.edu ADD_FIELD32(xsumfilter,23,1); // checksum filtering 5977639Sgblack@eecs.umich.edu ADD_FIELD32(brfilter,24,1); // broadcast filtering 5987639Sgblack@eecs.umich.edu ADD_FIELD32(smbreq,25,1); // smb request 5997435Sgblack@eecs.umich.edu ADD_FIELD32(smbgnt,26,1); // smb grant 6007435Sgblack@eecs.umich.edu ADD_FIELD32(smbclkin,27,1); // smbclkin 6017435Sgblack@eecs.umich.edu ADD_FIELD32(smbdatain,28,1); // smbdatain 6027435Sgblack@eecs.umich.edu ADD_FIELD32(smbdataout,29,1); // smb data out 6037435Sgblack@eecs.umich.edu ADD_FIELD32(smbclkout,30,1); // smb clock out 6047639Sgblack@eecs.umich.edu }; 6057639Sgblack@eecs.umich.edu MANC manc; 6067639Sgblack@eecs.umich.edu 6077639Sgblack@eecs.umich.edu void serialize(std::ostream &os) 6087639Sgblack@eecs.umich.edu { 6097435Sgblack@eecs.umich.edu paramOut(os, "ctrl", ctrl._data); 6107639Sgblack@eecs.umich.edu paramOut(os, "sts", sts._data); 6117639Sgblack@eecs.umich.edu paramOut(os, "eecd", eecd._data); 6127639Sgblack@eecs.umich.edu paramOut(os, "eerd", eerd._data); 6137639Sgblack@eecs.umich.edu paramOut(os, "ctrl_ext", ctrl_ext._data); 6147639Sgblack@eecs.umich.edu paramOut(os, "mdic", mdic._data); 6157435Sgblack@eecs.umich.edu paramOut(os, "icr", icr._data); 6167435Sgblack@eecs.umich.edu SERIALIZE_SCALAR(imr); 6177435Sgblack@eecs.umich.edu paramOut(os, "itr", itr._data); 6187435Sgblack@eecs.umich.edu SERIALIZE_SCALAR(iam); 6197435Sgblack@eecs.umich.edu paramOut(os, "rctl", rctl._data); 6207639Sgblack@eecs.umich.edu paramOut(os, "fcttv", fcttv._data); 6217639Sgblack@eecs.umich.edu paramOut(os, "tctl", tctl._data); 6227639Sgblack@eecs.umich.edu paramOut(os, "pba", pba._data); 6237639Sgblack@eecs.umich.edu paramOut(os, "fcrtl", fcrtl._data); 6247639Sgblack@eecs.umich.edu paramOut(os, "fcrth", fcrth._data); 6257435Sgblack@eecs.umich.edu paramOut(os, "rdba", rdba._data); 6267639Sgblack@eecs.umich.edu paramOut(os, "rdlen", rdlen._data); 6277639Sgblack@eecs.umich.edu paramOut(os, "rdh", rdh._data); 6287639Sgblack@eecs.umich.edu paramOut(os, "rdt", rdt._data); 6297639Sgblack@eecs.umich.edu paramOut(os, "rdtr", rdtr._data); 6307639Sgblack@eecs.umich.edu paramOut(os, "rxdctl", rxdctl._data); 6317435Sgblack@eecs.umich.edu paramOut(os, "radv", radv._data); 6327435Sgblack@eecs.umich.edu paramOut(os, "rsrpd", rsrpd._data); 6337435Sgblack@eecs.umich.edu paramOut(os, "tdba", tdba._data); 6347639Sgblack@eecs.umich.edu paramOut(os, "tdlen", tdlen._data); 6357639Sgblack@eecs.umich.edu paramOut(os, "tdh", tdh._data); 6367639Sgblack@eecs.umich.edu paramOut(os, "tdt", tdt._data); 6377639Sgblack@eecs.umich.edu paramOut(os, "tidv", tidv._data); 6387639Sgblack@eecs.umich.edu paramOut(os, "txdctl", txdctl._data); 6397435Sgblack@eecs.umich.edu paramOut(os, "tadv", tadv._data); 6407639Sgblack@eecs.umich.edu paramOut(os, "rxcsum", rxcsum._data); 6417639Sgblack@eecs.umich.edu paramOut(os, "manc", manc._data); 6427639Sgblack@eecs.umich.edu } 6437639Sgblack@eecs.umich.edu 6447639Sgblack@eecs.umich.edu void unserialize(Checkpoint *cp, const std::string §ion) 6457435Sgblack@eecs.umich.edu { 6467435Sgblack@eecs.umich.edu paramIn(cp, section, "ctrl", ctrl._data); 6477435Sgblack@eecs.umich.edu paramIn(cp, section, "sts", sts._data); 6487435Sgblack@eecs.umich.edu paramIn(cp, section, "eecd", eecd._data); 6497435Sgblack@eecs.umich.edu paramIn(cp, section, "eerd", eerd._data); 6507435Sgblack@eecs.umich.edu paramIn(cp, section, "ctrl_ext", ctrl_ext._data); 6517435Sgblack@eecs.umich.edu paramIn(cp, section, "mdic", mdic._data); 6527639Sgblack@eecs.umich.edu paramIn(cp, section, "icr", icr._data); 6537639Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(imr); 6547639Sgblack@eecs.umich.edu paramIn(cp, section, "itr", itr._data); 6557639Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(iam); 6567639Sgblack@eecs.umich.edu paramIn(cp, section, "rctl", rctl._data); 6577435Sgblack@eecs.umich.edu paramIn(cp, section, "fcttv", fcttv._data); 6587639Sgblack@eecs.umich.edu paramIn(cp, section, "tctl", tctl._data); 6597639Sgblack@eecs.umich.edu paramIn(cp, section, "pba", pba._data); 6607639Sgblack@eecs.umich.edu paramIn(cp, section, "fcrtl", fcrtl._data); 6617639Sgblack@eecs.umich.edu paramIn(cp, section, "fcrth", fcrth._data); 6627639Sgblack@eecs.umich.edu paramIn(cp, section, "rdba", rdba._data); 6637435Sgblack@eecs.umich.edu paramIn(cp, section, "rdlen", rdlen._data); 6647435Sgblack@eecs.umich.edu paramIn(cp, section, "rdh", rdh._data); 6657435Sgblack@eecs.umich.edu paramIn(cp, section, "rdt", rdt._data); 6667435Sgblack@eecs.umich.edu paramIn(cp, section, "rdtr", rdtr._data); 6677435Sgblack@eecs.umich.edu paramIn(cp, section, "rxdctl", rxdctl._data); 6687435Sgblack@eecs.umich.edu paramIn(cp, section, "radv", radv._data); 6697435Sgblack@eecs.umich.edu paramIn(cp, section, "rsrpd", rsrpd._data); 6707639Sgblack@eecs.umich.edu paramIn(cp, section, "tdba", tdba._data); 6717639Sgblack@eecs.umich.edu paramIn(cp, section, "tdlen", tdlen._data); 6727639Sgblack@eecs.umich.edu paramIn(cp, section, "tdh", tdh._data); 6737639Sgblack@eecs.umich.edu paramIn(cp, section, "tdt", tdt._data); 6747639Sgblack@eecs.umich.edu paramIn(cp, section, "tidv", tidv._data); 6757435Sgblack@eecs.umich.edu paramIn(cp, section, "txdctl", txdctl._data); 6767639Sgblack@eecs.umich.edu paramIn(cp, section, "tadv", tadv._data); 6777639Sgblack@eecs.umich.edu paramIn(cp, section, "rxcsum", rxcsum._data); 6787639Sgblack@eecs.umich.edu paramIn(cp, section, "manc", manc._data); 6797639Sgblack@eecs.umich.edu } 6807639Sgblack@eecs.umich.edu}; 6817435Sgblack@eecs.umich.edu} // iGbReg namespace 6827435Sgblack@eecs.umich.edu