i8254xGBe_defs.hh revision 4294
16657Snate@binkert.org/* 26657Snate@binkert.org * Copyright (c) 2006 The Regents of The University of Michigan 36657Snate@binkert.org * All rights reserved. 46657Snate@binkert.org * 56657Snate@binkert.org * Redistribution and use in source and binary forms, with or without 66657Snate@binkert.org * modification, are permitted provided that the following conditions are 76657Snate@binkert.org * met: redistributions of source code must retain the above copyright 86657Snate@binkert.org * notice, this list of conditions and the following disclaimer; 96657Snate@binkert.org * redistributions in binary form must reproduce the above copyright 106657Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 116657Snate@binkert.org * documentation and/or other materials provided with the distribution; 126657Snate@binkert.org * neither the name of the copyright holders nor the names of its 136657Snate@binkert.org * contributors may be used to endorse or promote products derived from 146657Snate@binkert.org * this software without specific prior written permission. 156657Snate@binkert.org * 166657Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176657Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186657Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196657Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206657Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216657Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226657Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236657Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246657Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256657Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266657Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276657Snate@binkert.org * 286999Snate@binkert.org * Authors: Ali Saidi 296657Snate@binkert.org */ 306657Snate@binkert.org 316657Snate@binkert.org/* @file 329302Snilay@cs.wisc.edu * Register and structure descriptions for Intel's 8254x line of gigabit ethernet controllers. 336657Snate@binkert.org */ 346657Snate@binkert.org#include "base/bitfield.hh" 356657Snate@binkert.org 366657Snate@binkert.orgnamespace iGbReg { 376657Snate@binkert.org 386657Snate@binkert.org 396657Snate@binkert.org// Registers used by the Intel GbE NIC 406657Snate@binkert.orgconst uint32_t REG_CTRL = 0x00000; 416657Snate@binkert.orgconst uint32_t REG_STATUS = 0x00008; 426657Snate@binkert.orgconst uint32_t REG_EECD = 0x00010; 436657Snate@binkert.orgconst uint32_t REG_EERD = 0x00014; 446657Snate@binkert.orgconst uint32_t REG_CTRL_EXT = 0x00018; 456657Snate@binkert.orgconst uint32_t REG_MDIC = 0x00020; 466657Snate@binkert.orgconst uint32_t REG_FCAL = 0x00028; 476657Snate@binkert.orgconst uint32_t REG_FCAH = 0x0002C; 486657Snate@binkert.orgconst uint32_t REG_FCT = 0x00030; 496657Snate@binkert.orgconst uint32_t REG_VET = 0x00038; 506657Snate@binkert.orgconst uint32_t REG_PBA = 0x01000; 516657Snate@binkert.orgconst uint32_t REG_ICR = 0x000C0; 526657Snate@binkert.orgconst uint32_t REG_ITR = 0x000C4; 536657Snate@binkert.orgconst uint32_t REG_ICS = 0x000C8; 546657Snate@binkert.orgconst uint32_t REG_IMS = 0x000D0; 556882SBrad.Beckmann@amd.comconst uint32_t REG_IMC = 0x000D8; 566657Snate@binkert.orgconst uint32_t REG_IAM = 0x000E0; 576657Snate@binkert.orgconst uint32_t REG_RCTL = 0x00100; 586657Snate@binkert.orgconst uint32_t REG_FCTTV = 0x00170; 596657Snate@binkert.orgconst uint32_t REG_TIPG = 0x00410; 606657Snate@binkert.orgconst uint32_t REG_AIFS = 0x00458; 616657Snate@binkert.orgconst uint32_t REG_LEDCTL = 0x00e00; 626657Snate@binkert.orgconst uint32_t REG_FCRTL = 0x02160; 636657Snate@binkert.orgconst uint32_t REG_FCRTH = 0x02168; 646657Snate@binkert.orgconst uint32_t REG_RDBAL = 0x02800; 656657Snate@binkert.orgconst uint32_t REG_RDBAH = 0x02804; 666657Snate@binkert.orgconst uint32_t REG_RDLEN = 0x02808; 676657Snate@binkert.orgconst uint32_t REG_RDH = 0x02810; 686657Snate@binkert.orgconst uint32_t REG_RDT = 0x02818; 696657Snate@binkert.orgconst uint32_t REG_RDTR = 0x02820; 706657Snate@binkert.orgconst uint32_t REG_RXDCTL = 0x02828; 716657Snate@binkert.orgconst uint32_t REG_RADV = 0x0282C; 726657Snate@binkert.orgconst uint32_t REG_TCTL = 0x00400; 736657Snate@binkert.orgconst uint32_t REG_TDBAL = 0x03800; 746657Snate@binkert.orgconst uint32_t REG_TDBAH = 0x03804; 756657Snate@binkert.orgconst uint32_t REG_TDLEN = 0x03808; 766657Snate@binkert.orgconst uint32_t REG_TDH = 0x03810; 776657Snate@binkert.orgconst uint32_t REG_TDT = 0x03818; 786657Snate@binkert.orgconst uint32_t REG_TIDV = 0x03820; 796657Snate@binkert.orgconst uint32_t REG_TXDCTL = 0x03828; 806657Snate@binkert.orgconst uint32_t REG_TADV = 0x0382C; 816657Snate@binkert.orgconst uint32_t REG_CRCERRS = 0x04000; 826657Snate@binkert.orgconst uint32_t REG_RXCSUM = 0x05000; 836657Snate@binkert.orgconst uint32_t REG_MTA = 0x05200; 846657Snate@binkert.orgconst uint32_t REG_RAL = 0x05400; 856657Snate@binkert.orgconst uint32_t REG_RAH = 0x05404; 866657Snate@binkert.orgconst uint32_t REG_VFTA = 0x05600; 876657Snate@binkert.org 886657Snate@binkert.orgconst uint32_t REG_WUC = 0x05800; 896657Snate@binkert.orgconst uint32_t REG_MANC = 0x05820; 906657Snate@binkert.org 916657Snate@binkert.orgconst uint8_t EEPROM_READ_OPCODE_SPI = 0x03; 926657Snate@binkert.orgconst uint8_t EEPROM_RDSR_OPCODE_SPI = 0x05; 936657Snate@binkert.orgconst uint8_t EEPROM_SIZE = 64; 946657Snate@binkert.orgconst uint16_t EEPROM_CSUM = 0xBABA; 956657Snate@binkert.org 966657Snate@binkert.orgconst uint8_t VLAN_FILTER_TABLE_SIZE = 128; 976657Snate@binkert.orgconst uint8_t RCV_ADDRESS_TABLE_SIZE = 16; 986657Snate@binkert.orgconst uint8_t MULTICAST_TABLE_SIZE = 128; 996657Snate@binkert.orgconst uint32_t STATS_REGS_SIZE = 0x124; 1006657Snate@binkert.org 1016657Snate@binkert.org 1026657Snate@binkert.org// Registers in that are accessed in the PHY 1036657Snate@binkert.orgconst uint8_t PHY_PSTATUS = 0x1; 1048086SBrad.Beckmann@amd.comconst uint8_t PHY_PID = 0x2; 1058086SBrad.Beckmann@amd.comconst uint8_t PHY_EPID = 0x3; 1068086SBrad.Beckmann@amd.comconst uint8_t PHY_GSTATUS = 10; 1076657Snate@binkert.orgconst uint8_t PHY_EPSTATUS = 15; 1086657Snate@binkert.orgconst uint8_t PHY_AGC = 18; 1096657Snate@binkert.org 1106657Snate@binkert.org// Receive Descriptor Status Flags 1119298Snilay@cs.wisc.educonst uint8_t RXDS_PIF = 0x80; 1126657Snate@binkert.orgconst uint8_t RXDS_IPCS = 0x40; 1136657Snate@binkert.orgconst uint8_t RXDS_TCPCS = 0x20; 1146657Snate@binkert.orgconst uint8_t RXDS_UDPCS = 0x10; 1156657Snate@binkert.orgconst uint8_t RXDS_VP = 0x08; 1166657Snate@binkert.orgconst uint8_t RXDS_IXSM = 0x04; 1176657Snate@binkert.orgconst uint8_t RXDS_EOP = 0x02; 1186657Snate@binkert.orgconst uint8_t RXDS_DD = 0x01; 1196657Snate@binkert.org 1206657Snate@binkert.org// Receive Descriptor Error Flags 1216657Snate@binkert.orgconst uint8_t RXDE_RXE = 0x80; 1226657Snate@binkert.orgconst uint8_t RXDE_IPE = 0x40; 1236657Snate@binkert.orgconst uint8_t RXDE_TCPE = 0x20; 1246657Snate@binkert.orgconst uint8_t RXDE_SEQ = 0x04; 1256657Snate@binkert.orgconst uint8_t RXDE_SE = 0x02; 1266657Snate@binkert.orgconst uint8_t RXDE_CE = 0x01; 1276657Snate@binkert.org 1286657Snate@binkert.org// Interrupt types 1296657Snate@binkert.orgenum IntTypes 1306657Snate@binkert.org{ 1316657Snate@binkert.org IT_NONE = 0x00000, //dummy value 1326657Snate@binkert.org IT_TXDW = 0x00001, 1336657Snate@binkert.org IT_TXQE = 0x00002, 1346657Snate@binkert.org IT_LSC = 0x00004, 1356657Snate@binkert.org IT_RXSEQ = 0x00008, 1366657Snate@binkert.org IT_RXDMT = 0x00010, 1376657Snate@binkert.org IT_RXO = 0x00040, 1386657Snate@binkert.org IT_RXT = 0x00080, 1396657Snate@binkert.org IT_MADC = 0x00200, 1406657Snate@binkert.org IT_RXCFG = 0x00400, 1416657Snate@binkert.org IT_GPI0 = 0x02000, 1426657Snate@binkert.org IT_GPI1 = 0x04000, 1436657Snate@binkert.org IT_TXDLOW = 0x08000, 1446657Snate@binkert.org IT_SRPD = 0x10000, 1456657Snate@binkert.org IT_ACK = 0x20000 1466657Snate@binkert.org}; 1476657Snate@binkert.org 1489298Snilay@cs.wisc.edu// Receive Descriptor struct 1496657Snate@binkert.orgstruct RxDesc { 1506657Snate@binkert.org Addr buf; 1516657Snate@binkert.org uint16_t len; 1526657Snate@binkert.org uint16_t csum; 1536657Snate@binkert.org uint8_t status; 1546657Snate@binkert.org uint8_t errors; 1559302Snilay@cs.wisc.edu uint16_t vlan; 1569302Snilay@cs.wisc.edu}; 1579302Snilay@cs.wisc.edu 1586657Snate@binkert.orgstruct TxDesc { 1596657Snate@binkert.org uint64_t d1; 1606657Snate@binkert.org uint64_t d2; 1616657Snate@binkert.org}; 1626657Snate@binkert.org 1636657Snate@binkert.orgnamespace TxdOp { 1646657Snate@binkert.orgconst uint8_t TXD_CNXT = 0x0; 1656657Snate@binkert.orgconst uint8_t TXD_DATA = 0x1; 1666882SBrad.Beckmann@amd.com 1676882SBrad.Beckmann@amd.combool isLegacy(TxDesc *d) { return !bits(d->d2,29,29); } 1686882SBrad.Beckmann@amd.comuint8_t getType(TxDesc *d) { return bits(d->d2, 23,20); } 1698086SBrad.Beckmann@amd.combool isContext(TxDesc *d) { return !isLegacy(d) && getType(d) == TXD_CNXT; } 1708086SBrad.Beckmann@amd.combool isData(TxDesc *d) { return !isLegacy(d) && getType(d) == TXD_DATA; } 1718086SBrad.Beckmann@amd.com 1729298Snilay@cs.wisc.eduAddr getBuf(TxDesc *d) { assert(isLegacy(d) || isData(d)); return d->d1; } 1736657Snate@binkert.orgAddr getLen(TxDesc *d) { if (isLegacy(d)) return bits(d->d2,15,0); else return bits(d->d2, 19,0); } 1746657Snate@binkert.orgvoid setDd(TxDesc *d) 1756657Snate@binkert.org{ 1766657Snate@binkert.org replaceBits(d->d2, 35, 32, ULL(1)); 1776657Snate@binkert.org} 1786657Snate@binkert.org 1796657Snate@binkert.orgbool ide(TxDesc *d) { return bits(d->d2, 31,31); } 1809298Snilay@cs.wisc.edubool vle(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 30,30); } 1819298Snilay@cs.wisc.edubool rs(TxDesc *d) { return bits(d->d2, 27,27); } 1829298Snilay@cs.wisc.edubool ic(TxDesc *d) { assert(isLegacy(d) || isData(d)); return isLegacy(d) && bits(d->d2, 26,26); } 1839298Snilay@cs.wisc.edubool tse(TxDesc *d) { return (isData(d) || isContext(d)) && bits(d->d2, 26,26); } 1849298Snilay@cs.wisc.edubool ifcs(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 25,25); } 1859298Snilay@cs.wisc.edubool eop(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 24,24); } 1869298Snilay@cs.wisc.edubool ip(TxDesc *d) { assert(isContext(d)); return bits(d->d2, 25,25); } 1879298Snilay@cs.wisc.edubool tcp(TxDesc *d) { assert(isContext(d)); return bits(d->d2, 24,24); } 1889298Snilay@cs.wisc.edu 1899298Snilay@cs.wisc.eduuint8_t getCso(TxDesc *d) { assert(isLegacy(d)); return bits(d->d2, 23,16); } 1909298Snilay@cs.wisc.eduuint8_t getCss(TxDesc *d) { assert(isLegacy(d)); return bits(d->d2, 47,40); } 1919298Snilay@cs.wisc.edu 1926657Snate@binkert.orgbool ixsm(TxDesc *d) { return isData(d) && bits(d->d2, 40,40); } 1936657Snate@binkert.orgbool txsm(TxDesc *d) { return isData(d) && bits(d->d2, 41,41); } 1946657Snate@binkert.org 1956657Snate@binkert.orgint tucse(TxDesc *d) { assert(isContext(d)); return bits(d->d1,63,48); } 1966657Snate@binkert.orgint tucso(TxDesc *d) { assert(isContext(d)); return bits(d->d1,47,40); } 1976657Snate@binkert.orgint tucss(TxDesc *d) { assert(isContext(d)); return bits(d->d1,39,32); } 1986657Snate@binkert.orgint ipcse(TxDesc *d) { assert(isContext(d)); return bits(d->d1,31,16); } 1996657Snate@binkert.orgint ipcso(TxDesc *d) { assert(isContext(d)); return bits(d->d1,15,8); } 2006657Snate@binkert.orgint ipcss(TxDesc *d) { assert(isContext(d)); return bits(d->d1,7,0); } 2016657Snate@binkert.orgint mss(TxDesc *d) { assert(isContext(d)); return bits(d->d2,63,48); } 2026657Snate@binkert.orgint hdrlen(TxDesc *d) { assert(isContext(d)); return bits(d->d2,47,40); } 2039219Spower.jg@gmail.com} // namespace TxdOp 2046657Snate@binkert.org 2056657Snate@binkert.org 2066657Snate@binkert.org#define ADD_FIELD32(NAME, OFFSET, BITS) \ 2076657Snate@binkert.org inline uint32_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \ 2086657Snate@binkert.org inline void NAME(uint32_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); } 2096657Snate@binkert.org 2106657Snate@binkert.org#define ADD_FIELD64(NAME, OFFSET, BITS) \ 2116657Snate@binkert.org inline uint64_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \ 2126657Snate@binkert.org inline void NAME(uint64_t d) { replaceBits(_data, OFFSET+BITS-1, OFFSET,d); } 2136657Snate@binkert.org 2146657Snate@binkert.orgstruct Regs { 2156657Snate@binkert.org template<class T> 2166999Snate@binkert.org struct Reg { 2176657Snate@binkert.org T _data; 2186657Snate@binkert.org T operator()() { return _data; } 2196657Snate@binkert.org const Reg<T> &operator=(T d) { _data = d; return *this;} 2206657Snate@binkert.org bool operator==(T d) { return d == _data; } 2216657Snate@binkert.org void operator()(T d) { _data = d; } 2226657Snate@binkert.org Reg() { _data = 0; } 2236657Snate@binkert.org void serialize(std::ostream &os) 2247007Snate@binkert.org { 2257007Snate@binkert.org SERIALIZE_SCALAR(_data); 2266657Snate@binkert.org } 2277002Snate@binkert.org void unserialize(Checkpoint *cp, const std::string §ion) 2287002Snate@binkert.org { 2299466Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(_data); 2306657Snate@binkert.org } 2316657Snate@binkert.org }; 2326657Snate@binkert.org 2336657Snate@binkert.org struct CTRL : public Reg<uint32_t> { // 0x0000 CTRL Register 2346657Snate@binkert.org using Reg<uint32_t>::operator=; 2356657Snate@binkert.org ADD_FIELD32(fd,0,1); // full duplex 2366657Snate@binkert.org ADD_FIELD32(bem,1,1); // big endian mode 2376657Snate@binkert.org ADD_FIELD32(pcipr,2,1); // PCI priority 2386657Snate@binkert.org ADD_FIELD32(lrst,3,1); // link reset 2396657Snate@binkert.org ADD_FIELD32(tme,4,1); // test mode enable 2406657Snate@binkert.org ADD_FIELD32(asde,5,1); // Auto-speed detection 2416657Snate@binkert.org ADD_FIELD32(slu,6,1); // Set link up 2427007Snate@binkert.org ADD_FIELD32(ilos,7,1); // invert los-of-signal 2437007Snate@binkert.org ADD_FIELD32(speed,8,2); // speed selection bits 2446657Snate@binkert.org ADD_FIELD32(be32,10,1); // big endian mode 32 2459466Snilay@cs.wisc.edu ADD_FIELD32(frcspd,11,1); // force speed 2466657Snate@binkert.org ADD_FIELD32(frcdpx,12,1); // force duplex 2476657Snate@binkert.org ADD_FIELD32(duden,13,1); // dock/undock enable 2489466Snilay@cs.wisc.edu ADD_FIELD32(dudpol,14,1); // dock/undock polarity 2499466Snilay@cs.wisc.edu ADD_FIELD32(fphyrst,15,1); // force phy reset 2509466Snilay@cs.wisc.edu ADD_FIELD32(extlen,16,1); // external link status enable 2519466Snilay@cs.wisc.edu ADD_FIELD32(rsvd,17,1); // reserved 2529466Snilay@cs.wisc.edu ADD_FIELD32(sdp0d,18,1); // software controlled pin data 2536657Snate@binkert.org ADD_FIELD32(sdp1d,19,1); // software controlled pin data 2546657Snate@binkert.org ADD_FIELD32(sdp2d,20,1); // software controlled pin data 2556657Snate@binkert.org ADD_FIELD32(sdp3d,21,1); // software controlled pin data 2566657Snate@binkert.org ADD_FIELD32(sdp0i,22,1); // software controlled pin dir 2576657Snate@binkert.org ADD_FIELD32(sdp1i,23,1); // software controlled pin dir 2586657Snate@binkert.org ADD_FIELD32(sdp2i,24,1); // software controlled pin dir 2596657Snate@binkert.org ADD_FIELD32(sdp3i,25,1); // software controlled pin dir 2606657Snate@binkert.org ADD_FIELD32(rst,26,1); // reset 2616657Snate@binkert.org ADD_FIELD32(rfce,27,1); // receive flow control enable 2626657Snate@binkert.org ADD_FIELD32(tfce,28,1); // transmit flow control enable 2636657Snate@binkert.org ADD_FIELD32(rte,29,1); // routing tag enable 2646657Snate@binkert.org ADD_FIELD32(vme,30,1); // vlan enable 2656657Snate@binkert.org ADD_FIELD32(phyrst,31,1); // phy reset 2666657Snate@binkert.org }; 2676657Snate@binkert.org CTRL ctrl; 2686657Snate@binkert.org 2696657Snate@binkert.org struct STATUS : public Reg<uint32_t> { // 0x0008 STATUS Register 2707453Snate@binkert.org using Reg<uint32_t>::operator=; 2717453Snate@binkert.org ADD_FIELD32(fd,0,1); // full duplex 2727453Snate@binkert.org ADD_FIELD32(lu,1,1); // link up 2737453Snate@binkert.org ADD_FIELD32(func,2,2); // function id 2747453Snate@binkert.org ADD_FIELD32(txoff,4,1); // transmission paused 2757453Snate@binkert.org ADD_FIELD32(tbimode,5,1); // tbi mode 2767453Snate@binkert.org ADD_FIELD32(speed,6,2); // link speed 2777453Snate@binkert.org ADD_FIELD32(asdv,8,2); // auto speed detection value 2787453Snate@binkert.org ADD_FIELD32(mtxckok,10,1); // mtx clock running ok 2797453Snate@binkert.org ADD_FIELD32(pci66,11,1); // In 66Mhz pci slot 2807453Snate@binkert.org ADD_FIELD32(bus64,12,1); // in 64 bit slot 2817453Snate@binkert.org ADD_FIELD32(pcix,13,1); // Pci mode 2827453Snate@binkert.org ADD_FIELD32(pcixspd,14,2); // pci x speed 2837453Snate@binkert.org }; 2847453Snate@binkert.org STATUS sts; 2857453Snate@binkert.org 2867453Snate@binkert.org struct EECD : public Reg<uint32_t> { // 0x0010 EECD Register 2876657Snate@binkert.org using Reg<uint32_t>::operator=; 2886657Snate@binkert.org ADD_FIELD32(sk,0,1); // clack input to the eeprom 2896657Snate@binkert.org ADD_FIELD32(cs,1,1); // chip select to eeprom 2906657Snate@binkert.org ADD_FIELD32(din,2,1); // data input to eeprom 2919466Snilay@cs.wisc.edu ADD_FIELD32(dout,3,1); // data output bit 2926657Snate@binkert.org ADD_FIELD32(fwe,4,2); // flash write enable 2939466Snilay@cs.wisc.edu ADD_FIELD32(ee_req,6,1); // request eeprom access 2949466Snilay@cs.wisc.edu ADD_FIELD32(ee_gnt,7,1); // grant eeprom access 2959466Snilay@cs.wisc.edu ADD_FIELD32(ee_pres,8,1); // eeprom present 2966657Snate@binkert.org ADD_FIELD32(ee_size,9,1); // eeprom size 2976657Snate@binkert.org ADD_FIELD32(ee_sz1,10,1); // eeprom size 2986657Snate@binkert.org ADD_FIELD32(rsvd,11,2); // reserved 2996657Snate@binkert.org ADD_FIELD32(ee_type,13,1); // type of eeprom 3009466Snilay@cs.wisc.edu } ; 3019466Snilay@cs.wisc.edu EECD eecd; 3029466Snilay@cs.wisc.edu 3039466Snilay@cs.wisc.edu struct EERD : public Reg<uint32_t> { // 0x0014 EERD Register 3046657Snate@binkert.org using Reg<uint32_t>::operator=; 3056657Snate@binkert.org ADD_FIELD32(start,0,1); // start read 3066657Snate@binkert.org ADD_FIELD32(done,4,1); // done read 3076657Snate@binkert.org ADD_FIELD32(addr,8,8); // address 3086657Snate@binkert.org ADD_FIELD32(data,16,16); // data 3096657Snate@binkert.org }; 3106657Snate@binkert.org EERD eerd; 3116657Snate@binkert.org 3126657Snate@binkert.org struct CTRL_EXT : public Reg<uint32_t> { // 0x0018 CTRL_EXT Register 3136657Snate@binkert.org using Reg<uint32_t>::operator=; 3146657Snate@binkert.org ADD_FIELD32(gpi_en,0,4); // enable interrupts from gpio 3159466Snilay@cs.wisc.edu ADD_FIELD32(phyint,5,1); // reads the phy internal int status 3167453Snate@binkert.org ADD_FIELD32(sdp2_data,6,1); // data from gpio sdp 3177453Snate@binkert.org ADD_FIELD32(spd3_data,7,1); // data frmo gpio sdp 3187007Snate@binkert.org ADD_FIELD32(spd2_iodir,10,1); // direction of sdp2 3197007Snate@binkert.org ADD_FIELD32(spd3_iodir,11,1); // direction of sdp2 3207453Snate@binkert.org ADD_FIELD32(asdchk,12,1); // initiate auto-speed-detection 3217007Snate@binkert.org ADD_FIELD32(eerst,13,1); // reset the eeprom 3226657Snate@binkert.org ADD_FIELD32(spd_byps,15,1); // bypass speed select 3236657Snate@binkert.org ADD_FIELD32(ro_dis,17,1); // disable relaxed memory ordering 3246657Snate@binkert.org ADD_FIELD32(vreg,21,1); // power down the voltage regulator 3256657Snate@binkert.org ADD_FIELD32(link_mode,22,2); // interface to talk to the link 3266657Snate@binkert.org ADD_FIELD32(iame, 27,1); // interrupt acknowledge auto-mask ?? 3276657Snate@binkert.org ADD_FIELD32(drv_loaded, 28,1);// driver is loaded and incharge of device 3286657Snate@binkert.org ADD_FIELD32(timer_clr, 29,1); // clear interrupt timers after IMS clear ?? 3296657Snate@binkert.org }; 3306657Snate@binkert.org CTRL_EXT ctrl_ext; 3316657Snate@binkert.org 3327007Snate@binkert.org struct MDIC : public Reg<uint32_t> { // 0x0020 MDIC Register 3337007Snate@binkert.org using Reg<uint32_t>::operator=; 3347007Snate@binkert.org ADD_FIELD32(data,0,16); // data 3357007Snate@binkert.org ADD_FIELD32(regadd,16,5); // register address 3367007Snate@binkert.org ADD_FIELD32(phyadd,21,5); // phy addresses 3376657Snate@binkert.org ADD_FIELD32(op,26,2); // opcode 3386657Snate@binkert.org ADD_FIELD32(r,28,1); // ready 3396657Snate@binkert.org ADD_FIELD32(i,29,1); // interrupt 3406657Snate@binkert.org ADD_FIELD32(e,30,1); // error 3416657Snate@binkert.org }; 3426657Snate@binkert.org MDIC mdic; 3436657Snate@binkert.org 3446657Snate@binkert.org struct ICR : public Reg<uint32_t> { // 0x00C0 ICR Register 3456657Snate@binkert.org using Reg<uint32_t>::operator=; 3467007Snate@binkert.org ADD_FIELD32(txdw,0,1) // tx descr witten back 3477007Snate@binkert.org ADD_FIELD32(txqe,1,1) // tx queue empty 3487007Snate@binkert.org ADD_FIELD32(lsc,2,1) // link status change 3497007Snate@binkert.org ADD_FIELD32(rxseq,3,1) // rcv sequence error 3507007Snate@binkert.org ADD_FIELD32(rxdmt0,4,1) // rcv descriptor min thresh 3516657Snate@binkert.org ADD_FIELD32(rsvd1,5,1) // reserved 3526657Snate@binkert.org ADD_FIELD32(rxo,6,1) // receive overrunn 3536657Snate@binkert.org ADD_FIELD32(rxt0,7,1) // receiver timer interrupt 3546657Snate@binkert.org ADD_FIELD32(mdac,9,1) // mdi/o access complete 3556657Snate@binkert.org ADD_FIELD32(rxcfg,10,1) // recv /c/ ordered sets 3566657Snate@binkert.org ADD_FIELD32(phyint,12,1) // phy interrupt 3576657Snate@binkert.org ADD_FIELD32(gpi1,13,1) // gpi int 1 3587007Snate@binkert.org ADD_FIELD32(gpi2,14,1) // gpi int 2 3597007Snate@binkert.org ADD_FIELD32(txdlow,15,1) // transmit desc low thresh 3607007Snate@binkert.org ADD_FIELD32(srpd,16,1) // small receive packet detected 3617007Snate@binkert.org ADD_FIELD32(ack,17,1); // receive ack frame 3627007Snate@binkert.org ADD_FIELD32(int_assert, 31,1); // interrupt caused a system interrupt 3636657Snate@binkert.org }; 3646657Snate@binkert.org ICR icr; 3657002Snate@binkert.org 3666657Snate@binkert.org uint32_t imr; // register that contains the current interrupt mask 3676657Snate@binkert.org 3686657Snate@binkert.org struct ITR : public Reg<uint32_t> { // 0x00C4 ITR Register 3696657Snate@binkert.org using Reg<uint32_t>::operator=; 3706657Snate@binkert.org ADD_FIELD32(interval, 0,16); // minimum inter-interrutp inteval 3716657Snate@binkert.org // specified in 256ns interrupts 3726657Snate@binkert.org }; 3736657Snate@binkert.org ITR itr; 3746657Snate@binkert.org 3756657Snate@binkert.org // When CTRL_EXT.IAME and the ICR.INT_ASSERT is 1 an ICR read or write 3766657Snate@binkert.org // causes the IAM register contents to be written into the IMC 3776657Snate@binkert.org // automatically clearing all interrupts that have a bit in the IAM set 3786657Snate@binkert.org uint32_t iam; 3796657Snate@binkert.org 3806657Snate@binkert.org struct RCTL : public Reg<uint32_t> { // 0x0100 RCTL Register 3816657Snate@binkert.org using Reg<uint32_t>::operator=; 3826657Snate@binkert.org ADD_FIELD32(rst,0,1); // Reset 3836657Snate@binkert.org ADD_FIELD32(en,1,1); // Enable 3846657Snate@binkert.org ADD_FIELD32(sbp,2,1); // Store bad packets 3856657Snate@binkert.org ADD_FIELD32(upe,3,1); // Unicast Promiscuous enabled 3866657Snate@binkert.org ADD_FIELD32(mpe,4,1); // Multicast promiscuous enabled 3877007Snate@binkert.org ADD_FIELD32(lpe,5,1); // long packet reception enabled 3886657Snate@binkert.org ADD_FIELD32(lbm,6,2); // 3897007Snate@binkert.org ADD_FIELD32(rdmts,8,2); // 3906657Snate@binkert.org ADD_FIELD32(mo,12,2); // 3919298Snilay@cs.wisc.edu ADD_FIELD32(mdr,14,1); // 3929298Snilay@cs.wisc.edu ADD_FIELD32(bam,15,1); // 3939298Snilay@cs.wisc.edu ADD_FIELD32(bsize,16,2); // 3949298Snilay@cs.wisc.edu ADD_FIELD32(vfe,18,1); // 3959298Snilay@cs.wisc.edu ADD_FIELD32(cfien,19,1); // 3969298Snilay@cs.wisc.edu ADD_FIELD32(cfi,20,1); // 3976657Snate@binkert.org ADD_FIELD32(dpf,22,1); // discard pause frames 3986657Snate@binkert.org ADD_FIELD32(pmcf,23,1); // pass mac control frames 3996657Snate@binkert.org ADD_FIELD32(bsex,25,1); // buffer size extension 4006657Snate@binkert.org ADD_FIELD32(secrc,26,1); // strip ethernet crc from incoming packet 4017055Snate@binkert.org int descSize() 4027007Snate@binkert.org { 4036657Snate@binkert.org switch(bsize()) { 4046657Snate@binkert.org case 0: return bsex() == 0 ? 2048 : -1; 4057002Snate@binkert.org case 1: return bsex() == 0 ? 1024 : 16384; 4066657Snate@binkert.org case 2: return bsex() == 0 ? 512 : 8192; 4076657Snate@binkert.org case 3: return bsex() == 0 ? 256 : 4096; 4086657Snate@binkert.org default: 4097007Snate@binkert.org return -1; 4106657Snate@binkert.org } 4116657Snate@binkert.org } 4126657Snate@binkert.org }; 4136657Snate@binkert.org RCTL rctl; 4146657Snate@binkert.org 4156999Snate@binkert.org struct FCTTV : public Reg<uint32_t> { // 0x0170 FCTTV 4166657Snate@binkert.org using Reg<uint32_t>::operator=; 4176657Snate@binkert.org ADD_FIELD32(ttv,0,16); // Transmit Timer Value 4186657Snate@binkert.org }; 4196657Snate@binkert.org FCTTV fcttv; 4206657Snate@binkert.org 4216657Snate@binkert.org struct TCTL : public Reg<uint32_t> { // 0x0400 TCTL Register 4226657Snate@binkert.org using Reg<uint32_t>::operator=; 4237002Snate@binkert.org ADD_FIELD32(rst,0,1); // Reset 4247002Snate@binkert.org ADD_FIELD32(en,1,1); // Enable 4256657Snate@binkert.org ADD_FIELD32(bce,2,1); // busy check enable 4269499Snilay@cs.wisc.edu ADD_FIELD32(psp,3,1); // pad short packets 4279499Snilay@cs.wisc.edu ADD_FIELD32(ct,4,8); // collision threshold 4287002Snate@binkert.org ADD_FIELD32(cold,12,10); // collision distance 4297002Snate@binkert.org ADD_FIELD32(swxoff,22,1); // software xoff transmission 4306657Snate@binkert.org ADD_FIELD32(pbe,23,1); // packet burst enable 4316657Snate@binkert.org ADD_FIELD32(rtlc,24,1); // retransmit late collisions 4326657Snate@binkert.org ADD_FIELD32(nrtu,25,1); // on underrun no TX 4336657Snate@binkert.org ADD_FIELD32(mulr,26,1); // multiple request 4347007Snate@binkert.org }; 4357007Snate@binkert.org TCTL tctl; 4366657Snate@binkert.org 4376657Snate@binkert.org struct PBA : public Reg<uint32_t> { // 0x1000 PBA Register 4386657Snate@binkert.org using Reg<uint32_t>::operator=; 4396657Snate@binkert.org ADD_FIELD32(rxa,0,16); 4406657Snate@binkert.org ADD_FIELD32(txa,16,16); 4416657Snate@binkert.org }; 4426657Snate@binkert.org PBA pba; 4436657Snate@binkert.org 4446657Snate@binkert.org struct FCRTL : public Reg<uint32_t> { // 0x2160 FCRTL Register 4456657Snate@binkert.org using Reg<uint32_t>::operator=; 4469206Snilay@cs.wisc.edu ADD_FIELD32(rtl,3,28); // make this bigger than the spec so we can have 4476657Snate@binkert.org // a larger buffer 4486657Snate@binkert.org ADD_FIELD32(xone, 31,1); 4496657Snate@binkert.org }; 4506657Snate@binkert.org FCRTL fcrtl; 4516657Snate@binkert.org 4526657Snate@binkert.org struct FCRTH : public Reg<uint32_t> { // 0x2168 FCRTL Register 4536657Snate@binkert.org using Reg<uint32_t>::operator=; 4549298Snilay@cs.wisc.edu ADD_FIELD32(rth,3,13); // make this bigger than the spec so we can have 4559298Snilay@cs.wisc.edu //a larger buffer 4569298Snilay@cs.wisc.edu ADD_FIELD32(xfce, 31,1); 4579298Snilay@cs.wisc.edu }; 4586657Snate@binkert.org FCRTH fcrth; 4596657Snate@binkert.org 4606657Snate@binkert.org struct RDBA : public Reg<uint64_t> { // 0x2800 RDBA Register 4616999Snate@binkert.org using Reg<uint64_t>::operator=; 4626657Snate@binkert.org ADD_FIELD64(rdbal,0,32); // base address of rx descriptor ring 4636657Snate@binkert.org ADD_FIELD64(rdbah,32,32); // base address of rx descriptor ring 4646657Snate@binkert.org }; 4656657Snate@binkert.org RDBA rdba; 4666657Snate@binkert.org 4677007Snate@binkert.org struct RDLEN : public Reg<uint32_t> { // 0x2808 RDLEN Register 4687007Snate@binkert.org using Reg<uint32_t>::operator=; 4697007Snate@binkert.org ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer 4706657Snate@binkert.org }; 4717002Snate@binkert.org RDLEN rdlen; 4727002Snate@binkert.org 4737002Snate@binkert.org struct RDH : public Reg<uint32_t> { // 0x2810 RDH Register 4748086SBrad.Beckmann@amd.com using Reg<uint32_t>::operator=; 4758086SBrad.Beckmann@amd.com ADD_FIELD32(rdh,0,16); // head of the descriptor ring 4768086SBrad.Beckmann@amd.com }; 4778086SBrad.Beckmann@amd.com RDH rdh; 4788602Snilay@cs.wisc.edu 4798602Snilay@cs.wisc.edu struct RDT : public Reg<uint32_t> { // 0x2818 RDT Register 4808602Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 4818602Snilay@cs.wisc.edu ADD_FIELD32(rdt,0,16); // tail of the descriptor ring 4828602Snilay@cs.wisc.edu }; 4838602Snilay@cs.wisc.edu RDT rdt; 4848086SBrad.Beckmann@amd.com 4856657Snate@binkert.org struct RDTR : public Reg<uint32_t> { // 0x2820 RDTR Register 4867007Snate@binkert.org using Reg<uint32_t>::operator=; 4876657Snate@binkert.org ADD_FIELD32(delay,0,16); // receive delay timer 4886657Snate@binkert.org ADD_FIELD32(fpd, 31,1); // flush partial descriptor block ?? 4896657Snate@binkert.org }; 4906657Snate@binkert.org RDTR rdtr; 4916657Snate@binkert.org 4926657Snate@binkert.org struct RXDCTL : public Reg<uint32_t> { // 0x2828 RXDCTL Register 4936657Snate@binkert.org using Reg<uint32_t>::operator=; 4946657Snate@binkert.org ADD_FIELD32(pthresh,0,6); // prefetch threshold, less that this 4956657Snate@binkert.org // consider prefetch 4966657Snate@binkert.org ADD_FIELD32(hthresh,8,6); // number of descriptors in host mem to 4976657Snate@binkert.org // consider prefetch 4986862Sdrh5@cs.wisc.edu ADD_FIELD32(wthresh,16,6); // writeback threshold 4996862Sdrh5@cs.wisc.edu ADD_FIELD32(gran,24,1); // granularity 0 = desc, 1 = cacheline 5006862Sdrh5@cs.wisc.edu }; 5016862Sdrh5@cs.wisc.edu RXDCTL rxdctl; 5026657Snate@binkert.org 5036657Snate@binkert.org struct RADV : public Reg<uint32_t> { // 0x282C RADV Register 5046657Snate@binkert.org using Reg<uint32_t>::operator=; 5056657Snate@binkert.org ADD_FIELD32(idv,0,16); // absolute interrupt delay 5066657Snate@binkert.org }; 5077007Snate@binkert.org RADV radv; 5087007Snate@binkert.org 5097002Snate@binkert.org struct RSRPD : public Reg<uint32_t> { // 0x2C00 RSRPD Register 5107007Snate@binkert.org using Reg<uint32_t>::operator=; 5117007Snate@binkert.org ADD_FIELD32(idv,0,12); // size to interrutp on small packets 5127002Snate@binkert.org }; 5137007Snate@binkert.org RSRPD rsrpd; 5147007Snate@binkert.org 5156657Snate@binkert.org struct TDBA : public Reg<uint64_t> { // 0x3800 TDBAL Register 5166657Snate@binkert.org using Reg<uint64_t>::operator=; 5176657Snate@binkert.org ADD_FIELD64(tdbal,0,32); // base address of transmit descriptor ring 5186657Snate@binkert.org ADD_FIELD64(tdbah,32,32); // base address of transmit descriptor ring 5196657Snate@binkert.org }; 5206657Snate@binkert.org TDBA tdba; 5216657Snate@binkert.org 5226657Snate@binkert.org struct TDLEN : public Reg<uint32_t> { // 0x3808 TDLEN Register 5236657Snate@binkert.org using Reg<uint32_t>::operator=; 5246657Snate@binkert.org ADD_FIELD32(len,7,13); // number of bytes in the descriptor buffer 5256657Snate@binkert.org }; 5266657Snate@binkert.org TDLEN tdlen; 5276657Snate@binkert.org 5288602Snilay@cs.wisc.edu struct TDH : public Reg<uint32_t> { // 0x3810 TDH Register 5298602Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 5308602Snilay@cs.wisc.edu ADD_FIELD32(tdh,0,16); // head of the descriptor ring 5318602Snilay@cs.wisc.edu }; 5328602Snilay@cs.wisc.edu TDH tdh; 5338602Snilay@cs.wisc.edu 5348602Snilay@cs.wisc.edu struct TDT : public Reg<uint32_t> { // 0x3818 TDT Register 5358602Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 5368602Snilay@cs.wisc.edu ADD_FIELD32(tdt,0,16); // tail of the descriptor ring 5378602Snilay@cs.wisc.edu }; 5388602Snilay@cs.wisc.edu TDT tdt; 5398602Snilay@cs.wisc.edu 5408602Snilay@cs.wisc.edu struct TIDV : public Reg<uint32_t> { // 0x3820 TIDV Register 5418602Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 5428602Snilay@cs.wisc.edu ADD_FIELD32(idv,0,16); // interrupt delay 5438602Snilay@cs.wisc.edu }; 5448602Snilay@cs.wisc.edu TIDV tidv; 5458602Snilay@cs.wisc.edu 5468602Snilay@cs.wisc.edu struct TXDCTL : public Reg<uint32_t> { // 0x3828 TXDCTL Register 5478602Snilay@cs.wisc.edu using Reg<uint32_t>::operator=; 5488602Snilay@cs.wisc.edu ADD_FIELD32(pthresh, 0,6); // if number of descriptors control has is 5498602Snilay@cs.wisc.edu // below this number, a prefetch is considered 5508602Snilay@cs.wisc.edu ADD_FIELD32(hthresh,8,8); // number of valid descriptors is host memory 5516657Snate@binkert.org // before a prefetch is considered 5528086SBrad.Beckmann@amd.com ADD_FIELD32(wthresh,16,6); // number of descriptors to keep until 5538086SBrad.Beckmann@amd.com // writeback is considered 5548086SBrad.Beckmann@amd.com ADD_FIELD32(gran, 24,1); // granulatiry of above values (0 = cacheline, 5558086SBrad.Beckmann@amd.com // 1 == desscriptor) 5568086SBrad.Beckmann@amd.com ADD_FIELD32(lwthresh,25,7); // xmit descriptor low thresh, interrupt 5578086SBrad.Beckmann@amd.com // below this level 5588086SBrad.Beckmann@amd.com }; 5598086SBrad.Beckmann@amd.com TXDCTL txdctl; 5606657Snate@binkert.org 5616657Snate@binkert.org struct TADV : public Reg<uint32_t> { // 0x382C TADV Register 5627002Snate@binkert.org using Reg<uint32_t>::operator=; 5636657Snate@binkert.org ADD_FIELD32(idv,0,16); // absolute interrupt delay 5647007Snate@binkert.org }; 5656657Snate@binkert.org TADV tadv; 5666657Snate@binkert.org 5676657Snate@binkert.org struct RXCSUM : public Reg<uint32_t> { // 0x5000 RXCSUM Register 5686657Snate@binkert.org using Reg<uint32_t>::operator=; 5696657Snate@binkert.org ADD_FIELD32(pcss,0,8); 5706999Snate@binkert.org ADD_FIELD32(ipofld,8,1); 5716657Snate@binkert.org ADD_FIELD32(tuofld,9,1); 5726657Snate@binkert.org }; 5736657Snate@binkert.org RXCSUM rxcsum; 5746657Snate@binkert.org 5756657Snate@binkert.org struct MANC : public Reg<uint32_t> { // 0x5820 MANC Register 5766657Snate@binkert.org using Reg<uint32_t>::operator=; 5777832Snate@binkert.org ADD_FIELD32(smbus,0,1); // SMBus enabled ##### 5787002Snate@binkert.org ADD_FIELD32(asf,1,1); // ASF enabled ##### 5797002Snate@binkert.org ADD_FIELD32(ronforce,2,1); // reset of force 5807002Snate@binkert.org ADD_FIELD32(rsvd,3,5); // reserved 5817805Snilay@cs.wisc.edu ADD_FIELD32(rmcp1,8,1); // rcmp1 filtering 5826657Snate@binkert.org ADD_FIELD32(rmcp2,9,1); // rcmp2 filtering 5836657Snate@binkert.org ADD_FIELD32(ipv4,10,1); // enable ipv4 5847002Snate@binkert.org ADD_FIELD32(ipv6,11,1); // enable ipv6 5857002Snate@binkert.org ADD_FIELD32(snap,12,1); // accept snap 5866657Snate@binkert.org ADD_FIELD32(arp,13,1); // filter arp ##### 5876657Snate@binkert.org ADD_FIELD32(neighbor,14,1); // neighbor discovery 5888086SBrad.Beckmann@amd.com ADD_FIELD32(arp_resp,15,1); // arp response 5898086SBrad.Beckmann@amd.com ADD_FIELD32(tcorst,16,1); // tco reset happened 5908086SBrad.Beckmann@amd.com ADD_FIELD32(rcvtco,17,1); // receive tco enabled ###### 5918086SBrad.Beckmann@amd.com ADD_FIELD32(blkphyrst,18,1);// block phy resets ######## 5928086SBrad.Beckmann@amd.com ADD_FIELD32(rcvall,19,1); // receive all 5938086SBrad.Beckmann@amd.com ADD_FIELD32(macaddrfltr,20,1); // mac address filtering ###### 5948086SBrad.Beckmann@amd.com ADD_FIELD32(mng2host,21,1); // mng2 host packets ####### 5958086SBrad.Beckmann@amd.com ADD_FIELD32(ipaddrfltr,22,1); // ip address filtering 5968086SBrad.Beckmann@amd.com ADD_FIELD32(xsumfilter,23,1); // checksum filtering 5978086SBrad.Beckmann@amd.com ADD_FIELD32(brfilter,24,1); // broadcast filtering 5988086SBrad.Beckmann@amd.com ADD_FIELD32(smbreq,25,1); // smb request 5998086SBrad.Beckmann@amd.com ADD_FIELD32(smbgnt,26,1); // smb grant 6008086SBrad.Beckmann@amd.com ADD_FIELD32(smbclkin,27,1); // smbclkin 6018086SBrad.Beckmann@amd.com ADD_FIELD32(smbdatain,28,1); // smbdatain 6028086SBrad.Beckmann@amd.com ADD_FIELD32(smbdataout,29,1); // smb data out 6038086SBrad.Beckmann@amd.com ADD_FIELD32(smbclkout,30,1); // smb clock out 6048086SBrad.Beckmann@amd.com }; 6058086SBrad.Beckmann@amd.com MANC manc; 6068086SBrad.Beckmann@amd.com 6078086SBrad.Beckmann@amd.com void serialize(std::ostream &os) 6088086SBrad.Beckmann@amd.com { 6096657Snate@binkert.org paramOut(os, "ctrl", ctrl._data); 6106657Snate@binkert.org paramOut(os, "sts", sts._data); 6116657Snate@binkert.org paramOut(os, "eecd", eecd._data); 6128602Snilay@cs.wisc.edu paramOut(os, "eerd", eerd._data); 6136657Snate@binkert.org paramOut(os, "ctrl_ext", ctrl_ext._data); 6146657Snate@binkert.org paramOut(os, "mdic", mdic._data); 6157007Snate@binkert.org paramOut(os, "icr", icr._data); 6167007Snate@binkert.org SERIALIZE_SCALAR(imr); 6177007Snate@binkert.org paramOut(os, "itr", itr._data); 6186657Snate@binkert.org SERIALIZE_SCALAR(iam); 6196657Snate@binkert.org paramOut(os, "rctl", rctl._data); 6206657Snate@binkert.org paramOut(os, "fcttv", fcttv._data); 6216657Snate@binkert.org paramOut(os, "tctl", tctl._data); 6226657Snate@binkert.org paramOut(os, "pba", pba._data); 6236657Snate@binkert.org paramOut(os, "fcrtl", fcrtl._data); 6247007Snate@binkert.org paramOut(os, "fcrth", fcrth._data); 6257007Snate@binkert.org paramOut(os, "rdba", rdba._data); 6267007Snate@binkert.org paramOut(os, "rdlen", rdlen._data); 6276657Snate@binkert.org paramOut(os, "rdh", rdh._data); 6286657Snate@binkert.org paramOut(os, "rdt", rdt._data); 6296657Snate@binkert.org paramOut(os, "rdtr", rdtr._data); 6306657Snate@binkert.org paramOut(os, "rxdctl", rxdctl._data); 6316657Snate@binkert.org paramOut(os, "radv", radv._data); 6326657Snate@binkert.org paramOut(os, "rsrpd", rsrpd._data); 6336657Snate@binkert.org paramOut(os, "tdba", tdba._data); 6346657Snate@binkert.org paramOut(os, "tdlen", tdlen._data); 6356657Snate@binkert.org paramOut(os, "tdh", tdh._data); 6366657Snate@binkert.org paramOut(os, "tdt", tdt._data); 6376657Snate@binkert.org paramOut(os, "tidv", tidv._data); 6386657Snate@binkert.org paramOut(os, "txdctl", txdctl._data); 6396657Snate@binkert.org paramOut(os, "tadv", tadv._data); 6406657Snate@binkert.org paramOut(os, "rxcsum", rxcsum._data); 6417805Snilay@cs.wisc.edu paramOut(os, "manc", manc._data); 6426657Snate@binkert.org } 6436657Snate@binkert.org 6446657Snate@binkert.org void unserialize(Checkpoint *cp, const std::string §ion) 6457007Snate@binkert.org { 6467007Snate@binkert.org paramIn(cp, section, "ctrl", ctrl._data); 6477007Snate@binkert.org paramIn(cp, section, "sts", sts._data); 6486657Snate@binkert.org paramIn(cp, section, "eecd", eecd._data); 6496657Snate@binkert.org paramIn(cp, section, "eerd", eerd._data); 6506657Snate@binkert.org paramIn(cp, section, "ctrl_ext", ctrl_ext._data); 6516657Snate@binkert.org paramIn(cp, section, "mdic", mdic._data); 6527007Snate@binkert.org paramIn(cp, section, "icr", icr._data); 6536657Snate@binkert.org UNSERIALIZE_SCALAR(imr); 6546657Snate@binkert.org paramIn(cp, section, "itr", itr._data); 6556657Snate@binkert.org UNSERIALIZE_SCALAR(iam); 6566657Snate@binkert.org paramIn(cp, section, "rctl", rctl._data); 6577007Snate@binkert.org paramIn(cp, section, "fcttv", fcttv._data); 6586657Snate@binkert.org paramIn(cp, section, "tctl", tctl._data); 6596657Snate@binkert.org paramIn(cp, section, "pba", pba._data); 6606657Snate@binkert.org paramIn(cp, section, "fcrtl", fcrtl._data); 6616657Snate@binkert.org paramIn(cp, section, "fcrth", fcrth._data); 6627805Snilay@cs.wisc.edu paramIn(cp, section, "rdba", rdba._data); 6636657Snate@binkert.org paramIn(cp, section, "rdlen", rdlen._data); 6646657Snate@binkert.org paramIn(cp, section, "rdh", rdh._data); 6656657Snate@binkert.org paramIn(cp, section, "rdt", rdt._data); 6667007Snate@binkert.org paramIn(cp, section, "rdtr", rdtr._data); 6677007Snate@binkert.org paramIn(cp, section, "rxdctl", rxdctl._data); 6687007Snate@binkert.org paramIn(cp, section, "radv", radv._data); 6697007Snate@binkert.org paramIn(cp, section, "rsrpd", rsrpd._data); 6706657Snate@binkert.org paramIn(cp, section, "tdba", tdba._data); 6716657Snate@binkert.org paramIn(cp, section, "tdlen", tdlen._data); 6726657Snate@binkert.org paramIn(cp, section, "tdh", tdh._data); 6736657Snate@binkert.org paramIn(cp, section, "tdt", tdt._data); 6746657Snate@binkert.org paramIn(cp, section, "tidv", tidv._data); 6756657Snate@binkert.org paramIn(cp, section, "txdctl", txdctl._data); 6766657Snate@binkert.org paramIn(cp, section, "tadv", tadv._data); 6776657Snate@binkert.org paramIn(cp, section, "rxcsum", rxcsum._data); 6786657Snate@binkert.org paramIn(cp, section, "manc", manc._data); 6797007Snate@binkert.org } 6807007Snate@binkert.org}; 6816657Snate@binkert.org} // iGbReg namespace 6826657Snate@binkert.org