kmi.cc revision 13230
17754SWilliam.Wang@arm.com/* 212659Sandreas.sandberg@arm.com * Copyright (c) 2010, 2017-2018 ARM Limited 37754SWilliam.Wang@arm.com * All rights reserved 47754SWilliam.Wang@arm.com * 57754SWilliam.Wang@arm.com * The license below extends only to copyright in the software and shall 67754SWilliam.Wang@arm.com * not be construed as granting a license to any other intellectual 77754SWilliam.Wang@arm.com * property including but not limited to intellectual property relating 87754SWilliam.Wang@arm.com * to a hardware implementation of the functionality of the software 97754SWilliam.Wang@arm.com * licensed hereunder. You may use the software subject to the license 107754SWilliam.Wang@arm.com * terms below provided that you ensure that this notice is replicated 117754SWilliam.Wang@arm.com * unmodified and in its entirety in all distributions of the software, 127754SWilliam.Wang@arm.com * modified or unmodified, in source code or in binary form. 137754SWilliam.Wang@arm.com * 147754SWilliam.Wang@arm.com * Copyright (c) 2005 The Regents of The University of Michigan 157754SWilliam.Wang@arm.com * All rights reserved. 167754SWilliam.Wang@arm.com * 177754SWilliam.Wang@arm.com * Redistribution and use in source and binary forms, with or without 187754SWilliam.Wang@arm.com * modification, are permitted provided that the following conditions are 197754SWilliam.Wang@arm.com * met: redistributions of source code must retain the above copyright 207754SWilliam.Wang@arm.com * notice, this list of conditions and the following disclaimer; 217754SWilliam.Wang@arm.com * redistributions in binary form must reproduce the above copyright 227754SWilliam.Wang@arm.com * notice, this list of conditions and the following disclaimer in the 237754SWilliam.Wang@arm.com * documentation and/or other materials provided with the distribution; 247754SWilliam.Wang@arm.com * neither the name of the copyright holders nor the names of its 257754SWilliam.Wang@arm.com * contributors may be used to endorse or promote products derived from 267754SWilliam.Wang@arm.com * this software without specific prior written permission. 277754SWilliam.Wang@arm.com * 287754SWilliam.Wang@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 297754SWilliam.Wang@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 307754SWilliam.Wang@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 317754SWilliam.Wang@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 327754SWilliam.Wang@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 337754SWilliam.Wang@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 347754SWilliam.Wang@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 357754SWilliam.Wang@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 367754SWilliam.Wang@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 377754SWilliam.Wang@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 387754SWilliam.Wang@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 397754SWilliam.Wang@arm.com * 407950SAli.Saidi@ARM.com * Authors: Ali Saidi 417950SAli.Saidi@ARM.com * William Wang 427754SWilliam.Wang@arm.com */ 437754SWilliam.Wang@arm.com 4411793Sbrandon.potter@amd.com#include "dev/arm/kmi.hh" 4511793Sbrandon.potter@amd.com 4611793Sbrandon.potter@amd.com#include "base/trace.hh" 479330Schander.sudanthi@arm.com#include "base/vnc/vncinput.hh" 488245Snate@binkert.org#include "debug/Pl050.hh" 497754SWilliam.Wang@arm.com#include "dev/arm/amba_device.hh" 5012659Sandreas.sandberg@arm.com#include "dev/ps2/device.hh" 517754SWilliam.Wang@arm.com#include "mem/packet.hh" 527754SWilliam.Wang@arm.com#include "mem/packet_access.hh" 537754SWilliam.Wang@arm.com 5412659Sandreas.sandberg@arm.comPl050::Pl050(const Pl050Params *p) 5512772Snikos.nikoleris@arm.com : AmbaIntDevice(p, 0x1000), control(0), status(0x43), clkdiv(0), 5612659Sandreas.sandberg@arm.com rawInterrupts(0), 5712659Sandreas.sandberg@arm.com ps2(p->ps2) 587754SWilliam.Wang@arm.com{ 5912664Sandreas.sandberg@arm.com ps2->hostRegDataAvailable([this]() { this->updateRxInt(); }); 607754SWilliam.Wang@arm.com} 617754SWilliam.Wang@arm.com 627754SWilliam.Wang@arm.comTick 637754SWilliam.Wang@arm.comPl050::read(PacketPtr pkt) 647754SWilliam.Wang@arm.com{ 657754SWilliam.Wang@arm.com assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 667754SWilliam.Wang@arm.com 677754SWilliam.Wang@arm.com Addr daddr = pkt->getAddr() - pioAddr; 687754SWilliam.Wang@arm.com 697754SWilliam.Wang@arm.com uint32_t data = 0; 707754SWilliam.Wang@arm.com 717754SWilliam.Wang@arm.com switch (daddr) { 727754SWilliam.Wang@arm.com case kmiCr: 737950SAli.Saidi@ARM.com DPRINTF(Pl050, "Read Commmand: %#x\n", (uint32_t)control); 747754SWilliam.Wang@arm.com data = control; 757754SWilliam.Wang@arm.com break; 7612659Sandreas.sandberg@arm.com 777754SWilliam.Wang@arm.com case kmiStat: 7812659Sandreas.sandberg@arm.com status.rxfull = ps2->hostDataAvailable() ? 1 : 0; 797950SAli.Saidi@ARM.com DPRINTF(Pl050, "Read Status: %#x\n", (uint32_t)status); 807754SWilliam.Wang@arm.com data = status; 817754SWilliam.Wang@arm.com break; 8212659Sandreas.sandberg@arm.com 837754SWilliam.Wang@arm.com case kmiData: 8412659Sandreas.sandberg@arm.com data = ps2->hostDataAvailable() ? ps2->hostRead() : 0; 8512664Sandreas.sandberg@arm.com updateRxInt(); 867950SAli.Saidi@ARM.com DPRINTF(Pl050, "Read Data: %#x\n", (uint32_t)data); 877754SWilliam.Wang@arm.com break; 8812659Sandreas.sandberg@arm.com 897754SWilliam.Wang@arm.com case kmiClkDiv: 907754SWilliam.Wang@arm.com data = clkdiv; 917754SWilliam.Wang@arm.com break; 9212659Sandreas.sandberg@arm.com 937754SWilliam.Wang@arm.com case kmiISR: 9411895Ssudhanshu.jha@arm.com data = getInterrupt(); 9511895Ssudhanshu.jha@arm.com DPRINTF(Pl050, "Read Interrupts: %#x\n", getInterrupt()); 967754SWilliam.Wang@arm.com break; 9712659Sandreas.sandberg@arm.com 987754SWilliam.Wang@arm.com default: 999806Sstever@gmail.com if (readId(pkt, ambaId, pioAddr)) { 1007754SWilliam.Wang@arm.com // Hack for variable size accesses 10113230Sgabeblack@google.com data = pkt->getLE<uint32_t>(); 1027754SWilliam.Wang@arm.com break; 1037754SWilliam.Wang@arm.com } 1047754SWilliam.Wang@arm.com 1057754SWilliam.Wang@arm.com warn("Tried to read PL050 at offset %#x that doesn't exist\n", daddr); 1067754SWilliam.Wang@arm.com break; 1077754SWilliam.Wang@arm.com } 1087754SWilliam.Wang@arm.com 10912664Sandreas.sandberg@arm.com pkt->setUintX(data, LittleEndianByteOrder); 1107754SWilliam.Wang@arm.com pkt->makeAtomicResponse(); 1117754SWilliam.Wang@arm.com return pioDelay; 1127754SWilliam.Wang@arm.com} 1137754SWilliam.Wang@arm.com 1147754SWilliam.Wang@arm.comTick 1157754SWilliam.Wang@arm.comPl050::write(PacketPtr pkt) 1167754SWilliam.Wang@arm.com{ 1177754SWilliam.Wang@arm.com 1187754SWilliam.Wang@arm.com assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 1197754SWilliam.Wang@arm.com 1207754SWilliam.Wang@arm.com Addr daddr = pkt->getAddr() - pioAddr; 12112664Sandreas.sandberg@arm.com const uint32_t data = pkt->getUintX(LittleEndianByteOrder); 1227754SWilliam.Wang@arm.com 12312664Sandreas.sandberg@arm.com panic_if(pkt->getSize() != 1, 12412664Sandreas.sandberg@arm.com "PL050: Unexpected write size " 12512664Sandreas.sandberg@arm.com "(offset: %#x, data: %#x, size: %u)\n", 12612664Sandreas.sandberg@arm.com daddr, data, pkt->getSize()); 1277754SWilliam.Wang@arm.com 1287754SWilliam.Wang@arm.com switch (daddr) { 1297754SWilliam.Wang@arm.com case kmiCr: 13012664Sandreas.sandberg@arm.com DPRINTF(Pl050, "Write Commmand: %#x\n", data); 13112664Sandreas.sandberg@arm.com // Use the update interrupts helper to make sure any interrupt 13212664Sandreas.sandberg@arm.com // mask changes are handled correctly. 13312664Sandreas.sandberg@arm.com setControl((uint8_t)data); 1347754SWilliam.Wang@arm.com break; 13512659Sandreas.sandberg@arm.com 1367754SWilliam.Wang@arm.com case kmiData: 13712664Sandreas.sandberg@arm.com DPRINTF(Pl050, "Write Data: %#x\n", data); 13812664Sandreas.sandberg@arm.com // Clear the TX interrupt before writing new data. 13912664Sandreas.sandberg@arm.com setTxInt(false); 14012664Sandreas.sandberg@arm.com ps2->hostWrite((uint8_t)data); 14112664Sandreas.sandberg@arm.com // Data is written in 0 time, so raise the TX interrupt again. 14212664Sandreas.sandberg@arm.com setTxInt(true); 1437754SWilliam.Wang@arm.com break; 14412659Sandreas.sandberg@arm.com 1457754SWilliam.Wang@arm.com case kmiClkDiv: 14612664Sandreas.sandberg@arm.com clkdiv = (uint8_t)data; 1477754SWilliam.Wang@arm.com break; 14812659Sandreas.sandberg@arm.com 1497754SWilliam.Wang@arm.com default: 15012664Sandreas.sandberg@arm.com warn("PL050: Unhandled write of %#x to offset %#x\n", data, daddr); 1517754SWilliam.Wang@arm.com break; 1527754SWilliam.Wang@arm.com } 15312659Sandreas.sandberg@arm.com 1547754SWilliam.Wang@arm.com pkt->makeAtomicResponse(); 1557754SWilliam.Wang@arm.com return pioDelay; 1567754SWilliam.Wang@arm.com} 1577754SWilliam.Wang@arm.com 15812664Sandreas.sandberg@arm.comvoid 15912664Sandreas.sandberg@arm.comPl050::setTxInt(bool value) 16012664Sandreas.sandberg@arm.com{ 16112664Sandreas.sandberg@arm.com InterruptReg ints = rawInterrupts; 16212664Sandreas.sandberg@arm.com 16312664Sandreas.sandberg@arm.com ints.tx = value ? 1 : 0; 16412664Sandreas.sandberg@arm.com 16512664Sandreas.sandberg@arm.com setInterrupts(ints); 16612664Sandreas.sandberg@arm.com} 1677950SAli.Saidi@ARM.com 1687950SAli.Saidi@ARM.comvoid 16912664Sandreas.sandberg@arm.comPl050::updateRxInt() 1707950SAli.Saidi@ARM.com{ 17112664Sandreas.sandberg@arm.com InterruptReg ints = rawInterrupts; 17211895Ssudhanshu.jha@arm.com 17312664Sandreas.sandberg@arm.com ints.rx = ps2->hostDataAvailable() ? 1 : 0; 1747950SAli.Saidi@ARM.com 17512664Sandreas.sandberg@arm.com setInterrupts(ints); 17612664Sandreas.sandberg@arm.com} 17712664Sandreas.sandberg@arm.com 17812664Sandreas.sandberg@arm.comvoid 17912664Sandreas.sandberg@arm.comPl050::updateIntCtrl(InterruptReg ints, ControlReg ctrl) 18012664Sandreas.sandberg@arm.com{ 18112664Sandreas.sandberg@arm.com const bool old_pending(getInterrupt()); 18212664Sandreas.sandberg@arm.com control = ctrl; 18312664Sandreas.sandberg@arm.com rawInterrupts = ints; 18412664Sandreas.sandberg@arm.com const bool new_pending(getInterrupt()); 18512664Sandreas.sandberg@arm.com 18612664Sandreas.sandberg@arm.com if (!old_pending && new_pending) { 18712664Sandreas.sandberg@arm.com DPRINTF(Pl050, "Generate interrupt: rawInt=%#x ctrl=%#x int=%#x\n", 18812664Sandreas.sandberg@arm.com rawInterrupts, control, getInterrupt()); 18912664Sandreas.sandberg@arm.com gic->sendInt(intNum); 19012664Sandreas.sandberg@arm.com } else if (old_pending && !new_pending) { 19112664Sandreas.sandberg@arm.com DPRINTF(Pl050, "Clear interrupt: rawInt=%#x ctrl=%#x int=%#x\n", 19212664Sandreas.sandberg@arm.com rawInterrupts, control, getInterrupt()); 19312664Sandreas.sandberg@arm.com gic->clearInt(intNum); 19411895Ssudhanshu.jha@arm.com } 1957950SAli.Saidi@ARM.com} 1967950SAli.Saidi@ARM.com 19712659Sandreas.sandberg@arm.comPl050::InterruptReg 19812659Sandreas.sandberg@arm.comPl050::getInterrupt() const 19912659Sandreas.sandberg@arm.com{ 20012659Sandreas.sandberg@arm.com InterruptReg tmp_interrupt(0); 20112659Sandreas.sandberg@arm.com 20212659Sandreas.sandberg@arm.com tmp_interrupt.tx = rawInterrupts.tx & control.txint_enable; 20312659Sandreas.sandberg@arm.com tmp_interrupt.rx = rawInterrupts.rx & control.rxint_enable; 20412659Sandreas.sandberg@arm.com 20512659Sandreas.sandberg@arm.com return tmp_interrupt; 20612659Sandreas.sandberg@arm.com} 20712659Sandreas.sandberg@arm.com 2087950SAli.Saidi@ARM.comvoid 20910905Sandreas.sandberg@arm.comPl050::serialize(CheckpointOut &cp) const 2107950SAli.Saidi@ARM.com{ 21112664Sandreas.sandberg@arm.com paramOut(cp, "ctrlreg", control); 21212664Sandreas.sandberg@arm.com paramOut(cp, "stsreg", status); 2137950SAli.Saidi@ARM.com SERIALIZE_SCALAR(clkdiv); 21412664Sandreas.sandberg@arm.com paramOut(cp, "raw_ints", rawInterrupts); 2157950SAli.Saidi@ARM.com} 2167950SAli.Saidi@ARM.com 2177950SAli.Saidi@ARM.comvoid 21810905Sandreas.sandberg@arm.comPl050::unserialize(CheckpointIn &cp) 2197950SAli.Saidi@ARM.com{ 22012664Sandreas.sandberg@arm.com paramIn(cp, "ctrlreg", control); 22112664Sandreas.sandberg@arm.com paramIn(cp, "stsreg", status); 2227950SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(clkdiv); 22312664Sandreas.sandberg@arm.com paramIn(cp, "raw_ints", rawInterrupts); 2247950SAli.Saidi@ARM.com} 2257950SAli.Saidi@ARM.com 2267754SWilliam.Wang@arm.comPl050 * 2277754SWilliam.Wang@arm.comPl050Params::create() 2287754SWilliam.Wang@arm.com{ 2297754SWilliam.Wang@arm.com return new Pl050(this); 2307754SWilliam.Wang@arm.com} 231