1/*
2 * Copyright (c) 2010, 2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 *          William Wang
42 */
43
44#include "dev/arm/kmi.hh"
45
46#include "base/trace.hh"
47#include "base/vnc/vncinput.hh"
48#include "debug/Pl050.hh"
49#include "dev/arm/amba_device.hh"
50#include "dev/ps2/device.hh"
51#include "mem/packet.hh"
52#include "mem/packet_access.hh"
53
54Pl050::Pl050(const Pl050Params *p)
55    : AmbaIntDevice(p, 0x1000), control(0), status(0x43), clkdiv(0),
56      rawInterrupts(0),
57      ps2(p->ps2)
58{
59    ps2->hostRegDataAvailable([this]() { this->updateRxInt(); });
60}
61
62Tick
63Pl050::read(PacketPtr pkt)
64{
65    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
66
67    Addr daddr = pkt->getAddr() - pioAddr;
68
69    uint32_t data = 0;
70
71    switch (daddr) {
72      case kmiCr:
73        DPRINTF(Pl050, "Read Commmand: %#x\n", (uint32_t)control);
74        data = control;
75        break;
76
77      case kmiStat:
78        status.rxfull = ps2->hostDataAvailable() ? 1 : 0;
79        DPRINTF(Pl050, "Read Status: %#x\n", (uint32_t)status);
80        data = status;
81        break;
82
83      case kmiData:
84        data = ps2->hostDataAvailable() ? ps2->hostRead() : 0;
85        updateRxInt();
86        DPRINTF(Pl050, "Read Data: %#x\n", (uint32_t)data);
87        break;
88
89      case kmiClkDiv:
90        data = clkdiv;
91        break;
92
93      case kmiISR:
94        data = getInterrupt();
95        DPRINTF(Pl050, "Read Interrupts: %#x\n", getInterrupt());
96        break;
97
98      default:
99        if (readId(pkt, ambaId, pioAddr)) {
100            // Hack for variable size accesses
101            data = pkt->getLE<uint32_t>();
102            break;
103        }
104
105        warn("Tried to read PL050 at offset %#x that doesn't exist\n", daddr);
106        break;
107    }
108
109    pkt->setUintX(data, LittleEndianByteOrder);
110    pkt->makeAtomicResponse();
111    return pioDelay;
112}
113
114Tick
115Pl050::write(PacketPtr pkt)
116{
117
118    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
119
120    Addr daddr = pkt->getAddr() - pioAddr;
121    const uint32_t data = pkt->getUintX(LittleEndianByteOrder);
122
123    panic_if(pkt->getSize() != 1,
124             "PL050: Unexpected write size "
125             "(offset: %#x, data: %#x, size: %u)\n",
126             daddr, data, pkt->getSize());
127
128    switch (daddr) {
129      case kmiCr:
130        DPRINTF(Pl050, "Write Commmand: %#x\n", data);
131        // Use the update interrupts helper to make sure any interrupt
132        // mask changes are handled correctly.
133        setControl((uint8_t)data);
134        break;
135
136      case kmiData:
137        DPRINTF(Pl050, "Write Data: %#x\n", data);
138        // Clear the TX interrupt before writing new data.
139        setTxInt(false);
140        ps2->hostWrite((uint8_t)data);
141        // Data is written in 0 time, so raise the TX interrupt again.
142        setTxInt(true);
143        break;
144
145      case kmiClkDiv:
146        clkdiv = (uint8_t)data;
147        break;
148
149      default:
150        warn("PL050: Unhandled write of %#x to offset %#x\n", data, daddr);
151        break;
152    }
153
154    pkt->makeAtomicResponse();
155    return pioDelay;
156}
157
158void
159Pl050::setTxInt(bool value)
160{
161    InterruptReg ints = rawInterrupts;
162
163    ints.tx = value ? 1 : 0;
164
165    setInterrupts(ints);
166}
167
168void
169Pl050::updateRxInt()
170{
171    InterruptReg ints = rawInterrupts;
172
173    ints.rx = ps2->hostDataAvailable() ? 1 : 0;
174
175    setInterrupts(ints);
176}
177
178void
179Pl050::updateIntCtrl(InterruptReg ints, ControlReg ctrl)
180{
181    const bool old_pending(getInterrupt());
182    control = ctrl;
183    rawInterrupts = ints;
184    const bool new_pending(getInterrupt());
185
186    if (!old_pending && new_pending) {
187        DPRINTF(Pl050, "Generate interrupt: rawInt=%#x ctrl=%#x int=%#x\n",
188                rawInterrupts, control, getInterrupt());
189        gic->sendInt(intNum);
190    } else if (old_pending && !new_pending) {
191        DPRINTF(Pl050, "Clear interrupt: rawInt=%#x ctrl=%#x int=%#x\n",
192                rawInterrupts, control, getInterrupt());
193        gic->clearInt(intNum);
194    }
195}
196
197Pl050::InterruptReg
198Pl050::getInterrupt() const
199{
200    InterruptReg tmp_interrupt(0);
201
202    tmp_interrupt.tx = rawInterrupts.tx & control.txint_enable;
203    tmp_interrupt.rx = rawInterrupts.rx & control.rxint_enable;
204
205    return tmp_interrupt;
206}
207
208void
209Pl050::serialize(CheckpointOut &cp) const
210{
211    paramOut(cp, "ctrlreg", control);
212    paramOut(cp, "stsreg", status);
213    SERIALIZE_SCALAR(clkdiv);
214    paramOut(cp, "raw_ints", rawInterrupts);
215}
216
217void
218Pl050::unserialize(CheckpointIn &cp)
219{
220    paramIn(cp, "ctrlreg", control);
221    paramIn(cp, "stsreg", status);
222    UNSERIALIZE_SCALAR(clkdiv);
223    paramIn(cp, "raw_ints", rawInterrupts);
224}
225
226Pl050 *
227Pl050Params::create()
228{
229    return new Pl050(this);
230}
231