RealView.py revision 11296
110780SCurtis.Dunham@arm.com# Copyright (c) 2009-2015 ARM Limited 27090SN/A# All rights reserved. 37090SN/A# 47090SN/A# The license below extends only to copyright in the software and shall 57090SN/A# not be construed as granting a license to any other intellectual 67090SN/A# property including but not limited to intellectual property relating 77090SN/A# to a hardware implementation of the functionality of the software 87090SN/A# licensed hereunder. You may use the software subject to the license 97090SN/A# terms below provided that you ensure that this notice is replicated 107090SN/A# unmodified and in its entirety in all distributions of the software, 117090SN/A# modified or unmodified, in source code or in binary form. 127090SN/A# 134486SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 397584SAli.Saidi@arm.com# Authors: Ali Saidi 407584SAli.Saidi@arm.com# Gabe Black 417754SWilliam.Wang@arm.com# William Wang 424486SN/A 433630SN/Afrom m5.params import * 443630SN/Afrom m5.proxy import * 4511011SAndreas.Sandberg@ARM.comfrom ClockDomain import ClockDomain 4611011SAndreas.Sandberg@ARM.comfrom VoltageDomain import VoltageDomain 477587SAli.Saidi@arm.comfrom Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 4811244Sandreas.sandberg@arm.comfrom PciHost import * 4910353SGeoffrey.Blake@arm.comfrom Ethernet import NSGigE, IGbE_igb, IGbE_e1000 508212SAli.Saidi@ARM.comfrom Ide import * 515478SN/Afrom Platform import Platform 525478SN/Afrom Terminal import Terminal 537584SAli.Saidi@arm.comfrom Uart import Uart 548931Sandreas.hansson@arm.comfrom SimpleMemory import SimpleMemory 559525SAndreas.Sandberg@ARM.comfrom Gic import * 5610397Sstephan.diestelhorst@arm.comfrom EnergyCtrl import EnergyCtrl 5711090Sandreas.sandberg@arm.comfrom ClockDomain import SrcClockDomain 5811236Sandreas.sandberg@arm.comfrom SubSystem import SubSystem 593630SN/A 609806Sstever@gmail.comclass AmbaPioDevice(BasicPioDevice): 619806Sstever@gmail.com type = 'AmbaPioDevice' 627584SAli.Saidi@arm.com abstract = True 639338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 647584SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 653898SN/A 669806Sstever@gmail.comclass AmbaIntDevice(AmbaPioDevice): 677950SAli.Saidi@ARM.com type = 'AmbaIntDevice' 687950SAli.Saidi@ARM.com abstract = True 699338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 709525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 717950SAli.Saidi@ARM.com int_num = Param.UInt32("Interrupt number that connects to GIC") 727950SAli.Saidi@ARM.com int_delay = Param.Latency("100ns", 737950SAli.Saidi@ARM.com "Time between action and interrupt generation by device") 747950SAli.Saidi@ARM.com 757587SAli.Saidi@arm.comclass AmbaDmaDevice(DmaDevice): 767587SAli.Saidi@arm.com type = 'AmbaDmaDevice' 777587SAli.Saidi@arm.com abstract = True 789338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 797753SWilliam.Wang@arm.com pio_addr = Param.Addr("Address for AMBA slave interface") 807753SWilliam.Wang@arm.com pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 819525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 827753SWilliam.Wang@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 837587SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 847587SAli.Saidi@arm.com 858282SAli.Saidi@ARM.comclass A9SCU(BasicPioDevice): 868282SAli.Saidi@ARM.com type = 'A9SCU' 879338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/a9scu.hh" 888282SAli.Saidi@ARM.com 8911296Sandreas.sandberg@arm.comclass ArmPciIntRouting(Enum): vals = [ 9011296Sandreas.sandberg@arm.com 'ARM_PCI_INT_STATIC', 9111296Sandreas.sandberg@arm.com 'ARM_PCI_INT_DEV', 9211296Sandreas.sandberg@arm.com 'ARM_PCI_INT_PIN', 9311296Sandreas.sandberg@arm.com ] 9411296Sandreas.sandberg@arm.com 9511296Sandreas.sandberg@arm.comclass GenericArmPciHost(GenericPciHost): 9611296Sandreas.sandberg@arm.com type = 'GenericArmPciHost' 9711296Sandreas.sandberg@arm.com cxx_header = "dev/arm/pci_host.hh" 9811296Sandreas.sandberg@arm.com 9911296Sandreas.sandberg@arm.com int_policy = Param.ArmPciIntRouting("PCI interrupt routing policy") 10011296Sandreas.sandberg@arm.com int_base = Param.Unsigned("PCI interrupt base") 10111296Sandreas.sandberg@arm.com int_count = Param.Unsigned("Maximum number of interrupts used by this host") 10211296Sandreas.sandberg@arm.com 1037584SAli.Saidi@arm.comclass RealViewCtrl(BasicPioDevice): 1047584SAli.Saidi@arm.com type = 'RealViewCtrl' 1059338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 1068524SAli.Saidi@ARM.com proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 1078524SAli.Saidi@ARM.com proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 1088299Schander.sudanthi@arm.com idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 1097584SAli.Saidi@arm.com 11011011SAndreas.Sandberg@ARM.comclass RealViewOsc(ClockDomain): 11111011SAndreas.Sandberg@ARM.com type = 'RealViewOsc' 11211011SAndreas.Sandberg@ARM.com cxx_header = "dev/arm/rv_ctrl.hh" 11311011SAndreas.Sandberg@ARM.com 11411011SAndreas.Sandberg@ARM.com parent = Param.RealViewCtrl(Parent.any, "RealView controller") 11511011SAndreas.Sandberg@ARM.com 11611011SAndreas.Sandberg@ARM.com # TODO: We currently don't have the notion of a clock source, 11711011SAndreas.Sandberg@ARM.com # which means we have to associate oscillators with a voltage 11811011SAndreas.Sandberg@ARM.com # source. 11911011SAndreas.Sandberg@ARM.com voltage_domain = Param.VoltageDomain(Parent.voltage_domain, 12011011SAndreas.Sandberg@ARM.com "Voltage domain") 12111011SAndreas.Sandberg@ARM.com 12211011SAndreas.Sandberg@ARM.com # See ARM DUI 0447J (ARM Motherboard Express uATX -- V2M-P1) and 12311011SAndreas.Sandberg@ARM.com # the individual core/logic tile reference manuals for details 12411011SAndreas.Sandberg@ARM.com # about the site/position/dcc/device allocation. 12511011SAndreas.Sandberg@ARM.com site = Param.UInt8("Board Site") 12611011SAndreas.Sandberg@ARM.com position = Param.UInt8("Position in device stack") 12711011SAndreas.Sandberg@ARM.com dcc = Param.UInt8("Daughterboard Configuration Controller") 12811011SAndreas.Sandberg@ARM.com device = Param.UInt8("Device ID") 12911011SAndreas.Sandberg@ARM.com 13011011SAndreas.Sandberg@ARM.com freq = Param.Clock("Default frequency") 13111011SAndreas.Sandberg@ARM.com 13211236Sandreas.sandberg@arm.comclass VExpressMCC(SubSystem): 13311236Sandreas.sandberg@arm.com """ARM V2M-P1 Motherboard Configuration Controller 13411236Sandreas.sandberg@arm.com 13511236Sandreas.sandberg@arm.comThis subsystem describes a subset of the devices that sit behind the 13611236Sandreas.sandberg@arm.commotherboard configuration controller on the the ARM Motherboard 13711236Sandreas.sandberg@arm.comExpress (V2M-P1) motherboard. See ARM DUI 0447J for details. 13811236Sandreas.sandberg@arm.com """ 13911236Sandreas.sandberg@arm.com 14011236Sandreas.sandberg@arm.com class Osc(RealViewOsc): 14111011SAndreas.Sandberg@ARM.com site, position, dcc = (0, 0, 0) 14211011SAndreas.Sandberg@ARM.com 14311236Sandreas.sandberg@arm.com osc_mcc = Osc(device=0, freq="50MHz") 14411236Sandreas.sandberg@arm.com osc_clcd = Osc(device=1, freq="23.75MHz") 14511236Sandreas.sandberg@arm.com osc_peripheral = Osc(device=2, freq="24MHz") 14611236Sandreas.sandberg@arm.com osc_system_bus = Osc(device=4, freq="24MHz") 14711236Sandreas.sandberg@arm.com 14811236Sandreas.sandberg@arm.comclass CoreTile2A15DCC(SubSystem): 14911236Sandreas.sandberg@arm.com """ARM CoreTile Express A15x2 Daughterboard Configuration Controller 15011236Sandreas.sandberg@arm.com 15111236Sandreas.sandberg@arm.comThis subsystem describes a subset of the devices that sit behind the 15211236Sandreas.sandberg@arm.comdaughterboard configuration controller on a CoreTile Express A15x2. See 15311236Sandreas.sandberg@arm.comARM DUI 0604E for details. 15411236Sandreas.sandberg@arm.com """ 15511236Sandreas.sandberg@arm.com 15611236Sandreas.sandberg@arm.com class Osc(RealViewOsc): 15711011SAndreas.Sandberg@ARM.com site, position, dcc = (1, 0, 0) 15811011SAndreas.Sandberg@ARM.com 15911236Sandreas.sandberg@arm.com # See Table 2.8 in ARM DUI 0604E (CoreTile Express A15x2 TRM) 16011236Sandreas.sandberg@arm.com osc_cpu = Osc(device=0, freq="60MHz") 16111236Sandreas.sandberg@arm.com osc_hsbm = Osc(device=4, freq="40MHz") 16211236Sandreas.sandberg@arm.com osc_pxl = Osc(device=5, freq="23.75MHz") 16311236Sandreas.sandberg@arm.com osc_smb = Osc(device=6, freq="50MHz") 16411236Sandreas.sandberg@arm.com osc_sys = Osc(device=7, freq="60MHz") 16511236Sandreas.sandberg@arm.com osc_ddr = Osc(device=8, freq="40MHz") 16611011SAndreas.Sandberg@ARM.com 16710037SARM gem5 Developersclass VGic(PioDevice): 16810037SARM gem5 Developers type = 'VGic' 16910037SARM gem5 Developers cxx_header = "dev/arm/vgic.hh" 17010037SARM gem5 Developers gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 17110037SARM gem5 Developers platform = Param.Platform(Parent.any, "Platform this device is part of.") 17210037SARM gem5 Developers vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 17310037SARM gem5 Developers hv_addr = Param.Addr(0, "Address for hv control") 17410037SARM gem5 Developers pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 17510037SARM gem5 Developers # The number of list registers is not currently configurable at runtime. 17610037SARM gem5 Developers ppint = Param.UInt32("HV maintenance interrupt number") 17710037SARM gem5 Developers 1789806Sstever@gmail.comclass AmbaFake(AmbaPioDevice): 1797584SAli.Saidi@arm.com type = 'AmbaFake' 1809338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_fake.hh" 1817584SAli.Saidi@arm.com ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 1827584SAli.Saidi@arm.com amba_id = 0; 1837584SAli.Saidi@arm.com 1847584SAli.Saidi@arm.comclass Pl011(Uart): 1857584SAli.Saidi@arm.com type = 'Pl011' 1869338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl011.hh" 1879525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1887584SAli.Saidi@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 1897584SAli.Saidi@arm.com end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 1907584SAli.Saidi@arm.com int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 1917584SAli.Saidi@arm.com 1929806Sstever@gmail.comclass Sp804(AmbaPioDevice): 1937584SAli.Saidi@arm.com type = 'Sp804' 1949338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_sp804.hh" 1959525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1967584SAli.Saidi@arm.com int_num0 = Param.UInt32("Interrupt number that connects to GIC") 1977584SAli.Saidi@arm.com clock0 = Param.Clock('1MHz', "Clock speed of the input") 1987584SAli.Saidi@arm.com int_num1 = Param.UInt32("Interrupt number that connects to GIC") 1997584SAli.Saidi@arm.com clock1 = Param.Clock('1MHz', "Clock speed of the input") 2007584SAli.Saidi@arm.com amba_id = 0x00141804 2017584SAli.Saidi@arm.com 2028512Sgeoffrey.blake@arm.comclass CpuLocalTimer(BasicPioDevice): 2038512Sgeoffrey.blake@arm.com type = 'CpuLocalTimer' 2049338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_cpulocal.hh" 2059525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 2068512Sgeoffrey.blake@arm.com int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 2078512Sgeoffrey.blake@arm.com int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 2088512Sgeoffrey.blake@arm.com 20910037SARM gem5 Developersclass GenericTimer(SimObject): 21010037SARM gem5 Developers type = 'GenericTimer' 21110037SARM gem5 Developers cxx_header = "dev/arm/generic_timer.hh" 21210037SARM gem5 Developers system = Param.System(Parent.any, "system") 21310037SARM gem5 Developers gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 21410845Sandreas.sandberg@arm.com # @todo: for now only two timers per CPU is supported, which is the 21510845Sandreas.sandberg@arm.com # normal behaviour when security extensions are disabled. 21610845Sandreas.sandberg@arm.com int_phys = Param.UInt32("Physical timer interrupt number") 21710845Sandreas.sandberg@arm.com int_virt = Param.UInt32("Virtual timer interrupt number") 21810037SARM gem5 Developers 21910847Sandreas.sandberg@arm.comclass GenericTimerMem(PioDevice): 22010847Sandreas.sandberg@arm.com type = 'GenericTimerMem' 22110847Sandreas.sandberg@arm.com cxx_header = "dev/arm/generic_timer.hh" 22210847Sandreas.sandberg@arm.com gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 22310847Sandreas.sandberg@arm.com 22410847Sandreas.sandberg@arm.com base = Param.Addr(0, "Base address") 22510847Sandreas.sandberg@arm.com 22610847Sandreas.sandberg@arm.com int_phys = Param.UInt32("Interrupt number") 22710847Sandreas.sandberg@arm.com int_virt = Param.UInt32("Interrupt number") 22810847Sandreas.sandberg@arm.com 2298870SAli.Saidi@ARM.comclass PL031(AmbaIntDevice): 2308870SAli.Saidi@ARM.com type = 'PL031' 2319338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rtc_pl031.hh" 2328870SAli.Saidi@ARM.com time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 2338870SAli.Saidi@ARM.com amba_id = 0x00341031 2348870SAli.Saidi@ARM.com 2357950SAli.Saidi@ARM.comclass Pl050(AmbaIntDevice): 2367754SWilliam.Wang@arm.com type = 'Pl050' 2379338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/kmi.hh" 2389330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 2397950SAli.Saidi@ARM.com is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 2407950SAli.Saidi@ARM.com int_delay = '1us' 2417754SWilliam.Wang@arm.com amba_id = 0x00141050 2427754SWilliam.Wang@arm.com 2437753SWilliam.Wang@arm.comclass Pl111(AmbaDmaDevice): 2447753SWilliam.Wang@arm.com type = 'Pl111' 2459338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl111.hh" 2469394Sandreas.hansson@arm.com pixel_clock = Param.Clock('24MHz', "Pixel clock") 2479330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 2487753SWilliam.Wang@arm.com amba_id = 0x00141111 2499939Sdam.sunwoo@arm.com enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 2509939Sdam.sunwoo@arm.com 2519646SChris.Emmons@arm.comclass HDLcd(AmbaDmaDevice): 2529646SChris.Emmons@arm.com type = 'HDLcd' 2539646SChris.Emmons@arm.com cxx_header = "dev/arm/hdlcd.hh" 2549646SChris.Emmons@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 2559646SChris.Emmons@arm.com "display") 2569646SChris.Emmons@arm.com amba_id = 0x00141000 25711237Sandreas.sandberg@arm.com workaround_swap_rb = Param.Bool(False, "Workaround incorrect color " 25810840Sandreas.sandberg@arm.com "selector order in some kernels") 25911090Sandreas.sandberg@arm.com workaround_dma_line_count = Param.Bool(True, "Workaround incorrect " 26011090Sandreas.sandberg@arm.com "DMA line count (off by 1)") 2619939Sdam.sunwoo@arm.com enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 2629646SChris.Emmons@arm.com 26311090Sandreas.sandberg@arm.com pixel_buffer_size = Param.MemorySize32("2kB", "Size of address range") 26411090Sandreas.sandberg@arm.com 26511090Sandreas.sandberg@arm.com pxl_clk = Param.ClockDomain("Pixel clock source") 26611090Sandreas.sandberg@arm.com pixel_chunk = Param.Unsigned(32, "Number of pixels to handle in one batch") 26711090Sandreas.sandberg@arm.com 2687584SAli.Saidi@arm.comclass RealView(Platform): 2697584SAli.Saidi@arm.com type = 'RealView' 2709338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/realview.hh" 2713630SN/A system = Param.System(Parent.any, "system") 27210358SAli.Saidi@ARM.com _mem_regions = [(Addr(0), Addr('256MB'))] 2738870SAli.Saidi@ARM.com 27410353SGeoffrey.Blake@arm.com def attachPciDevices(self): 27510353SGeoffrey.Blake@arm.com pass 27610353SGeoffrey.Blake@arm.com 27710353SGeoffrey.Blake@arm.com def enableMSIX(self): 27810353SGeoffrey.Blake@arm.com pass 27910353SGeoffrey.Blake@arm.com 28010353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 28110353SGeoffrey.Blake@arm.com pass 28210353SGeoffrey.Blake@arm.com 28310353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 28410353SGeoffrey.Blake@arm.com pass 28510353SGeoffrey.Blake@arm.com 2868870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 2879835Sandreas.hansson@arm.com self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 2889835Sandreas.hansson@arm.com conf_table_reported = False) 2898870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 2908870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot.arm') 29110037SARM gem5 Developers cur_sys.atags_addr = 0x100 29210037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 29310037SARM gem5 Developers cur_sys.load_offset = 0 2948870SAli.Saidi@ARM.com 2953630SN/A 2967753SWilliam.Wang@arm.com# Reference for memory map and interrupt number 2977753SWilliam.Wang@arm.com# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 2987753SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 2997584SAli.Saidi@arm.comclass RealViewPBX(RealView): 3007584SAli.Saidi@arm.com uart = Pl011(pio_addr=0x10009000, int_num=44) 30111236Sandreas.sandberg@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000) 30211236Sandreas.sandberg@arm.com mcc = VExpressMCC() 30311236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 3049525SAndreas.Sandberg@ARM.com gic = Pl390() 30511244Sandreas.sandberg@arm.com pci_host = GenericPciHost( 30611244Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 30711244Sandreas.sandberg@arm.com pci_pio_base=0) 3087584SAli.Saidi@arm.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 3097584SAli.Saidi@arm.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 3108512Sgeoffrey.blake@arm.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 3117753SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=55) 3127754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 3137950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 3148282SAli.Saidi@ARM.com a9scu = A9SCU(pio_addr=0x1f000000) 3158525SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 3168212SAli.Saidi@ARM.com io_shift = 1, ctrl_offset = 2, Command = 0x1, 3178212SAli.Saidi@ARM.com BAR0 = 0x18000000, BAR0Size = '16B', 3188212SAli.Saidi@ARM.com BAR1 = 0x18000100, BAR1Size = '1B', 3198212SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 3208212SAli.Saidi@ARM.com 3217584SAli.Saidi@arm.com 3227731SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 3238461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 3248461SAli.Saidi@ARM.com fake_mem=True) 3257696SAli.Saidi@ARM.com dmac_fake = AmbaFake(pio_addr=0x10030000) 3267696SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 3277696SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 3287696SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 3297696SAli.Saidi@ARM.com smc_fake = AmbaFake(pio_addr=0x100e1000) 3307696SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 3317696SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 3327696SAli.Saidi@ARM.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 3337696SAli.Saidi@ARM.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 3347696SAli.Saidi@ARM.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 3357696SAli.Saidi@ARM.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 3367696SAli.Saidi@ARM.com sci_fake = AmbaFake(pio_addr=0x1000e000) 3377696SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x10004000) 3387696SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x10005000) 3398906Skoansin.tan@gmail.com rtc = PL031(pio_addr=0x10017000, int_num=42) 34010397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 3417696SAli.Saidi@ARM.com 3427696SAli.Saidi@ARM.com 3438713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 3448713Sandreas.hansson@arm.com # ranges for the bridge 3458713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 3468839Sandreas.hansson@arm.com self.gic.pio = bus.master 3478839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 3488839Sandreas.hansson@arm.com self.a9scu.pio = bus.master 3498839Sandreas.hansson@arm.com self.local_cpu_timer.pio = bus.master 3508713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 3518713Sandreas.hansson@arm.com # (gic, l2x0, a9scu, local_cpu_timer) 3528713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 3538713Sandreas.hansson@arm.com self.a9scu.pio_addr - 1), 3548870SAli.Saidi@ARM.com AddrRange(self.flash_fake.pio_addr, 3558870SAli.Saidi@ARM.com self.flash_fake.pio_addr + \ 3568870SAli.Saidi@ARM.com self.flash_fake.pio_size - 1)] 3577696SAli.Saidi@ARM.com 35810353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 35910353SGeoffrey.Blake@arm.com # to be "close" to the cores. 36010353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 36110353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 36210353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 36310353SGeoffrey.Blake@arm.com self.a9scu.clkdomain = clkdomain 36410353SGeoffrey.Blake@arm.com self.local_cpu_timer.clk_domain = clkdomain 36510353SGeoffrey.Blake@arm.com 3667696SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 3677696SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 3687696SAli.Saidi@ARM.com # System level. 3697696SAli.Saidi@ARM.com def attachIO(self, bus): 3708839Sandreas.hansson@arm.com self.uart.pio = bus.master 3718839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 37211244Sandreas.sandberg@arm.com self.pci_host.pio = bus.master 3738839Sandreas.hansson@arm.com self.timer0.pio = bus.master 3748839Sandreas.hansson@arm.com self.timer1.pio = bus.master 3758839Sandreas.hansson@arm.com self.clcd.pio = bus.master 3768839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 3778839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 3788839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 3798839Sandreas.hansson@arm.com self.cf_ctrl.pio = bus.master 3808839Sandreas.hansson@arm.com self.cf_ctrl.dma = bus.slave 3818839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 3828839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 3838839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 3848839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 3858839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 3868839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 3878839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 3888839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 3898839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 3908839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 3918839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 3928839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 3938839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 3948839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 3958906Skoansin.tan@gmail.com self.rtc.pio = bus.master 3968839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 39710397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 3987696SAli.Saidi@ARM.com 39910353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 40010353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 40110353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 40210353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 40310353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 40410353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 40510353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 40610353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 40710353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 40810353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 40910353SGeoffrey.Blake@arm.com self.cf_ctrl.clk_domain = clkdomain 41010353SGeoffrey.Blake@arm.com self.dmac_fake.clk_domain = clkdomain 41110353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 41210353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 41310353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 41410353SGeoffrey.Blake@arm.com self.smc_fake.clk_domain = clkdomain 41510353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 41610353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 41710353SGeoffrey.Blake@arm.com self.gpio0_fake.clk_domain = clkdomain 41810353SGeoffrey.Blake@arm.com self.gpio1_fake.clk_domain = clkdomain 41910353SGeoffrey.Blake@arm.com self.gpio2_fake.clk_domain = clkdomain 42010353SGeoffrey.Blake@arm.com self.ssp_fake.clk_domain = clkdomain 42110353SGeoffrey.Blake@arm.com self.sci_fake.clk_domain = clkdomain 42210353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 42310353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 42410353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 42510353SGeoffrey.Blake@arm.com self.flash_fake.clk_domain = clkdomain 42610397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 42710353SGeoffrey.Blake@arm.com 4287754SWilliam.Wang@arm.com# Reference for memory map and interrupt number 4297754SWilliam.Wang@arm.com# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 4307754SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 4317696SAli.Saidi@ARM.comclass RealViewEB(RealView): 4327696SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x10009000, int_num=44) 43311236Sandreas.sandberg@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500) 43411236Sandreas.sandberg@arm.com mcc = VExpressMCC() 43511236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 4369525SAndreas.Sandberg@ARM.com gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 4377696SAli.Saidi@ARM.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 4387696SAli.Saidi@ARM.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 4397754SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=23) 4407754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 4417950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 4427696SAli.Saidi@ARM.com 4437696SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 4448461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 4458461SAli.Saidi@ARM.com fake_mem=True) 4467584SAli.Saidi@arm.com dmac_fake = AmbaFake(pio_addr=0x10030000) 4477584SAli.Saidi@arm.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 4487584SAli.Saidi@arm.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 4497584SAli.Saidi@arm.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 4508299Schander.sudanthi@arm.com smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 4517584SAli.Saidi@arm.com smc_fake = AmbaFake(pio_addr=0x100e1000) 4527584SAli.Saidi@arm.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 4537584SAli.Saidi@arm.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 4547584SAli.Saidi@arm.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 4557584SAli.Saidi@arm.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 4567584SAli.Saidi@arm.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 4577584SAli.Saidi@arm.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 4587584SAli.Saidi@arm.com sci_fake = AmbaFake(pio_addr=0x1000e000) 4597584SAli.Saidi@arm.com aaci_fake = AmbaFake(pio_addr=0x10004000) 4607584SAli.Saidi@arm.com mmc_fake = AmbaFake(pio_addr=0x10005000) 4617584SAli.Saidi@arm.com rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 46210397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 4637584SAli.Saidi@arm.com 4648713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 4658713Sandreas.hansson@arm.com # ranges for the bridge 4668713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 4678839Sandreas.hansson@arm.com self.gic.pio = bus.master 4688839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 4698713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 4708713Sandreas.hansson@arm.com # (gic, l2x0) 4718713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 4728713Sandreas.hansson@arm.com self.gic.cpu_addr - 1), 4738713Sandreas.hansson@arm.com AddrRange(self.flash_fake.pio_addr, Addr.max)] 4744104SN/A 47510353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 47610353SGeoffrey.Blake@arm.com # to be "close" to the cores. 47710353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 47810353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 47910353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 48010353SGeoffrey.Blake@arm.com 4813630SN/A # Attach I/O devices to specified bus object. Can't do this 4823630SN/A # earlier, since the bus object itself is typically defined at the 4833630SN/A # System level. 4843630SN/A def attachIO(self, bus): 4858839Sandreas.hansson@arm.com self.uart.pio = bus.master 4868839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 48711244Sandreas.sandberg@arm.com self.pci_host.pio = bus.master 4888839Sandreas.hansson@arm.com self.timer0.pio = bus.master 4898839Sandreas.hansson@arm.com self.timer1.pio = bus.master 4908839Sandreas.hansson@arm.com self.clcd.pio = bus.master 4918839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 4928839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 4938839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 4948839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 4958839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 4968839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 4978839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 4988839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 4998839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 5008839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 5018839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 5028839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 5038839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 5048839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 5058839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 5068839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 5078839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 5088839Sandreas.hansson@arm.com self.rtc_fake.pio = bus.master 5098839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 5108839Sandreas.hansson@arm.com self.smcreg_fake.pio = bus.master 51110397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 5127584SAli.Saidi@arm.com 51310353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 51410353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 51510353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 51610353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 51710353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 51810353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 51910353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 52010353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 52110353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 52210353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 52310353SGeoffrey.Blake@arm.com self.dmac_fake.clk_domain = clkdomain 52410353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 52510353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 52610353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 52710353SGeoffrey.Blake@arm.com self.smc_fake.clk_domain = clkdomain 52810353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 52910353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 53010353SGeoffrey.Blake@arm.com self.gpio0_fake.clk_domain = clkdomain 53110353SGeoffrey.Blake@arm.com self.gpio1_fake.clk_domain = clkdomain 53210353SGeoffrey.Blake@arm.com self.gpio2_fake.clk_domain = clkdomain 53310353SGeoffrey.Blake@arm.com self.ssp_fake.clk_domain = clkdomain 53410353SGeoffrey.Blake@arm.com self.sci_fake.clk_domain = clkdomain 53510353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 53610353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 53710353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 53810353SGeoffrey.Blake@arm.com self.flash_fake.clk_domain = clkdomain 53910353SGeoffrey.Blake@arm.com self.smcreg_fake.clk_domain = clkdomain 54010397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 54110353SGeoffrey.Blake@arm.com 5428870SAli.Saidi@ARM.comclass VExpress_EMM(RealView): 54310358SAli.Saidi@ARM.com _mem_regions = [(Addr('2GB'), Addr('2GB'))] 5448870SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x1c090000, int_num=37) 54511236Sandreas.sandberg@arm.com realview_io = RealViewCtrl( 54611011SAndreas.Sandberg@ARM.com proc_id0=0x14000000, proc_id1=0x14000000, 54711011SAndreas.Sandberg@ARM.com idreg=0x02250000, pio_addr=0x1C010000) 54811236Sandreas.sandberg@arm.com mcc = VExpressMCC() 54911236Sandreas.sandberg@arm.com dcc = CoreTile2A15DCC() 5509525SAndreas.Sandberg@ARM.com gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 55111244Sandreas.sandberg@arm.com pci_host = GenericPciHost( 55211244Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=16, 55311244Sandreas.sandberg@arm.com pci_pio_base=0) 5548870SAli.Saidi@ARM.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 55510845Sandreas.sandberg@arm.com generic_timer = GenericTimer(int_phys=29, int_virt=27) 5569185SAli.Saidi@ARM.com timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 5579185SAli.Saidi@ARM.com timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 5588870SAli.Saidi@ARM.com clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 55911236Sandreas.sandberg@arm.com hdlcd = HDLcd(pxl_clk=dcc.osc_pxl, 56011237Sandreas.sandberg@arm.com pio_addr=0x2b000000, int_num=117, 56111237Sandreas.sandberg@arm.com workaround_swap_rb=True) 5628870SAli.Saidi@ARM.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 5639387SChris.Emmons@arm.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 56410037SARM gem5 Developers vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 5658870SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 5668870SAli.Saidi@ARM.com io_shift = 2, ctrl_offset = 2, Command = 0x1, 5678870SAli.Saidi@ARM.com BAR0 = 0x1C1A0000, BAR0Size = '256B', 5688870SAli.Saidi@ARM.com BAR1 = 0x1C1A0100, BAR1Size = '4096B', 5698870SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 5709052Sgeoffrey.blake@arm.com 5719835Sandreas.hansson@arm.com vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 5729835Sandreas.hansson@arm.com conf_table_reported = False) 5738870SAli.Saidi@ARM.com rtc = PL031(pio_addr=0x1C170000, int_num=36) 5748870SAli.Saidi@ARM.com 5758870SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 5768870SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 5778870SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 5788870SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 5798870SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 5808870SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 5818870SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x1C040000) 5828870SAli.Saidi@ARM.com lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 5838870SAli.Saidi@ARM.com usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 5848870SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x1c050000) 58510397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1c080000) 5868870SAli.Saidi@ARM.com 58710353SGeoffrey.Blake@arm.com # Attach any PCI devices that are supported 58810353SGeoffrey.Blake@arm.com def attachPciDevices(self): 58910353SGeoffrey.Blake@arm.com self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 59010353SGeoffrey.Blake@arm.com InterruptLine=1, InterruptPin=1) 59110353SGeoffrey.Blake@arm.com self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 59210353SGeoffrey.Blake@arm.com InterruptLine=2, InterruptPin=2) 59310353SGeoffrey.Blake@arm.com 59410353SGeoffrey.Blake@arm.com def enableMSIX(self): 59510353SGeoffrey.Blake@arm.com self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512) 59610353SGeoffrey.Blake@arm.com self.gicv2m = Gicv2m() 59710353SGeoffrey.Blake@arm.com self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 59810353SGeoffrey.Blake@arm.com 5998870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 6009835Sandreas.hansson@arm.com self.nvmem = SimpleMemory(range = AddrRange('64MB'), 6019835Sandreas.hansson@arm.com conf_table_reported = False) 6028870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 6038870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot_emm.arm') 60410037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 60510037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 60610037SARM gem5 Developers cur_sys.load_offset = 0x80000000 6078870SAli.Saidi@ARM.com 6088870SAli.Saidi@ARM.com # Attach I/O devices that are on chip and also set the appropriate 6098870SAli.Saidi@ARM.com # ranges for the bridge 61010780SCurtis.Dunham@arm.com def attachOnChipIO(self, bus, bridge=None): 61110780SCurtis.Dunham@arm.com self.gic.pio = bus.master 61210780SCurtis.Dunham@arm.com self.vgic.pio = bus.master 61310780SCurtis.Dunham@arm.com self.local_cpu_timer.pio = bus.master 61410780SCurtis.Dunham@arm.com if hasattr(self, "gicv2m"): 61510780SCurtis.Dunham@arm.com self.gicv2m.pio = bus.master 61610780SCurtis.Dunham@arm.com self.hdlcd.dma = bus.slave 61710780SCurtis.Dunham@arm.com if bridge: 61810780SCurtis.Dunham@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 61910780SCurtis.Dunham@arm.com # (gic, a9scu) 62010780SCurtis.Dunham@arm.com bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 62110780SCurtis.Dunham@arm.com AddrRange(0x2B000000, size='4MB'), 62210780SCurtis.Dunham@arm.com AddrRange(0x30000000, size='256MB'), 62310780SCurtis.Dunham@arm.com AddrRange(0x40000000, size='512MB'), 62410780SCurtis.Dunham@arm.com AddrRange(0x18000000, size='64MB'), 62510780SCurtis.Dunham@arm.com AddrRange(0x1C000000, size='64MB')] 62610037SARM gem5 Developers 6278870SAli.Saidi@ARM.com 62810353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 62910353SGeoffrey.Blake@arm.com # to be "close" to the cores. 63010353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 63110353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 63210353SGeoffrey.Blake@arm.com if hasattr(self, "gicv2m"): 63310353SGeoffrey.Blake@arm.com self.gicv2m.clk_domain = clkdomain 63410353SGeoffrey.Blake@arm.com self.hdlcd.clk_domain = clkdomain 63510353SGeoffrey.Blake@arm.com self.vgic.clk_domain = clkdomain 63610353SGeoffrey.Blake@arm.com 63710353SGeoffrey.Blake@arm.com # Attach I/O devices to specified bus object. Done here 63810353SGeoffrey.Blake@arm.com # as the specified bus to connect to may not always be fixed. 6398870SAli.Saidi@ARM.com def attachIO(self, bus): 6408870SAli.Saidi@ARM.com self.uart.pio = bus.master 6418870SAli.Saidi@ARM.com self.realview_io.pio = bus.master 64211244Sandreas.sandberg@arm.com self.pci_host.pio = bus.master 6438870SAli.Saidi@ARM.com self.timer0.pio = bus.master 6448870SAli.Saidi@ARM.com self.timer1.pio = bus.master 6458870SAli.Saidi@ARM.com self.clcd.pio = bus.master 6468870SAli.Saidi@ARM.com self.clcd.dma = bus.slave 6479646SChris.Emmons@arm.com self.hdlcd.pio = bus.master 6488870SAli.Saidi@ARM.com self.kmi0.pio = bus.master 6498870SAli.Saidi@ARM.com self.kmi1.pio = bus.master 6508870SAli.Saidi@ARM.com self.cf_ctrl.pio = bus.master 6518872Ssaidi@eecs.umich.edu self.cf_ctrl.dma = bus.slave 6528870SAli.Saidi@ARM.com self.rtc.pio = bus.master 6538870SAli.Saidi@ARM.com self.vram.port = bus.master 6548870SAli.Saidi@ARM.com 6558870SAli.Saidi@ARM.com self.l2x0_fake.pio = bus.master 6568870SAli.Saidi@ARM.com self.uart1_fake.pio = bus.master 6578870SAli.Saidi@ARM.com self.uart2_fake.pio = bus.master 6588870SAli.Saidi@ARM.com self.uart3_fake.pio = bus.master 6598870SAli.Saidi@ARM.com self.sp810_fake.pio = bus.master 6608870SAli.Saidi@ARM.com self.watchdog_fake.pio = bus.master 6618870SAli.Saidi@ARM.com self.aaci_fake.pio = bus.master 6628870SAli.Saidi@ARM.com self.lan_fake.pio = bus.master 6638870SAli.Saidi@ARM.com self.usb_fake.pio = bus.master 6648870SAli.Saidi@ARM.com self.mmc_fake.pio = bus.master 66510397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 6668870SAli.Saidi@ARM.com 66710353SGeoffrey.Blake@arm.com # Try to attach the I/O if it exists 66810353SGeoffrey.Blake@arm.com try: 66910353SGeoffrey.Blake@arm.com self.ide.pio = bus.master 67010353SGeoffrey.Blake@arm.com self.ide.dma = bus.slave 67110353SGeoffrey.Blake@arm.com self.ethernet.pio = bus.master 67210353SGeoffrey.Blake@arm.com self.ethernet.dma = bus.slave 67310353SGeoffrey.Blake@arm.com except: 67410353SGeoffrey.Blake@arm.com pass 67510353SGeoffrey.Blake@arm.com 67610353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 67710353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 67810353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 67910353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 68010353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 68110353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 68210353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 68310353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 68410353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 68510353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 68610353SGeoffrey.Blake@arm.com self.cf_ctrl.clk_domain = clkdomain 68710353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 68810353SGeoffrey.Blake@arm.com self.vram.clk_domain = clkdomain 68910353SGeoffrey.Blake@arm.com 69010353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 69110353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 69210353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 69310353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 69410353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 69510353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 69610353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 69710353SGeoffrey.Blake@arm.com self.lan_fake.clk_domain = clkdomain 69810353SGeoffrey.Blake@arm.com self.usb_fake.clk_domain = clkdomain 69910353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 70010397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 70110353SGeoffrey.Blake@arm.com 70210037SARM gem5 Developersclass VExpress_EMM64(VExpress_EMM): 70310358SAli.Saidi@ARM.com # Three memory regions are specified totalling 512GB 70410358SAli.Saidi@ARM.com _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 70510358SAli.Saidi@ARM.com (Addr('512GB'), Addr('480GB'))] 70611244Sandreas.sandberg@arm.com pci_host = GenericPciHost( 70711244Sandreas.sandberg@arm.com conf_base=0x30000000, conf_size='256MB', conf_device_bits=12, 70811244Sandreas.sandberg@arm.com pci_pio_base=0x2f000000) 70911244Sandreas.sandberg@arm.com 71010037SARM gem5 Developers def setupBootLoader(self, mem_bus, cur_sys, loc): 71110037SARM gem5 Developers self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) 71210037SARM gem5 Developers self.nvmem.port = mem_bus.master 71310037SARM gem5 Developers cur_sys.boot_loader = loc('boot_emm.arm64') 71410037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 71510037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 71610037SARM gem5 Developers cur_sys.load_offset = 0x80000000 71710037SARM gem5 Developers 71810037SARM gem5 Developers 719