RealView.py revision 10845
110780SCurtis.Dunham@arm.com# Copyright (c) 2009-2015 ARM Limited 27090SN/A# All rights reserved. 37090SN/A# 47090SN/A# The license below extends only to copyright in the software and shall 57090SN/A# not be construed as granting a license to any other intellectual 67090SN/A# property including but not limited to intellectual property relating 77090SN/A# to a hardware implementation of the functionality of the software 87090SN/A# licensed hereunder. You may use the software subject to the license 97090SN/A# terms below provided that you ensure that this notice is replicated 107090SN/A# unmodified and in its entirety in all distributions of the software, 117090SN/A# modified or unmodified, in source code or in binary form. 127090SN/A# 134486SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 397584SAli.Saidi@arm.com# Authors: Ali Saidi 407584SAli.Saidi@arm.com# Gabe Black 417754SWilliam.Wang@arm.com# William Wang 424486SN/A 433630SN/Afrom m5.params import * 443630SN/Afrom m5.proxy import * 457587SAli.Saidi@arm.comfrom Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 468525SAli.Saidi@ARM.comfrom Pci import PciConfigAll 4710353SGeoffrey.Blake@arm.comfrom Ethernet import NSGigE, IGbE_igb, IGbE_e1000 488212SAli.Saidi@ARM.comfrom Ide import * 495478SN/Afrom Platform import Platform 505478SN/Afrom Terminal import Terminal 517584SAli.Saidi@arm.comfrom Uart import Uart 528931Sandreas.hansson@arm.comfrom SimpleMemory import SimpleMemory 539525SAndreas.Sandberg@ARM.comfrom Gic import * 5410397Sstephan.diestelhorst@arm.comfrom EnergyCtrl import EnergyCtrl 553630SN/A 569806Sstever@gmail.comclass AmbaPioDevice(BasicPioDevice): 579806Sstever@gmail.com type = 'AmbaPioDevice' 587584SAli.Saidi@arm.com abstract = True 599338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 607584SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 613898SN/A 629806Sstever@gmail.comclass AmbaIntDevice(AmbaPioDevice): 637950SAli.Saidi@ARM.com type = 'AmbaIntDevice' 647950SAli.Saidi@ARM.com abstract = True 659338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 669525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 677950SAli.Saidi@ARM.com int_num = Param.UInt32("Interrupt number that connects to GIC") 687950SAli.Saidi@ARM.com int_delay = Param.Latency("100ns", 697950SAli.Saidi@ARM.com "Time between action and interrupt generation by device") 707950SAli.Saidi@ARM.com 717587SAli.Saidi@arm.comclass AmbaDmaDevice(DmaDevice): 727587SAli.Saidi@arm.com type = 'AmbaDmaDevice' 737587SAli.Saidi@arm.com abstract = True 749338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_device.hh" 757753SWilliam.Wang@arm.com pio_addr = Param.Addr("Address for AMBA slave interface") 767753SWilliam.Wang@arm.com pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 779525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 787753SWilliam.Wang@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 797587SAli.Saidi@arm.com amba_id = Param.UInt32("ID of AMBA device for kernel detection") 807587SAli.Saidi@arm.com 818282SAli.Saidi@ARM.comclass A9SCU(BasicPioDevice): 828282SAli.Saidi@ARM.com type = 'A9SCU' 839338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/a9scu.hh" 848282SAli.Saidi@ARM.com 857584SAli.Saidi@arm.comclass RealViewCtrl(BasicPioDevice): 867584SAli.Saidi@arm.com type = 'RealViewCtrl' 879338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rv_ctrl.hh" 888524SAli.Saidi@ARM.com proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 898524SAli.Saidi@ARM.com proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 908299Schander.sudanthi@arm.com idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 917584SAli.Saidi@arm.com 9210037SARM gem5 Developersclass VGic(PioDevice): 9310037SARM gem5 Developers type = 'VGic' 9410037SARM gem5 Developers cxx_header = "dev/arm/vgic.hh" 9510037SARM gem5 Developers gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 9610037SARM gem5 Developers platform = Param.Platform(Parent.any, "Platform this device is part of.") 9710037SARM gem5 Developers vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 9810037SARM gem5 Developers hv_addr = Param.Addr(0, "Address for hv control") 9910037SARM gem5 Developers pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 10010037SARM gem5 Developers # The number of list registers is not currently configurable at runtime. 10110037SARM gem5 Developers ppint = Param.UInt32("HV maintenance interrupt number") 10210037SARM gem5 Developers 1039806Sstever@gmail.comclass AmbaFake(AmbaPioDevice): 1047584SAli.Saidi@arm.com type = 'AmbaFake' 1059338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/amba_fake.hh" 1067584SAli.Saidi@arm.com ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 1077584SAli.Saidi@arm.com amba_id = 0; 1087584SAli.Saidi@arm.com 1097584SAli.Saidi@arm.comclass Pl011(Uart): 1107584SAli.Saidi@arm.com type = 'Pl011' 1119338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl011.hh" 1129525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1137584SAli.Saidi@arm.com int_num = Param.UInt32("Interrupt number that connects to GIC") 1147584SAli.Saidi@arm.com end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 1157584SAli.Saidi@arm.com int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 1167584SAli.Saidi@arm.com 1179806Sstever@gmail.comclass Sp804(AmbaPioDevice): 1187584SAli.Saidi@arm.com type = 'Sp804' 1199338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_sp804.hh" 1209525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1217584SAli.Saidi@arm.com int_num0 = Param.UInt32("Interrupt number that connects to GIC") 1227584SAli.Saidi@arm.com clock0 = Param.Clock('1MHz', "Clock speed of the input") 1237584SAli.Saidi@arm.com int_num1 = Param.UInt32("Interrupt number that connects to GIC") 1247584SAli.Saidi@arm.com clock1 = Param.Clock('1MHz', "Clock speed of the input") 1257584SAli.Saidi@arm.com amba_id = 0x00141804 1267584SAli.Saidi@arm.com 1278512Sgeoffrey.blake@arm.comclass CpuLocalTimer(BasicPioDevice): 1288512Sgeoffrey.blake@arm.com type = 'CpuLocalTimer' 1299338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/timer_cpulocal.hh" 1309525SAndreas.Sandberg@ARM.com gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 1318512Sgeoffrey.blake@arm.com int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 1328512Sgeoffrey.blake@arm.com int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 1338512Sgeoffrey.blake@arm.com 13410037SARM gem5 Developersclass GenericTimer(SimObject): 13510037SARM gem5 Developers type = 'GenericTimer' 13610037SARM gem5 Developers cxx_header = "dev/arm/generic_timer.hh" 13710037SARM gem5 Developers system = Param.System(Parent.any, "system") 13810037SARM gem5 Developers gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 13910845Sandreas.sandberg@arm.com # @todo: for now only two timers per CPU is supported, which is the 14010845Sandreas.sandberg@arm.com # normal behaviour when security extensions are disabled. 14110845Sandreas.sandberg@arm.com int_phys = Param.UInt32("Physical timer interrupt number") 14210845Sandreas.sandberg@arm.com int_virt = Param.UInt32("Virtual timer interrupt number") 14310037SARM gem5 Developers 1448870SAli.Saidi@ARM.comclass PL031(AmbaIntDevice): 1458870SAli.Saidi@ARM.com type = 'PL031' 1469338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/rtc_pl031.hh" 1478870SAli.Saidi@ARM.com time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 1488870SAli.Saidi@ARM.com amba_id = 0x00341031 1498870SAli.Saidi@ARM.com 1507950SAli.Saidi@ARM.comclass Pl050(AmbaIntDevice): 1517754SWilliam.Wang@arm.com type = 'Pl050' 1529338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/kmi.hh" 1539330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 1547950SAli.Saidi@ARM.com is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 1557950SAli.Saidi@ARM.com int_delay = '1us' 1567754SWilliam.Wang@arm.com amba_id = 0x00141050 1577754SWilliam.Wang@arm.com 1587753SWilliam.Wang@arm.comclass Pl111(AmbaDmaDevice): 1597753SWilliam.Wang@arm.com type = 'Pl111' 1609338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/pl111.hh" 1619394Sandreas.hansson@arm.com pixel_clock = Param.Clock('24MHz', "Pixel clock") 1629330Schander.sudanthi@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 1637753SWilliam.Wang@arm.com amba_id = 0x00141111 1649939Sdam.sunwoo@arm.com enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 1659939Sdam.sunwoo@arm.com 1667753SWilliam.Wang@arm.com 1679646SChris.Emmons@arm.comclass HDLcd(AmbaDmaDevice): 1689646SChris.Emmons@arm.com type = 'HDLcd' 1699646SChris.Emmons@arm.com cxx_header = "dev/arm/hdlcd.hh" 17010187SChris.Emmons@arm.com # For reference, 1024x768MR-16@60 ~= 56 MHz 17110187SChris.Emmons@arm.com # 1920x1080MR-16@60 ~= 137 MHz 17210187SChris.Emmons@arm.com # 3840x2160MR-16@60 ~= 533 MHz 17310187SChris.Emmons@arm.com # Match against the resolution selected in the Linux DTS/DTB file. 17410187SChris.Emmons@arm.com pixel_clock = Param.Clock('137MHz', "Clock frequency of the pixel clock " 17510187SChris.Emmons@arm.com "(i.e. PXLREFCLK / OSCCLK 5") 1769646SChris.Emmons@arm.com vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 1779646SChris.Emmons@arm.com "display") 1789646SChris.Emmons@arm.com amba_id = 0x00141000 17910840Sandreas.sandberg@arm.com workaround_swap_rb = Param.Bool(True, "Workaround incorrect color " 18010840Sandreas.sandberg@arm.com "selector order in some kernels") 1819939Sdam.sunwoo@arm.com enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 1829646SChris.Emmons@arm.com 1837584SAli.Saidi@arm.comclass RealView(Platform): 1847584SAli.Saidi@arm.com type = 'RealView' 1859338SAndreas.Sandberg@arm.com cxx_header = "dev/arm/realview.hh" 1863630SN/A system = Param.System(Parent.any, "system") 18710356SAli.Saidi@ARM.com pci_io_base = Param.Addr(0, "Base address of PCI IO Space") 1888525SAli.Saidi@ARM.com pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 18910356SAli.Saidi@ARM.com pci_cfg_gen_offsets = Param.Bool(False, "Should the offsets used for PCI cfg access" 19010356SAli.Saidi@ARM.com " be compatible with the pci-generic-host or the legacy host bridge?") 19110358SAli.Saidi@ARM.com _mem_regions = [(Addr(0), Addr('256MB'))] 1928870SAli.Saidi@ARM.com 19310353SGeoffrey.Blake@arm.com def attachPciDevices(self): 19410353SGeoffrey.Blake@arm.com pass 19510353SGeoffrey.Blake@arm.com 19610353SGeoffrey.Blake@arm.com def enableMSIX(self): 19710353SGeoffrey.Blake@arm.com pass 19810353SGeoffrey.Blake@arm.com 19910353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 20010353SGeoffrey.Blake@arm.com pass 20110353SGeoffrey.Blake@arm.com 20210353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 20310353SGeoffrey.Blake@arm.com pass 20410353SGeoffrey.Blake@arm.com 2058870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 2069835Sandreas.hansson@arm.com self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 2079835Sandreas.hansson@arm.com conf_table_reported = False) 2088870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 2098870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot.arm') 21010037SARM gem5 Developers cur_sys.atags_addr = 0x100 21110037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 21210037SARM gem5 Developers cur_sys.load_offset = 0 2138870SAli.Saidi@ARM.com 2143630SN/A 2157753SWilliam.Wang@arm.com# Reference for memory map and interrupt number 2167753SWilliam.Wang@arm.com# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 2177753SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 2187584SAli.Saidi@arm.comclass RealViewPBX(RealView): 2197584SAli.Saidi@arm.com uart = Pl011(pio_addr=0x10009000, int_num=44) 2207584SAli.Saidi@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000) 2219525SAndreas.Sandberg@ARM.com gic = Pl390() 2227584SAli.Saidi@arm.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 2237584SAli.Saidi@arm.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 2248512Sgeoffrey.blake@arm.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 2257753SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=55) 2267754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 2277950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 2288282SAli.Saidi@ARM.com a9scu = A9SCU(pio_addr=0x1f000000) 2298525SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 2308212SAli.Saidi@ARM.com io_shift = 1, ctrl_offset = 2, Command = 0x1, 2318212SAli.Saidi@ARM.com BAR0 = 0x18000000, BAR0Size = '16B', 2328212SAli.Saidi@ARM.com BAR1 = 0x18000100, BAR1Size = '1B', 2338212SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 2348212SAli.Saidi@ARM.com 2357584SAli.Saidi@arm.com 2367731SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 2378461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 2388461SAli.Saidi@ARM.com fake_mem=True) 2397696SAli.Saidi@ARM.com dmac_fake = AmbaFake(pio_addr=0x10030000) 2407696SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 2417696SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 2427696SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 2437696SAli.Saidi@ARM.com smc_fake = AmbaFake(pio_addr=0x100e1000) 2447696SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 2457696SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 2467696SAli.Saidi@ARM.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 2477696SAli.Saidi@ARM.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 2487696SAli.Saidi@ARM.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 2497696SAli.Saidi@ARM.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 2507696SAli.Saidi@ARM.com sci_fake = AmbaFake(pio_addr=0x1000e000) 2517696SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x10004000) 2527696SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x10005000) 2538906Skoansin.tan@gmail.com rtc = PL031(pio_addr=0x10017000, int_num=42) 25410397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 2557696SAli.Saidi@ARM.com 2567696SAli.Saidi@ARM.com 2578713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 2588713Sandreas.hansson@arm.com # ranges for the bridge 2598713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 2608839Sandreas.hansson@arm.com self.gic.pio = bus.master 2618839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 2628839Sandreas.hansson@arm.com self.a9scu.pio = bus.master 2638839Sandreas.hansson@arm.com self.local_cpu_timer.pio = bus.master 2648713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 2658713Sandreas.hansson@arm.com # (gic, l2x0, a9scu, local_cpu_timer) 2668713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 2678713Sandreas.hansson@arm.com self.a9scu.pio_addr - 1), 2688870SAli.Saidi@ARM.com AddrRange(self.flash_fake.pio_addr, 2698870SAli.Saidi@ARM.com self.flash_fake.pio_addr + \ 2708870SAli.Saidi@ARM.com self.flash_fake.pio_size - 1)] 2717696SAli.Saidi@ARM.com 27210353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 27310353SGeoffrey.Blake@arm.com # to be "close" to the cores. 27410353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 27510353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 27610353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 27710353SGeoffrey.Blake@arm.com self.a9scu.clkdomain = clkdomain 27810353SGeoffrey.Blake@arm.com self.local_cpu_timer.clk_domain = clkdomain 27910353SGeoffrey.Blake@arm.com 2807696SAli.Saidi@ARM.com # Attach I/O devices to specified bus object. Can't do this 2817696SAli.Saidi@ARM.com # earlier, since the bus object itself is typically defined at the 2827696SAli.Saidi@ARM.com # System level. 2837696SAli.Saidi@ARM.com def attachIO(self, bus): 2848839Sandreas.hansson@arm.com self.uart.pio = bus.master 2858839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 2868839Sandreas.hansson@arm.com self.timer0.pio = bus.master 2878839Sandreas.hansson@arm.com self.timer1.pio = bus.master 2888839Sandreas.hansson@arm.com self.clcd.pio = bus.master 2898839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 2908839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 2918839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 2928839Sandreas.hansson@arm.com self.cf_ctrl.pio = bus.master 2938839Sandreas.hansson@arm.com self.cf_ctrl.config = bus.master 2948839Sandreas.hansson@arm.com self.cf_ctrl.dma = bus.slave 2958839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 2968839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 2978839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 2988839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 2998839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 3008839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 3018839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 3028839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 3038839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 3048839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 3058839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 3068839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 3078839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 3088839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 3098906Skoansin.tan@gmail.com self.rtc.pio = bus.master 3108839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 31110397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 3127696SAli.Saidi@ARM.com 31310353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 31410353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 31510353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 31610353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 31710353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 31810353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 31910353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 32010353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 32110353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 32210353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 32310353SGeoffrey.Blake@arm.com self.cf_ctrl.clk_domain = clkdomain 32410353SGeoffrey.Blake@arm.com self.dmac_fake.clk_domain = clkdomain 32510353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 32610353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 32710353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 32810353SGeoffrey.Blake@arm.com self.smc_fake.clk_domain = clkdomain 32910353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 33010353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 33110353SGeoffrey.Blake@arm.com self.gpio0_fake.clk_domain = clkdomain 33210353SGeoffrey.Blake@arm.com self.gpio1_fake.clk_domain = clkdomain 33310353SGeoffrey.Blake@arm.com self.gpio2_fake.clk_domain = clkdomain 33410353SGeoffrey.Blake@arm.com self.ssp_fake.clk_domain = clkdomain 33510353SGeoffrey.Blake@arm.com self.sci_fake.clk_domain = clkdomain 33610353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 33710353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 33810353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 33910353SGeoffrey.Blake@arm.com self.flash_fake.clk_domain = clkdomain 34010397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 34110353SGeoffrey.Blake@arm.com 3427754SWilliam.Wang@arm.com# Reference for memory map and interrupt number 3437754SWilliam.Wang@arm.com# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 3447754SWilliam.Wang@arm.com# Chapter 4: Programmer's Reference 3457696SAli.Saidi@ARM.comclass RealViewEB(RealView): 3467696SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x10009000, int_num=44) 34710353SGeoffrey.Blake@arm.com realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500) 3489525SAndreas.Sandberg@ARM.com gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 3497696SAli.Saidi@ARM.com timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 3507696SAli.Saidi@ARM.com timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 3517754SWilliam.Wang@arm.com clcd = Pl111(pio_addr=0x10020000, int_num=23) 3527754SWilliam.Wang@arm.com kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 3537950SAli.Saidi@ARM.com kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 3547696SAli.Saidi@ARM.com 3557696SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 3568461SAli.Saidi@ARM.com flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 3578461SAli.Saidi@ARM.com fake_mem=True) 3587584SAli.Saidi@arm.com dmac_fake = AmbaFake(pio_addr=0x10030000) 3597584SAli.Saidi@arm.com uart1_fake = AmbaFake(pio_addr=0x1000a000) 3607584SAli.Saidi@arm.com uart2_fake = AmbaFake(pio_addr=0x1000b000) 3617584SAli.Saidi@arm.com uart3_fake = AmbaFake(pio_addr=0x1000c000) 3628299Schander.sudanthi@arm.com smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 3637584SAli.Saidi@arm.com smc_fake = AmbaFake(pio_addr=0x100e1000) 3647584SAli.Saidi@arm.com sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 3657584SAli.Saidi@arm.com watchdog_fake = AmbaFake(pio_addr=0x10010000) 3667584SAli.Saidi@arm.com gpio0_fake = AmbaFake(pio_addr=0x10013000) 3677584SAli.Saidi@arm.com gpio1_fake = AmbaFake(pio_addr=0x10014000) 3687584SAli.Saidi@arm.com gpio2_fake = AmbaFake(pio_addr=0x10015000) 3697584SAli.Saidi@arm.com ssp_fake = AmbaFake(pio_addr=0x1000d000) 3707584SAli.Saidi@arm.com sci_fake = AmbaFake(pio_addr=0x1000e000) 3717584SAli.Saidi@arm.com aaci_fake = AmbaFake(pio_addr=0x10004000) 3727584SAli.Saidi@arm.com mmc_fake = AmbaFake(pio_addr=0x10005000) 3737584SAli.Saidi@arm.com rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 37410397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 3757584SAli.Saidi@arm.com 3768713Sandreas.hansson@arm.com # Attach I/O devices that are on chip and also set the appropriate 3778713Sandreas.hansson@arm.com # ranges for the bridge 3788713Sandreas.hansson@arm.com def attachOnChipIO(self, bus, bridge): 3798839Sandreas.hansson@arm.com self.gic.pio = bus.master 3808839Sandreas.hansson@arm.com self.l2x0_fake.pio = bus.master 3818713Sandreas.hansson@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 3828713Sandreas.hansson@arm.com # (gic, l2x0) 3838713Sandreas.hansson@arm.com bridge.ranges = [AddrRange(self.realview_io.pio_addr, 3848713Sandreas.hansson@arm.com self.gic.cpu_addr - 1), 3858713Sandreas.hansson@arm.com AddrRange(self.flash_fake.pio_addr, Addr.max)] 3864104SN/A 38710353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 38810353SGeoffrey.Blake@arm.com # to be "close" to the cores. 38910353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 39010353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 39110353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 39210353SGeoffrey.Blake@arm.com 3933630SN/A # Attach I/O devices to specified bus object. Can't do this 3943630SN/A # earlier, since the bus object itself is typically defined at the 3953630SN/A # System level. 3963630SN/A def attachIO(self, bus): 3978839Sandreas.hansson@arm.com self.uart.pio = bus.master 3988839Sandreas.hansson@arm.com self.realview_io.pio = bus.master 3998839Sandreas.hansson@arm.com self.timer0.pio = bus.master 4008839Sandreas.hansson@arm.com self.timer1.pio = bus.master 4018839Sandreas.hansson@arm.com self.clcd.pio = bus.master 4028839Sandreas.hansson@arm.com self.clcd.dma = bus.slave 4038839Sandreas.hansson@arm.com self.kmi0.pio = bus.master 4048839Sandreas.hansson@arm.com self.kmi1.pio = bus.master 4058839Sandreas.hansson@arm.com self.dmac_fake.pio = bus.master 4068839Sandreas.hansson@arm.com self.uart1_fake.pio = bus.master 4078839Sandreas.hansson@arm.com self.uart2_fake.pio = bus.master 4088839Sandreas.hansson@arm.com self.uart3_fake.pio = bus.master 4098839Sandreas.hansson@arm.com self.smc_fake.pio = bus.master 4108839Sandreas.hansson@arm.com self.sp810_fake.pio = bus.master 4118839Sandreas.hansson@arm.com self.watchdog_fake.pio = bus.master 4128839Sandreas.hansson@arm.com self.gpio0_fake.pio = bus.master 4138839Sandreas.hansson@arm.com self.gpio1_fake.pio = bus.master 4148839Sandreas.hansson@arm.com self.gpio2_fake.pio = bus.master 4158839Sandreas.hansson@arm.com self.ssp_fake.pio = bus.master 4168839Sandreas.hansson@arm.com self.sci_fake.pio = bus.master 4178839Sandreas.hansson@arm.com self.aaci_fake.pio = bus.master 4188839Sandreas.hansson@arm.com self.mmc_fake.pio = bus.master 4198839Sandreas.hansson@arm.com self.rtc_fake.pio = bus.master 4208839Sandreas.hansson@arm.com self.flash_fake.pio = bus.master 4218839Sandreas.hansson@arm.com self.smcreg_fake.pio = bus.master 42210397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 4237584SAli.Saidi@arm.com 42410353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 42510353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 42610353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 42710353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 42810353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 42910353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 43010353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 43110353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 43210353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 43310353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 43410353SGeoffrey.Blake@arm.com self.dmac_fake.clk_domain = clkdomain 43510353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 43610353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 43710353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 43810353SGeoffrey.Blake@arm.com self.smc_fake.clk_domain = clkdomain 43910353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 44010353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 44110353SGeoffrey.Blake@arm.com self.gpio0_fake.clk_domain = clkdomain 44210353SGeoffrey.Blake@arm.com self.gpio1_fake.clk_domain = clkdomain 44310353SGeoffrey.Blake@arm.com self.gpio2_fake.clk_domain = clkdomain 44410353SGeoffrey.Blake@arm.com self.ssp_fake.clk_domain = clkdomain 44510353SGeoffrey.Blake@arm.com self.sci_fake.clk_domain = clkdomain 44610353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 44710353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 44810353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 44910353SGeoffrey.Blake@arm.com self.flash_fake.clk_domain = clkdomain 45010353SGeoffrey.Blake@arm.com self.smcreg_fake.clk_domain = clkdomain 45110397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 45210353SGeoffrey.Blake@arm.com 4538870SAli.Saidi@ARM.comclass VExpress_EMM(RealView): 45410358SAli.Saidi@ARM.com _mem_regions = [(Addr('2GB'), Addr('2GB'))] 4559052Sgeoffrey.blake@arm.com pci_cfg_base = 0x30000000 4568870SAli.Saidi@ARM.com uart = Pl011(pio_addr=0x1c090000, int_num=37) 45710353SGeoffrey.Blake@arm.com realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, \ 45810353SGeoffrey.Blake@arm.com idreg=0x02250000, pio_addr=0x1C010000) 4599525SAndreas.Sandberg@ARM.com gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 4608870SAli.Saidi@ARM.com local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 46110845Sandreas.sandberg@arm.com generic_timer = GenericTimer(int_phys=29, int_virt=27) 4629185SAli.Saidi@ARM.com timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 4639185SAli.Saidi@ARM.com timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 4648870SAli.Saidi@ARM.com clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 4659646SChris.Emmons@arm.com hdlcd = HDLcd(pio_addr=0x2b000000, int_num=117) 4668870SAli.Saidi@ARM.com kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 4679387SChris.Emmons@arm.com kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 46810037SARM gem5 Developers vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 4698870SAli.Saidi@ARM.com cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 4708870SAli.Saidi@ARM.com io_shift = 2, ctrl_offset = 2, Command = 0x1, 4718870SAli.Saidi@ARM.com BAR0 = 0x1C1A0000, BAR0Size = '256B', 4728870SAli.Saidi@ARM.com BAR1 = 0x1C1A0100, BAR1Size = '4096B', 4738870SAli.Saidi@ARM.com BAR0LegacyIO = True, BAR1LegacyIO = True) 4749052Sgeoffrey.blake@arm.com 4759052Sgeoffrey.blake@arm.com pciconfig = PciConfigAll(size='256MB') 4769835Sandreas.hansson@arm.com vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 4779835Sandreas.hansson@arm.com conf_table_reported = False) 4788870SAli.Saidi@ARM.com rtc = PL031(pio_addr=0x1C170000, int_num=36) 4798870SAli.Saidi@ARM.com 4808870SAli.Saidi@ARM.com l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 4818870SAli.Saidi@ARM.com uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 4828870SAli.Saidi@ARM.com uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 4838870SAli.Saidi@ARM.com uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 4848870SAli.Saidi@ARM.com sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 4858870SAli.Saidi@ARM.com watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 4868870SAli.Saidi@ARM.com aaci_fake = AmbaFake(pio_addr=0x1C040000) 4878870SAli.Saidi@ARM.com lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 4888870SAli.Saidi@ARM.com usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 4898870SAli.Saidi@ARM.com mmc_fake = AmbaFake(pio_addr=0x1c050000) 49010397Sstephan.diestelhorst@arm.com energy_ctrl = EnergyCtrl(pio_addr=0x1c080000) 4918870SAli.Saidi@ARM.com 49210353SGeoffrey.Blake@arm.com # Attach any PCI devices that are supported 49310353SGeoffrey.Blake@arm.com def attachPciDevices(self): 49410353SGeoffrey.Blake@arm.com self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 49510353SGeoffrey.Blake@arm.com InterruptLine=1, InterruptPin=1) 49610353SGeoffrey.Blake@arm.com self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 49710353SGeoffrey.Blake@arm.com InterruptLine=2, InterruptPin=2) 49810353SGeoffrey.Blake@arm.com 49910353SGeoffrey.Blake@arm.com def enableMSIX(self): 50010353SGeoffrey.Blake@arm.com self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512) 50110353SGeoffrey.Blake@arm.com self.gicv2m = Gicv2m() 50210353SGeoffrey.Blake@arm.com self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 50310353SGeoffrey.Blake@arm.com 5048870SAli.Saidi@ARM.com def setupBootLoader(self, mem_bus, cur_sys, loc): 5059835Sandreas.hansson@arm.com self.nvmem = SimpleMemory(range = AddrRange('64MB'), 5069835Sandreas.hansson@arm.com conf_table_reported = False) 5078870SAli.Saidi@ARM.com self.nvmem.port = mem_bus.master 5088870SAli.Saidi@ARM.com cur_sys.boot_loader = loc('boot_emm.arm') 50910037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 51010037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 51110037SARM gem5 Developers cur_sys.load_offset = 0x80000000 5128870SAli.Saidi@ARM.com 5138870SAli.Saidi@ARM.com # Attach I/O devices that are on chip and also set the appropriate 5148870SAli.Saidi@ARM.com # ranges for the bridge 51510780SCurtis.Dunham@arm.com def attachOnChipIO(self, bus, bridge=None): 51610780SCurtis.Dunham@arm.com self.gic.pio = bus.master 51710780SCurtis.Dunham@arm.com self.vgic.pio = bus.master 51810780SCurtis.Dunham@arm.com self.local_cpu_timer.pio = bus.master 51910780SCurtis.Dunham@arm.com if hasattr(self, "gicv2m"): 52010780SCurtis.Dunham@arm.com self.gicv2m.pio = bus.master 52110780SCurtis.Dunham@arm.com self.hdlcd.dma = bus.slave 52210780SCurtis.Dunham@arm.com if bridge: 52310780SCurtis.Dunham@arm.com # Bridge ranges based on excluding what is part of on-chip I/O 52410780SCurtis.Dunham@arm.com # (gic, a9scu) 52510780SCurtis.Dunham@arm.com bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 52610780SCurtis.Dunham@arm.com AddrRange(0x2B000000, size='4MB'), 52710780SCurtis.Dunham@arm.com AddrRange(0x30000000, size='256MB'), 52810780SCurtis.Dunham@arm.com AddrRange(0x40000000, size='512MB'), 52910780SCurtis.Dunham@arm.com AddrRange(0x18000000, size='64MB'), 53010780SCurtis.Dunham@arm.com AddrRange(0x1C000000, size='64MB')] 53110037SARM gem5 Developers 5328870SAli.Saidi@ARM.com 53310353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 53410353SGeoffrey.Blake@arm.com # to be "close" to the cores. 53510353SGeoffrey.Blake@arm.com def onChipIOClkDomain(self, clkdomain): 53610353SGeoffrey.Blake@arm.com self.gic.clk_domain = clkdomain 53710353SGeoffrey.Blake@arm.com if hasattr(self, "gicv2m"): 53810353SGeoffrey.Blake@arm.com self.gicv2m.clk_domain = clkdomain 53910353SGeoffrey.Blake@arm.com self.hdlcd.clk_domain = clkdomain 54010353SGeoffrey.Blake@arm.com self.vgic.clk_domain = clkdomain 54110353SGeoffrey.Blake@arm.com 54210353SGeoffrey.Blake@arm.com # Attach I/O devices to specified bus object. Done here 54310353SGeoffrey.Blake@arm.com # as the specified bus to connect to may not always be fixed. 5448870SAli.Saidi@ARM.com def attachIO(self, bus): 5458870SAli.Saidi@ARM.com self.uart.pio = bus.master 5468870SAli.Saidi@ARM.com self.realview_io.pio = bus.master 5478870SAli.Saidi@ARM.com self.timer0.pio = bus.master 5488870SAli.Saidi@ARM.com self.timer1.pio = bus.master 5498870SAli.Saidi@ARM.com self.clcd.pio = bus.master 5508870SAli.Saidi@ARM.com self.clcd.dma = bus.slave 5519646SChris.Emmons@arm.com self.hdlcd.pio = bus.master 5528870SAli.Saidi@ARM.com self.kmi0.pio = bus.master 5538870SAli.Saidi@ARM.com self.kmi1.pio = bus.master 5548870SAli.Saidi@ARM.com self.cf_ctrl.pio = bus.master 5558872Ssaidi@eecs.umich.edu self.cf_ctrl.dma = bus.slave 5568870SAli.Saidi@ARM.com self.cf_ctrl.config = bus.master 5578870SAli.Saidi@ARM.com self.rtc.pio = bus.master 5588870SAli.Saidi@ARM.com bus.use_default_range = True 5598870SAli.Saidi@ARM.com self.vram.port = bus.master 5609052Sgeoffrey.blake@arm.com self.pciconfig.pio = bus.default 5618870SAli.Saidi@ARM.com 5628870SAli.Saidi@ARM.com self.l2x0_fake.pio = bus.master 5638870SAli.Saidi@ARM.com self.uart1_fake.pio = bus.master 5648870SAli.Saidi@ARM.com self.uart2_fake.pio = bus.master 5658870SAli.Saidi@ARM.com self.uart3_fake.pio = bus.master 5668870SAli.Saidi@ARM.com self.sp810_fake.pio = bus.master 5678870SAli.Saidi@ARM.com self.watchdog_fake.pio = bus.master 5688870SAli.Saidi@ARM.com self.aaci_fake.pio = bus.master 5698870SAli.Saidi@ARM.com self.lan_fake.pio = bus.master 5708870SAli.Saidi@ARM.com self.usb_fake.pio = bus.master 5718870SAli.Saidi@ARM.com self.mmc_fake.pio = bus.master 57210397Sstephan.diestelhorst@arm.com self.energy_ctrl.pio = bus.master 5738870SAli.Saidi@ARM.com 57410353SGeoffrey.Blake@arm.com # Try to attach the I/O if it exists 57510353SGeoffrey.Blake@arm.com try: 57610353SGeoffrey.Blake@arm.com self.ide.pio = bus.master 57710353SGeoffrey.Blake@arm.com self.ide.config = bus.master 57810353SGeoffrey.Blake@arm.com self.ide.dma = bus.slave 57910353SGeoffrey.Blake@arm.com self.ethernet.pio = bus.master 58010353SGeoffrey.Blake@arm.com self.ethernet.config = bus.master 58110353SGeoffrey.Blake@arm.com self.ethernet.dma = bus.slave 58210353SGeoffrey.Blake@arm.com except: 58310353SGeoffrey.Blake@arm.com pass 58410353SGeoffrey.Blake@arm.com 58510353SGeoffrey.Blake@arm.com # Set the clock domain for IO objects that are considered 58610353SGeoffrey.Blake@arm.com # to be "far" away from the cores. 58710353SGeoffrey.Blake@arm.com def offChipIOClkDomain(self, clkdomain): 58810353SGeoffrey.Blake@arm.com self.uart.clk_domain = clkdomain 58910353SGeoffrey.Blake@arm.com self.realview_io.clk_domain = clkdomain 59010353SGeoffrey.Blake@arm.com self.timer0.clk_domain = clkdomain 59110353SGeoffrey.Blake@arm.com self.timer1.clk_domain = clkdomain 59210353SGeoffrey.Blake@arm.com self.clcd.clk_domain = clkdomain 59310353SGeoffrey.Blake@arm.com self.kmi0.clk_domain = clkdomain 59410353SGeoffrey.Blake@arm.com self.kmi1.clk_domain = clkdomain 59510353SGeoffrey.Blake@arm.com self.cf_ctrl.clk_domain = clkdomain 59610353SGeoffrey.Blake@arm.com self.rtc.clk_domain = clkdomain 59710353SGeoffrey.Blake@arm.com self.vram.clk_domain = clkdomain 59810353SGeoffrey.Blake@arm.com self.pciconfig.clk_domain = clkdomain 59910353SGeoffrey.Blake@arm.com 60010353SGeoffrey.Blake@arm.com self.l2x0_fake.clk_domain = clkdomain 60110353SGeoffrey.Blake@arm.com self.uart1_fake.clk_domain = clkdomain 60210353SGeoffrey.Blake@arm.com self.uart2_fake.clk_domain = clkdomain 60310353SGeoffrey.Blake@arm.com self.uart3_fake.clk_domain = clkdomain 60410353SGeoffrey.Blake@arm.com self.sp810_fake.clk_domain = clkdomain 60510353SGeoffrey.Blake@arm.com self.watchdog_fake.clk_domain = clkdomain 60610353SGeoffrey.Blake@arm.com self.aaci_fake.clk_domain = clkdomain 60710353SGeoffrey.Blake@arm.com self.lan_fake.clk_domain = clkdomain 60810353SGeoffrey.Blake@arm.com self.usb_fake.clk_domain = clkdomain 60910353SGeoffrey.Blake@arm.com self.mmc_fake.clk_domain = clkdomain 61010397Sstephan.diestelhorst@arm.com self.energy_ctrl.clk_domain = clkdomain 61110353SGeoffrey.Blake@arm.com 61210037SARM gem5 Developersclass VExpress_EMM64(VExpress_EMM): 61310356SAli.Saidi@ARM.com pci_io_base = 0x2f000000 61410356SAli.Saidi@ARM.com pci_cfg_gen_offsets = True 61510358SAli.Saidi@ARM.com # Three memory regions are specified totalling 512GB 61610358SAli.Saidi@ARM.com _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 61710358SAli.Saidi@ARM.com (Addr('512GB'), Addr('480GB'))] 61810037SARM gem5 Developers def setupBootLoader(self, mem_bus, cur_sys, loc): 61910037SARM gem5 Developers self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) 62010037SARM gem5 Developers self.nvmem.port = mem_bus.master 62110037SARM gem5 Developers cur_sys.boot_loader = loc('boot_emm.arm64') 62210037SARM gem5 Developers cur_sys.atags_addr = 0x8000000 62310037SARM gem5 Developers cur_sys.load_addr_mask = 0xfffffff 62410037SARM gem5 Developers cur_sys.load_offset = 0x80000000 62510037SARM gem5 Developers 62610037SARM gem5 Developers 627