RealView.py revision 10845
1# Copyright (c) 2009-2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ali Saidi 40# Gabe Black 41# William Wang 42 43from m5.params import * 44from m5.proxy import * 45from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice 46from Pci import PciConfigAll 47from Ethernet import NSGigE, IGbE_igb, IGbE_e1000 48from Ide import * 49from Platform import Platform 50from Terminal import Terminal 51from Uart import Uart 52from SimpleMemory import SimpleMemory 53from Gic import * 54from EnergyCtrl import EnergyCtrl 55 56class AmbaPioDevice(BasicPioDevice): 57 type = 'AmbaPioDevice' 58 abstract = True 59 cxx_header = "dev/arm/amba_device.hh" 60 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 61 62class AmbaIntDevice(AmbaPioDevice): 63 type = 'AmbaIntDevice' 64 abstract = True 65 cxx_header = "dev/arm/amba_device.hh" 66 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 67 int_num = Param.UInt32("Interrupt number that connects to GIC") 68 int_delay = Param.Latency("100ns", 69 "Time between action and interrupt generation by device") 70 71class AmbaDmaDevice(DmaDevice): 72 type = 'AmbaDmaDevice' 73 abstract = True 74 cxx_header = "dev/arm/amba_device.hh" 75 pio_addr = Param.Addr("Address for AMBA slave interface") 76 pio_latency = Param.Latency("10ns", "Time between action and write/read result by AMBA DMA Device") 77 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 78 int_num = Param.UInt32("Interrupt number that connects to GIC") 79 amba_id = Param.UInt32("ID of AMBA device for kernel detection") 80 81class A9SCU(BasicPioDevice): 82 type = 'A9SCU' 83 cxx_header = "dev/arm/a9scu.hh" 84 85class RealViewCtrl(BasicPioDevice): 86 type = 'RealViewCtrl' 87 cxx_header = "dev/arm/rv_ctrl.hh" 88 proc_id0 = Param.UInt32(0x0C000000, "Processor ID, SYS_PROCID") 89 proc_id1 = Param.UInt32(0x0C000222, "Processor ID, SYS_PROCID1") 90 idreg = Param.UInt32(0x00000000, "ID Register, SYS_ID") 91 92class VGic(PioDevice): 93 type = 'VGic' 94 cxx_header = "dev/arm/vgic.hh" 95 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 96 platform = Param.Platform(Parent.any, "Platform this device is part of.") 97 vcpu_addr = Param.Addr(0, "Address for vcpu interfaces") 98 hv_addr = Param.Addr(0, "Address for hv control") 99 pio_delay = Param.Latency('10ns', "Delay for PIO r/w") 100 # The number of list registers is not currently configurable at runtime. 101 ppint = Param.UInt32("HV maintenance interrupt number") 102 103class AmbaFake(AmbaPioDevice): 104 type = 'AmbaFake' 105 cxx_header = "dev/arm/amba_fake.hh" 106 ignore_access = Param.Bool(False, "Ignore reads/writes to this device, (e.g. IsaFake + AMBA)") 107 amba_id = 0; 108 109class Pl011(Uart): 110 type = 'Pl011' 111 cxx_header = "dev/arm/pl011.hh" 112 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 113 int_num = Param.UInt32("Interrupt number that connects to GIC") 114 end_on_eot = Param.Bool(False, "End the simulation when a EOT is received on the UART") 115 int_delay = Param.Latency("100ns", "Time between action and interrupt generation by UART") 116 117class Sp804(AmbaPioDevice): 118 type = 'Sp804' 119 cxx_header = "dev/arm/timer_sp804.hh" 120 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 121 int_num0 = Param.UInt32("Interrupt number that connects to GIC") 122 clock0 = Param.Clock('1MHz', "Clock speed of the input") 123 int_num1 = Param.UInt32("Interrupt number that connects to GIC") 124 clock1 = Param.Clock('1MHz', "Clock speed of the input") 125 amba_id = 0x00141804 126 127class CpuLocalTimer(BasicPioDevice): 128 type = 'CpuLocalTimer' 129 cxx_header = "dev/arm/timer_cpulocal.hh" 130 gic = Param.BaseGic(Parent.any, "Gic to use for interrupting") 131 int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC") 132 int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC") 133 134class GenericTimer(SimObject): 135 type = 'GenericTimer' 136 cxx_header = "dev/arm/generic_timer.hh" 137 system = Param.System(Parent.any, "system") 138 gic = Param.BaseGic(Parent.any, "GIC to use for interrupting") 139 # @todo: for now only two timers per CPU is supported, which is the 140 # normal behaviour when security extensions are disabled. 141 int_phys = Param.UInt32("Physical timer interrupt number") 142 int_virt = Param.UInt32("Virtual timer interrupt number") 143 144class PL031(AmbaIntDevice): 145 type = 'PL031' 146 cxx_header = "dev/arm/rtc_pl031.hh" 147 time = Param.Time('01/01/2009', "System time to use ('Now' for actual time)") 148 amba_id = 0x00341031 149 150class Pl050(AmbaIntDevice): 151 type = 'Pl050' 152 cxx_header = "dev/arm/kmi.hh" 153 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 154 is_mouse = Param.Bool(False, "Is this interface a mouse, if not a keyboard") 155 int_delay = '1us' 156 amba_id = 0x00141050 157 158class Pl111(AmbaDmaDevice): 159 type = 'Pl111' 160 cxx_header = "dev/arm/pl111.hh" 161 pixel_clock = Param.Clock('24MHz', "Pixel clock") 162 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer display") 163 amba_id = 0x00141111 164 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 165 166 167class HDLcd(AmbaDmaDevice): 168 type = 'HDLcd' 169 cxx_header = "dev/arm/hdlcd.hh" 170 # For reference, 1024x768MR-16@60 ~= 56 MHz 171 # 1920x1080MR-16@60 ~= 137 MHz 172 # 3840x2160MR-16@60 ~= 533 MHz 173 # Match against the resolution selected in the Linux DTS/DTB file. 174 pixel_clock = Param.Clock('137MHz', "Clock frequency of the pixel clock " 175 "(i.e. PXLREFCLK / OSCCLK 5") 176 vnc = Param.VncInput(Parent.any, "Vnc server for remote frame buffer " 177 "display") 178 amba_id = 0x00141000 179 workaround_swap_rb = Param.Bool(True, "Workaround incorrect color " 180 "selector order in some kernels") 181 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp") 182 183class RealView(Platform): 184 type = 'RealView' 185 cxx_header = "dev/arm/realview.hh" 186 system = Param.System(Parent.any, "system") 187 pci_io_base = Param.Addr(0, "Base address of PCI IO Space") 188 pci_cfg_base = Param.Addr(0, "Base address of PCI Configuraiton Space") 189 pci_cfg_gen_offsets = Param.Bool(False, "Should the offsets used for PCI cfg access" 190 " be compatible with the pci-generic-host or the legacy host bridge?") 191 _mem_regions = [(Addr(0), Addr('256MB'))] 192 193 def attachPciDevices(self): 194 pass 195 196 def enableMSIX(self): 197 pass 198 199 def onChipIOClkDomain(self, clkdomain): 200 pass 201 202 def offChipIOClkDomain(self, clkdomain): 203 pass 204 205 def setupBootLoader(self, mem_bus, cur_sys, loc): 206 self.nvmem = SimpleMemory(range = AddrRange('2GB', size = '64MB'), 207 conf_table_reported = False) 208 self.nvmem.port = mem_bus.master 209 cur_sys.boot_loader = loc('boot.arm') 210 cur_sys.atags_addr = 0x100 211 cur_sys.load_addr_mask = 0xfffffff 212 cur_sys.load_offset = 0 213 214 215# Reference for memory map and interrupt number 216# RealView Platform Baseboard Explore for Cortex-A9 User Guide(ARM DUI 0440A) 217# Chapter 4: Programmer's Reference 218class RealViewPBX(RealView): 219 uart = Pl011(pio_addr=0x10009000, int_num=44) 220 realview_io = RealViewCtrl(pio_addr=0x10000000) 221 gic = Pl390() 222 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 223 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 224 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x1f000600) 225 clcd = Pl111(pio_addr=0x10020000, int_num=55) 226 kmi0 = Pl050(pio_addr=0x10006000, int_num=52) 227 kmi1 = Pl050(pio_addr=0x10007000, int_num=53, is_mouse=True) 228 a9scu = A9SCU(pio_addr=0x1f000000) 229 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=7, pci_bus=2, 230 io_shift = 1, ctrl_offset = 2, Command = 0x1, 231 BAR0 = 0x18000000, BAR0Size = '16B', 232 BAR1 = 0x18000100, BAR1Size = '1B', 233 BAR0LegacyIO = True, BAR1LegacyIO = True) 234 235 236 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff) 237 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000, 238 fake_mem=True) 239 dmac_fake = AmbaFake(pio_addr=0x10030000) 240 uart1_fake = AmbaFake(pio_addr=0x1000a000) 241 uart2_fake = AmbaFake(pio_addr=0x1000b000) 242 uart3_fake = AmbaFake(pio_addr=0x1000c000) 243 smc_fake = AmbaFake(pio_addr=0x100e1000) 244 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 245 watchdog_fake = AmbaFake(pio_addr=0x10010000) 246 gpio0_fake = AmbaFake(pio_addr=0x10013000) 247 gpio1_fake = AmbaFake(pio_addr=0x10014000) 248 gpio2_fake = AmbaFake(pio_addr=0x10015000) 249 ssp_fake = AmbaFake(pio_addr=0x1000d000) 250 sci_fake = AmbaFake(pio_addr=0x1000e000) 251 aaci_fake = AmbaFake(pio_addr=0x10004000) 252 mmc_fake = AmbaFake(pio_addr=0x10005000) 253 rtc = PL031(pio_addr=0x10017000, int_num=42) 254 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 255 256 257 # Attach I/O devices that are on chip and also set the appropriate 258 # ranges for the bridge 259 def attachOnChipIO(self, bus, bridge): 260 self.gic.pio = bus.master 261 self.l2x0_fake.pio = bus.master 262 self.a9scu.pio = bus.master 263 self.local_cpu_timer.pio = bus.master 264 # Bridge ranges based on excluding what is part of on-chip I/O 265 # (gic, l2x0, a9scu, local_cpu_timer) 266 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 267 self.a9scu.pio_addr - 1), 268 AddrRange(self.flash_fake.pio_addr, 269 self.flash_fake.pio_addr + \ 270 self.flash_fake.pio_size - 1)] 271 272 # Set the clock domain for IO objects that are considered 273 # to be "close" to the cores. 274 def onChipIOClkDomain(self, clkdomain): 275 self.gic.clk_domain = clkdomain 276 self.l2x0_fake.clk_domain = clkdomain 277 self.a9scu.clkdomain = clkdomain 278 self.local_cpu_timer.clk_domain = clkdomain 279 280 # Attach I/O devices to specified bus object. Can't do this 281 # earlier, since the bus object itself is typically defined at the 282 # System level. 283 def attachIO(self, bus): 284 self.uart.pio = bus.master 285 self.realview_io.pio = bus.master 286 self.timer0.pio = bus.master 287 self.timer1.pio = bus.master 288 self.clcd.pio = bus.master 289 self.clcd.dma = bus.slave 290 self.kmi0.pio = bus.master 291 self.kmi1.pio = bus.master 292 self.cf_ctrl.pio = bus.master 293 self.cf_ctrl.config = bus.master 294 self.cf_ctrl.dma = bus.slave 295 self.dmac_fake.pio = bus.master 296 self.uart1_fake.pio = bus.master 297 self.uart2_fake.pio = bus.master 298 self.uart3_fake.pio = bus.master 299 self.smc_fake.pio = bus.master 300 self.sp810_fake.pio = bus.master 301 self.watchdog_fake.pio = bus.master 302 self.gpio0_fake.pio = bus.master 303 self.gpio1_fake.pio = bus.master 304 self.gpio2_fake.pio = bus.master 305 self.ssp_fake.pio = bus.master 306 self.sci_fake.pio = bus.master 307 self.aaci_fake.pio = bus.master 308 self.mmc_fake.pio = bus.master 309 self.rtc.pio = bus.master 310 self.flash_fake.pio = bus.master 311 self.energy_ctrl.pio = bus.master 312 313 # Set the clock domain for IO objects that are considered 314 # to be "far" away from the cores. 315 def offChipIOClkDomain(self, clkdomain): 316 self.uart.clk_domain = clkdomain 317 self.realview_io.clk_domain = clkdomain 318 self.timer0.clk_domain = clkdomain 319 self.timer1.clk_domain = clkdomain 320 self.clcd.clk_domain = clkdomain 321 self.kmi0.clk_domain = clkdomain 322 self.kmi1.clk_domain = clkdomain 323 self.cf_ctrl.clk_domain = clkdomain 324 self.dmac_fake.clk_domain = clkdomain 325 self.uart1_fake.clk_domain = clkdomain 326 self.uart2_fake.clk_domain = clkdomain 327 self.uart3_fake.clk_domain = clkdomain 328 self.smc_fake.clk_domain = clkdomain 329 self.sp810_fake.clk_domain = clkdomain 330 self.watchdog_fake.clk_domain = clkdomain 331 self.gpio0_fake.clk_domain = clkdomain 332 self.gpio1_fake.clk_domain = clkdomain 333 self.gpio2_fake.clk_domain = clkdomain 334 self.ssp_fake.clk_domain = clkdomain 335 self.sci_fake.clk_domain = clkdomain 336 self.aaci_fake.clk_domain = clkdomain 337 self.mmc_fake.clk_domain = clkdomain 338 self.rtc.clk_domain = clkdomain 339 self.flash_fake.clk_domain = clkdomain 340 self.energy_ctrl.clk_domain = clkdomain 341 342# Reference for memory map and interrupt number 343# RealView Emulation Baseboard User Guide (ARM DUI 0143B) 344# Chapter 4: Programmer's Reference 345class RealViewEB(RealView): 346 uart = Pl011(pio_addr=0x10009000, int_num=44) 347 realview_io = RealViewCtrl(pio_addr=0x10000000, idreg=0x01400500) 348 gic = Pl390(dist_addr=0x10041000, cpu_addr=0x10040000) 349 timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000) 350 timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000) 351 clcd = Pl111(pio_addr=0x10020000, int_num=23) 352 kmi0 = Pl050(pio_addr=0x10006000, int_num=20) 353 kmi1 = Pl050(pio_addr=0x10007000, int_num=21, is_mouse=True) 354 355 l2x0_fake = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1") 356 flash_fake = IsaFake(pio_addr=0x40000000, pio_size=0x20000000-1, 357 fake_mem=True) 358 dmac_fake = AmbaFake(pio_addr=0x10030000) 359 uart1_fake = AmbaFake(pio_addr=0x1000a000) 360 uart2_fake = AmbaFake(pio_addr=0x1000b000) 361 uart3_fake = AmbaFake(pio_addr=0x1000c000) 362 smcreg_fake = IsaFake(pio_addr=0x10080000, pio_size=0x10000-1) 363 smc_fake = AmbaFake(pio_addr=0x100e1000) 364 sp810_fake = AmbaFake(pio_addr=0x10001000, ignore_access=True) 365 watchdog_fake = AmbaFake(pio_addr=0x10010000) 366 gpio0_fake = AmbaFake(pio_addr=0x10013000) 367 gpio1_fake = AmbaFake(pio_addr=0x10014000) 368 gpio2_fake = AmbaFake(pio_addr=0x10015000) 369 ssp_fake = AmbaFake(pio_addr=0x1000d000) 370 sci_fake = AmbaFake(pio_addr=0x1000e000) 371 aaci_fake = AmbaFake(pio_addr=0x10004000) 372 mmc_fake = AmbaFake(pio_addr=0x10005000) 373 rtc_fake = AmbaFake(pio_addr=0x10017000, amba_id=0x41031) 374 energy_ctrl = EnergyCtrl(pio_addr=0x1000f000) 375 376 # Attach I/O devices that are on chip and also set the appropriate 377 # ranges for the bridge 378 def attachOnChipIO(self, bus, bridge): 379 self.gic.pio = bus.master 380 self.l2x0_fake.pio = bus.master 381 # Bridge ranges based on excluding what is part of on-chip I/O 382 # (gic, l2x0) 383 bridge.ranges = [AddrRange(self.realview_io.pio_addr, 384 self.gic.cpu_addr - 1), 385 AddrRange(self.flash_fake.pio_addr, Addr.max)] 386 387 # Set the clock domain for IO objects that are considered 388 # to be "close" to the cores. 389 def onChipIOClkDomain(self, clkdomain): 390 self.gic.clk_domain = clkdomain 391 self.l2x0_fake.clk_domain = clkdomain 392 393 # Attach I/O devices to specified bus object. Can't do this 394 # earlier, since the bus object itself is typically defined at the 395 # System level. 396 def attachIO(self, bus): 397 self.uart.pio = bus.master 398 self.realview_io.pio = bus.master 399 self.timer0.pio = bus.master 400 self.timer1.pio = bus.master 401 self.clcd.pio = bus.master 402 self.clcd.dma = bus.slave 403 self.kmi0.pio = bus.master 404 self.kmi1.pio = bus.master 405 self.dmac_fake.pio = bus.master 406 self.uart1_fake.pio = bus.master 407 self.uart2_fake.pio = bus.master 408 self.uart3_fake.pio = bus.master 409 self.smc_fake.pio = bus.master 410 self.sp810_fake.pio = bus.master 411 self.watchdog_fake.pio = bus.master 412 self.gpio0_fake.pio = bus.master 413 self.gpio1_fake.pio = bus.master 414 self.gpio2_fake.pio = bus.master 415 self.ssp_fake.pio = bus.master 416 self.sci_fake.pio = bus.master 417 self.aaci_fake.pio = bus.master 418 self.mmc_fake.pio = bus.master 419 self.rtc_fake.pio = bus.master 420 self.flash_fake.pio = bus.master 421 self.smcreg_fake.pio = bus.master 422 self.energy_ctrl.pio = bus.master 423 424 # Set the clock domain for IO objects that are considered 425 # to be "far" away from the cores. 426 def offChipIOClkDomain(self, clkdomain): 427 self.uart.clk_domain = clkdomain 428 self.realview_io.clk_domain = clkdomain 429 self.timer0.clk_domain = clkdomain 430 self.timer1.clk_domain = clkdomain 431 self.clcd.clk_domain = clkdomain 432 self.kmi0.clk_domain = clkdomain 433 self.kmi1.clk_domain = clkdomain 434 self.dmac_fake.clk_domain = clkdomain 435 self.uart1_fake.clk_domain = clkdomain 436 self.uart2_fake.clk_domain = clkdomain 437 self.uart3_fake.clk_domain = clkdomain 438 self.smc_fake.clk_domain = clkdomain 439 self.sp810_fake.clk_domain = clkdomain 440 self.watchdog_fake.clk_domain = clkdomain 441 self.gpio0_fake.clk_domain = clkdomain 442 self.gpio1_fake.clk_domain = clkdomain 443 self.gpio2_fake.clk_domain = clkdomain 444 self.ssp_fake.clk_domain = clkdomain 445 self.sci_fake.clk_domain = clkdomain 446 self.aaci_fake.clk_domain = clkdomain 447 self.mmc_fake.clk_domain = clkdomain 448 self.rtc.clk_domain = clkdomain 449 self.flash_fake.clk_domain = clkdomain 450 self.smcreg_fake.clk_domain = clkdomain 451 self.energy_ctrl.clk_domain = clkdomain 452 453class VExpress_EMM(RealView): 454 _mem_regions = [(Addr('2GB'), Addr('2GB'))] 455 pci_cfg_base = 0x30000000 456 uart = Pl011(pio_addr=0x1c090000, int_num=37) 457 realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, \ 458 idreg=0x02250000, pio_addr=0x1C010000) 459 gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000) 460 local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0x2C080000) 461 generic_timer = GenericTimer(int_phys=29, int_virt=27) 462 timer0 = Sp804(int_num0=34, int_num1=34, pio_addr=0x1C110000, clock0='1MHz', clock1='1MHz') 463 timer1 = Sp804(int_num0=35, int_num1=35, pio_addr=0x1C120000, clock0='1MHz', clock1='1MHz') 464 clcd = Pl111(pio_addr=0x1c1f0000, int_num=46) 465 hdlcd = HDLcd(pio_addr=0x2b000000, int_num=117) 466 kmi0 = Pl050(pio_addr=0x1c060000, int_num=44) 467 kmi1 = Pl050(pio_addr=0x1c070000, int_num=45, is_mouse=True) 468 vgic = VGic(vcpu_addr=0x2c006000, hv_addr=0x2c004000, ppint=25) 469 cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2, 470 io_shift = 2, ctrl_offset = 2, Command = 0x1, 471 BAR0 = 0x1C1A0000, BAR0Size = '256B', 472 BAR1 = 0x1C1A0100, BAR1Size = '4096B', 473 BAR0LegacyIO = True, BAR1LegacyIO = True) 474 475 pciconfig = PciConfigAll(size='256MB') 476 vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'), 477 conf_table_reported = False) 478 rtc = PL031(pio_addr=0x1C170000, int_num=36) 479 480 l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff) 481 uart1_fake = AmbaFake(pio_addr=0x1C0A0000) 482 uart2_fake = AmbaFake(pio_addr=0x1C0B0000) 483 uart3_fake = AmbaFake(pio_addr=0x1C0C0000) 484 sp810_fake = AmbaFake(pio_addr=0x1C020000, ignore_access=True) 485 watchdog_fake = AmbaFake(pio_addr=0x1C0F0000) 486 aaci_fake = AmbaFake(pio_addr=0x1C040000) 487 lan_fake = IsaFake(pio_addr=0x1A000000, pio_size=0xffff) 488 usb_fake = IsaFake(pio_addr=0x1B000000, pio_size=0x1ffff) 489 mmc_fake = AmbaFake(pio_addr=0x1c050000) 490 energy_ctrl = EnergyCtrl(pio_addr=0x1c080000) 491 492 # Attach any PCI devices that are supported 493 def attachPciDevices(self): 494 self.ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0, 495 InterruptLine=1, InterruptPin=1) 496 self.ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0, 497 InterruptLine=2, InterruptPin=2) 498 499 def enableMSIX(self): 500 self.gic = Pl390(dist_addr=0x2C001000, cpu_addr=0x2C002000, it_lines=512) 501 self.gicv2m = Gicv2m() 502 self.gicv2m.frames = [Gicv2mFrame(spi_base=256, spi_len=64, addr=0x2C1C0000)] 503 504 def setupBootLoader(self, mem_bus, cur_sys, loc): 505 self.nvmem = SimpleMemory(range = AddrRange('64MB'), 506 conf_table_reported = False) 507 self.nvmem.port = mem_bus.master 508 cur_sys.boot_loader = loc('boot_emm.arm') 509 cur_sys.atags_addr = 0x8000000 510 cur_sys.load_addr_mask = 0xfffffff 511 cur_sys.load_offset = 0x80000000 512 513 # Attach I/O devices that are on chip and also set the appropriate 514 # ranges for the bridge 515 def attachOnChipIO(self, bus, bridge=None): 516 self.gic.pio = bus.master 517 self.vgic.pio = bus.master 518 self.local_cpu_timer.pio = bus.master 519 if hasattr(self, "gicv2m"): 520 self.gicv2m.pio = bus.master 521 self.hdlcd.dma = bus.slave 522 if bridge: 523 # Bridge ranges based on excluding what is part of on-chip I/O 524 # (gic, a9scu) 525 bridge.ranges = [AddrRange(0x2F000000, size='16MB'), 526 AddrRange(0x2B000000, size='4MB'), 527 AddrRange(0x30000000, size='256MB'), 528 AddrRange(0x40000000, size='512MB'), 529 AddrRange(0x18000000, size='64MB'), 530 AddrRange(0x1C000000, size='64MB')] 531 532 533 # Set the clock domain for IO objects that are considered 534 # to be "close" to the cores. 535 def onChipIOClkDomain(self, clkdomain): 536 self.gic.clk_domain = clkdomain 537 if hasattr(self, "gicv2m"): 538 self.gicv2m.clk_domain = clkdomain 539 self.hdlcd.clk_domain = clkdomain 540 self.vgic.clk_domain = clkdomain 541 542 # Attach I/O devices to specified bus object. Done here 543 # as the specified bus to connect to may not always be fixed. 544 def attachIO(self, bus): 545 self.uart.pio = bus.master 546 self.realview_io.pio = bus.master 547 self.timer0.pio = bus.master 548 self.timer1.pio = bus.master 549 self.clcd.pio = bus.master 550 self.clcd.dma = bus.slave 551 self.hdlcd.pio = bus.master 552 self.kmi0.pio = bus.master 553 self.kmi1.pio = bus.master 554 self.cf_ctrl.pio = bus.master 555 self.cf_ctrl.dma = bus.slave 556 self.cf_ctrl.config = bus.master 557 self.rtc.pio = bus.master 558 bus.use_default_range = True 559 self.vram.port = bus.master 560 self.pciconfig.pio = bus.default 561 562 self.l2x0_fake.pio = bus.master 563 self.uart1_fake.pio = bus.master 564 self.uart2_fake.pio = bus.master 565 self.uart3_fake.pio = bus.master 566 self.sp810_fake.pio = bus.master 567 self.watchdog_fake.pio = bus.master 568 self.aaci_fake.pio = bus.master 569 self.lan_fake.pio = bus.master 570 self.usb_fake.pio = bus.master 571 self.mmc_fake.pio = bus.master 572 self.energy_ctrl.pio = bus.master 573 574 # Try to attach the I/O if it exists 575 try: 576 self.ide.pio = bus.master 577 self.ide.config = bus.master 578 self.ide.dma = bus.slave 579 self.ethernet.pio = bus.master 580 self.ethernet.config = bus.master 581 self.ethernet.dma = bus.slave 582 except: 583 pass 584 585 # Set the clock domain for IO objects that are considered 586 # to be "far" away from the cores. 587 def offChipIOClkDomain(self, clkdomain): 588 self.uart.clk_domain = clkdomain 589 self.realview_io.clk_domain = clkdomain 590 self.timer0.clk_domain = clkdomain 591 self.timer1.clk_domain = clkdomain 592 self.clcd.clk_domain = clkdomain 593 self.kmi0.clk_domain = clkdomain 594 self.kmi1.clk_domain = clkdomain 595 self.cf_ctrl.clk_domain = clkdomain 596 self.rtc.clk_domain = clkdomain 597 self.vram.clk_domain = clkdomain 598 self.pciconfig.clk_domain = clkdomain 599 600 self.l2x0_fake.clk_domain = clkdomain 601 self.uart1_fake.clk_domain = clkdomain 602 self.uart2_fake.clk_domain = clkdomain 603 self.uart3_fake.clk_domain = clkdomain 604 self.sp810_fake.clk_domain = clkdomain 605 self.watchdog_fake.clk_domain = clkdomain 606 self.aaci_fake.clk_domain = clkdomain 607 self.lan_fake.clk_domain = clkdomain 608 self.usb_fake.clk_domain = clkdomain 609 self.mmc_fake.clk_domain = clkdomain 610 self.energy_ctrl.clk_domain = clkdomain 611 612class VExpress_EMM64(VExpress_EMM): 613 pci_io_base = 0x2f000000 614 pci_cfg_gen_offsets = True 615 # Three memory regions are specified totalling 512GB 616 _mem_regions = [(Addr('2GB'), Addr('2GB')), (Addr('34GB'), Addr('30GB')), 617 (Addr('512GB'), Addr('480GB'))] 618 def setupBootLoader(self, mem_bus, cur_sys, loc): 619 self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB')) 620 self.nvmem.port = mem_bus.master 621 cur_sys.boot_loader = loc('boot_emm.arm64') 622 cur_sys.atags_addr = 0x8000000 623 cur_sys.load_addr_mask = 0xfffffff 624 cur_sys.load_offset = 0x80000000 625 626 627