tsunami_pchip.cc revision 775 
1/* $Id$ */
2
3/* @file
4 * Tsunami PChip (pci)
5 */
6
7#include <deque>
8#include <string>
9#include <vector>
10
11#include "base/trace.hh"
12#include "cpu/exec_context.hh"
13#include "dev/console.hh"
14#include "dev/etherdev.hh"
15#include "dev/scsi_ctrl.hh"
16#include "dev/tlaser_clock.hh"
17#include "dev/tsunami_pchip.hh"
18#include "dev/tsunamireg.h"
19#include "dev/tsunami.hh"
20#include "mem/functional_mem/memory_control.hh"
21#include "sim/builder.hh"
22#include "sim/system.hh"
23
24using namespace std;
25
26TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t,
27                       Addr addr, Addr mask, MemoryController *mmu)
28    : MmapDevice(name, addr, mask, mmu), tsunami(t)
29{
30    wsba0 = 0;
31    wsba1 = 0;
32    wsba2 = 0;
33    wsba3 = 0;
34    wsm0 = 0;
35    wsm1 = 0;
36    wsm2 = 0;
37    wsm3 = 0;
38    tba0 = 0;
39    tba1 = 0;
40    tba2 = 0;
41    tba3 = 0;
42
43    //Set back pointer in tsunami
44    tsunami->pchip = this;
45}
46
47Fault
48TsunamiPChip::read(MemReqPtr req, uint8_t *data)
49{
50    DPRINTF(Tsunami, "read  va=%#x size=%d\n",
51            req->vaddr, req->size);
52
53    Addr daddr = (req->paddr & addr_mask) >> 6;
54//    ExecContext *xc = req->xc;
55//    int cpuid = xc->cpu_id;
56
57    switch (req->size) {
58
59      case sizeof(uint64_t):
60          switch(daddr) {
61              case TSDEV_PC_WSBA0:
62                    *(uint64_t*)data = wsba0;
63                    return No_Fault;
64              case TSDEV_PC_WSBA1:
65                    *(uint64_t*)data = wsba1;
66                    return No_Fault;
67              case TSDEV_PC_WSBA2:
68                    *(uint64_t*)data = wsba2;
69                    return No_Fault;
70              case TSDEV_PC_WSBA3:
71                    *(uint64_t*)data = wsba3;
72                    return No_Fault;
73              case TSDEV_PC_WSM0:
74                    *(uint64_t*)data = wsm0;
75                    return No_Fault;
76              case TSDEV_PC_WSM1:
77                    *(uint64_t*)data = wsm1;
78                    return No_Fault;
79              case TSDEV_PC_WSM2:
80                    *(uint64_t*)data = wsm2;
81                    return No_Fault;
82              case TSDEV_PC_WSM3:
83                    *(uint64_t*)data = wsm3;
84                    return No_Fault;
85              case TSDEV_PC_TBA0:
86                    *(uint64_t*)data = tba0;
87                    return No_Fault;
88              case TSDEV_PC_TBA1:
89                    *(uint64_t*)data = tba1;
90                    return No_Fault;
91              case TSDEV_PC_TBA2:
92                    *(uint64_t*)data = tba2;
93                    return No_Fault;
94              case TSDEV_PC_TBA3:
95                    *(uint64_t*)data = tba3;
96                    return No_Fault;
97              case TSDEV_PC_PCTL:
98                    // might want to change the clock??
99                    *(uint64_t*)data = 0x00; // try this
100                    return No_Fault;
101              case TSDEV_PC_PLAT:
102                    panic("PC_PLAT not implemented\n");
103              case TSDEV_PC_RES:
104                    panic("PC_RES not implemented\n");
105              case TSDEV_PC_PERROR:
106                    panic("PC_PERROR not implemented\n");
107              case TSDEV_PC_PERRMASK:
108                    panic("PC_PERRMASK not implemented\n");
109              case TSDEV_PC_PERRSET:
110                    panic("PC_PERRSET not implemented\n");
111              case TSDEV_PC_TLBIV:
112                    panic("PC_TLBIV not implemented\n");
113              case TSDEV_PC_TLBIA:
114                    *(uint64_t*)data = 0x00; // shouldn't be readable, but linux
115                    return No_Fault;
116              case TSDEV_PC_PMONCTL:
117                    panic("PC_PMONCTL not implemented\n");
118              case TSDEV_PC_PMONCNT:
119                    panic("PC_PMONCTN not implemented\n");
120              default:
121                  panic("Default in PChip Read reached reading 0x%x\n", daddr);
122
123           } // uint64_t
124
125      break;
126      case sizeof(uint32_t):
127      case sizeof(uint16_t):
128      case sizeof(uint8_t):
129      default:
130        panic("invalid access size(?) for tsunami register!\n\n");
131    }
132    DPRINTFN("Tsunami PChip ERROR: read  daddr=%#x size=%d\n", daddr, req->size);
133
134    return No_Fault;
135}
136
137Fault
138TsunamiPChip::write(MemReqPtr req, const uint8_t *data)
139{
140    DPRINTF(Tsunami, "write - va=%#x size=%d \n",
141            req->vaddr, req->size);
142
143    Addr daddr = (req->paddr & addr_mask) >> 6;
144
145    switch (req->size) {
146
147      case sizeof(uint64_t):
148          switch(daddr) {
149              case TSDEV_PC_WSBA0:
150                    wsba0 = *(uint64_t*)data;
151                    return No_Fault;
152              case TSDEV_PC_WSBA1:
153                    wsba1 = *(uint64_t*)data;
154                    return No_Fault;
155              case TSDEV_PC_WSBA2:
156                    wsba2 = *(uint64_t*)data;
157                    return No_Fault;
158              case TSDEV_PC_WSBA3:
159                    wsba3 = *(uint64_t*)data;
160                    return No_Fault;
161              case TSDEV_PC_WSM0:
162                    wsm0 = *(uint64_t*)data;
163                    return No_Fault;
164              case TSDEV_PC_WSM1:
165                    wsm1 = *(uint64_t*)data;
166                    return No_Fault;
167              case TSDEV_PC_WSM2:
168                    wsm2 = *(uint64_t*)data;
169                    return No_Fault;
170              case TSDEV_PC_WSM3:
171                    wsm3 = *(uint64_t*)data;
172                    return No_Fault;
173              case TSDEV_PC_TBA0:
174                    tba0 = *(uint64_t*)data;
175                    return No_Fault;
176              case TSDEV_PC_TBA1:
177                    tba1 = *(uint64_t*)data;
178                    return No_Fault;
179              case TSDEV_PC_TBA2:
180                    tba2 = *(uint64_t*)data;
181                    return No_Fault;
182              case TSDEV_PC_TBA3:
183                    tba3 = *(uint64_t*)data;
184                    return No_Fault;
185              case TSDEV_PC_PCTL:
186                    // might want to change the clock??
187                    //*(uint64_t*)data; // try this
188                    return No_Fault;
189              case TSDEV_PC_PLAT:
190                    panic("PC_PLAT not implemented\n");
191              case TSDEV_PC_RES:
192                    panic("PC_RES not implemented\n");
193              case TSDEV_PC_PERROR:
194                    panic("PC_PERROR not implemented\n");
195              case TSDEV_PC_PERRMASK:
196                    panic("PC_PERRMASK not implemented\n");
197              case TSDEV_PC_PERRSET:
198                    panic("PC_PERRSET not implemented\n");
199              case TSDEV_PC_TLBIV:
200                    panic("PC_TLBIV not implemented\n");
201              case TSDEV_PC_TLBIA:
202                    return No_Fault; // value ignored, supposted to invalidate SG TLB
203              case TSDEV_PC_PMONCTL:
204                    panic("PC_PMONCTL not implemented\n");
205              case TSDEV_PC_PMONCNT:
206                    panic("PC_PMONCTN not implemented\n");
207              default:
208                  panic("Default in PChip Read reached reading 0x%x\n", daddr);
209
210           } // uint64_t
211
212      break;
213      case sizeof(uint32_t):
214      case sizeof(uint16_t):
215      case sizeof(uint8_t):
216      default:
217        panic("invalid access size(?) for tsunami register!\n\n");
218    }
219
220    DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
221
222    return No_Fault;
223}
224
225void
226TsunamiPChip::serialize(std::ostream &os)
227{
228    // code should be written
229}
230
231void
232TsunamiPChip::unserialize(Checkpoint *cp, const std::string &section)
233{
234    //code should be written
235}
236
237BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
238
239    SimObjectParam<Tsunami *> tsunami;
240    SimObjectParam<MemoryController *> mmu;
241    Param<Addr> addr;
242    Param<Addr> mask;
243
244END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
245
246BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
247
248    INIT_PARAM(tsunami, "Tsunami"),
249    INIT_PARAM(mmu, "Memory Controller"),
250    INIT_PARAM(addr, "Device Address"),
251    INIT_PARAM(mask, "Address Mask")
252
253END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
254
255CREATE_SIM_OBJECT(TsunamiPChip)
256{
257    return new TsunamiPChip(getInstanceName(), tsunami, addr, mask, mmu);
258}
259
260REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)
261