tsunami_pchip.cc revision 4870
1892SN/A/*
21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
3892SN/A * All rights reserved.
4892SN/A *
5892SN/A * Redistribution and use in source and binary forms, with or without
6892SN/A * modification, are permitted provided that the following conditions are
7892SN/A * met: redistributions of source code must retain the above copyright
8892SN/A * notice, this list of conditions and the following disclaimer;
9892SN/A * redistributions in binary form must reproduce the above copyright
10892SN/A * notice, this list of conditions and the following disclaimer in the
11892SN/A * documentation and/or other materials provided with the distribution;
12892SN/A * neither the name of the copyright holders nor the names of its
13892SN/A * contributors may be used to endorse or promote products derived from
14892SN/A * this software without specific prior written permission.
15892SN/A *
16892SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17892SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18892SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19892SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20892SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21892SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22892SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23892SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24892SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25892SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26892SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665SN/A *
282665SN/A * Authors: Ali Saidi
292665SN/A *          Andrew Schultz
30892SN/A */
31768SN/A
321730SN/A/** @file
33768SN/A * Tsunami PChip (pci)
34768SN/A */
35768SN/A
36768SN/A#include <deque>
37768SN/A#include <string>
38768SN/A#include <vector>
39768SN/A
40768SN/A#include "base/trace.hh"
413540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_pchip.hh"
423540Sgblack@eecs.umich.edu#include "dev/alpha/tsunamireg.h"
433540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami.hh"
442542SN/A#include "mem/packet.hh"
453348SN/A#include "mem/packet_access.hh"
46768SN/A#include "sim/builder.hh"
47768SN/A#include "sim/system.hh"
48768SN/A
49768SN/Ausing namespace std;
502107SN/A//Should this be AlphaISA?
512107SN/Ausing namespace TheISA;
52768SN/A
532539SN/ATsunamiPChip::TsunamiPChip(Params *p)
542542SN/A: BasicPioDevice(p)
55768SN/A{
563846Shsul@eecs.umich.edu    pioSize = 0x1000;
57809SN/A
58835SN/A    for (int i = 0; i < 4; i++) {
59835SN/A        wsba[i] = 0;
60835SN/A        wsm[i] = 0;
61835SN/A        tba[i] = 0;
62835SN/A    }
63768SN/A
64896SN/A    // initialize pchip control register
65896SN/A    pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
66896SN/A
67775SN/A    //Set back pointer in tsunami
682539SN/A    p->tsunami->pchip = this;
692539SN/A}
702539SN/A
712539SN/ATick
723349SN/ATsunamiPChip::read(PacketPtr pkt)
732539SN/A{
742641SN/A    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
752539SN/A
762630SN/A    pkt->allocate();
772641SN/A    Addr daddr = (pkt->getAddr() - pioAddr) >> 6;;
782641SN/A    assert(pkt->getSize() == sizeof(uint64_t));
792539SN/A
802539SN/A
812641SN/A    DPRINTF(Tsunami, "read  va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
822539SN/A
832539SN/A    switch(daddr) {
842539SN/A      case TSDEV_PC_WSBA0:
852630SN/A            pkt->set(wsba[0]);
862539SN/A            break;
872539SN/A      case TSDEV_PC_WSBA1:
882630SN/A            pkt->set(wsba[1]);
892539SN/A            break;
902539SN/A      case TSDEV_PC_WSBA2:
912630SN/A            pkt->set(wsba[2]);
922539SN/A            break;
932539SN/A      case TSDEV_PC_WSBA3:
942630SN/A            pkt->set(wsba[3]);
952539SN/A            break;
962539SN/A      case TSDEV_PC_WSM0:
972630SN/A            pkt->set(wsm[0]);
982539SN/A            break;
992539SN/A      case TSDEV_PC_WSM1:
1002630SN/A            pkt->set(wsm[1]);
1012539SN/A            break;
1022539SN/A      case TSDEV_PC_WSM2:
1032630SN/A            pkt->set(wsm[2]);
1042539SN/A            break;
1052539SN/A      case TSDEV_PC_WSM3:
1062630SN/A            pkt->set(wsm[3]);
1072539SN/A            break;
1082539SN/A      case TSDEV_PC_TBA0:
1092630SN/A            pkt->set(tba[0]);
1102539SN/A            break;
1112539SN/A      case TSDEV_PC_TBA1:
1122630SN/A            pkt->set(tba[1]);
1132539SN/A            break;
1142539SN/A      case TSDEV_PC_TBA2:
1152630SN/A            pkt->set(tba[2]);
1162539SN/A            break;
1172542SN/A      case TSDEV_PC_TBA3:
1182630SN/A            pkt->set(tba[3]);
1192539SN/A            break;
1202539SN/A      case TSDEV_PC_PCTL:
1212630SN/A            pkt->set(pctl);
1222539SN/A            break;
1232539SN/A      case TSDEV_PC_PLAT:
1242539SN/A            panic("PC_PLAT not implemented\n");
1252539SN/A      case TSDEV_PC_RES:
1262539SN/A            panic("PC_RES not implemented\n");
1272539SN/A      case TSDEV_PC_PERROR:
1282630SN/A            pkt->set((uint64_t)0x00);
1292539SN/A            break;
1302539SN/A      case TSDEV_PC_PERRMASK:
1312630SN/A            pkt->set((uint64_t)0x00);
1322539SN/A            break;
1332539SN/A      case TSDEV_PC_PERRSET:
1342539SN/A            panic("PC_PERRSET not implemented\n");
1352539SN/A      case TSDEV_PC_TLBIV:
1362539SN/A            panic("PC_TLBIV not implemented\n");
1372539SN/A      case TSDEV_PC_TLBIA:
1382630SN/A            pkt->set((uint64_t)0x00); // shouldn't be readable, but linux
1392539SN/A            break;
1402539SN/A      case TSDEV_PC_PMONCTL:
1412539SN/A            panic("PC_PMONCTL not implemented\n");
1422539SN/A      case TSDEV_PC_PMONCNT:
1432539SN/A            panic("PC_PMONCTN not implemented\n");
1442539SN/A      default:
1452539SN/A          panic("Default in PChip Read reached reading 0x%x\n", daddr);
1462539SN/A    }
1474870Sstever@eecs.umich.edu    pkt->makeAtomicResponse();
1482539SN/A    return pioDelay;
1492539SN/A
150768SN/A}
151768SN/A
1522542SN/ATick
1533349SN/ATsunamiPChip::write(PacketPtr pkt)
154768SN/A{
1552641SN/A    assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize);
1562641SN/A    Addr daddr = (pkt->getAddr() - pioAddr) >> 6;
157768SN/A
1582641SN/A    assert(pkt->getSize() == sizeof(uint64_t));
159768SN/A
1602641SN/A    DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize());
161768SN/A
1622539SN/A    switch(daddr) {
1632539SN/A        case TSDEV_PC_WSBA0:
1642630SN/A              wsba[0] = pkt->get<uint64_t>();
1652539SN/A              break;
1662539SN/A        case TSDEV_PC_WSBA1:
1672630SN/A              wsba[1] = pkt->get<uint64_t>();
1682539SN/A              break;
1692539SN/A        case TSDEV_PC_WSBA2:
1702630SN/A              wsba[2] = pkt->get<uint64_t>();
1712539SN/A              break;
1722539SN/A        case TSDEV_PC_WSBA3:
1732630SN/A              wsba[3] = pkt->get<uint64_t>();
1742539SN/A              break;
1752539SN/A        case TSDEV_PC_WSM0:
1762630SN/A              wsm[0] = pkt->get<uint64_t>();
1772539SN/A              break;
1782539SN/A        case TSDEV_PC_WSM1:
1792630SN/A              wsm[1] = pkt->get<uint64_t>();
1802539SN/A              break;
1812539SN/A        case TSDEV_PC_WSM2:
1822630SN/A              wsm[2] = pkt->get<uint64_t>();
1832539SN/A              break;
1842539SN/A        case TSDEV_PC_WSM3:
1852630SN/A              wsm[3] = pkt->get<uint64_t>();
1862539SN/A              break;
1872539SN/A        case TSDEV_PC_TBA0:
1882630SN/A              tba[0] = pkt->get<uint64_t>();
1892539SN/A              break;
1902539SN/A        case TSDEV_PC_TBA1:
1912630SN/A              tba[1] = pkt->get<uint64_t>();
1922539SN/A              break;
1932539SN/A        case TSDEV_PC_TBA2:
1942630SN/A              tba[2] = pkt->get<uint64_t>();
1952539SN/A              break;
1962539SN/A        case TSDEV_PC_TBA3:
1972630SN/A              tba[3] = pkt->get<uint64_t>();
1982539SN/A              break;
1992539SN/A        case TSDEV_PC_PCTL:
2002630SN/A              pctl = pkt->get<uint64_t>();
2012539SN/A              break;
2022539SN/A        case TSDEV_PC_PLAT:
2032539SN/A              panic("PC_PLAT not implemented\n");
2042539SN/A        case TSDEV_PC_RES:
2052539SN/A              panic("PC_RES not implemented\n");
2062539SN/A        case TSDEV_PC_PERROR:
2072539SN/A              break;
2082539SN/A        case TSDEV_PC_PERRMASK:
2092539SN/A              panic("PC_PERRMASK not implemented\n");
2102539SN/A        case TSDEV_PC_PERRSET:
2112539SN/A              panic("PC_PERRSET not implemented\n");
2122539SN/A        case TSDEV_PC_TLBIV:
2132539SN/A              panic("PC_TLBIV not implemented\n");
2142539SN/A        case TSDEV_PC_TLBIA:
2152539SN/A              break; // value ignored, supposted to invalidate SG TLB
2162539SN/A        case TSDEV_PC_PMONCTL:
2172539SN/A              panic("PC_PMONCTL not implemented\n");
2182539SN/A        case TSDEV_PC_PMONCNT:
2192539SN/A              panic("PC_PMONCTN not implemented\n");
2202539SN/A        default:
2212549SN/A            panic("Default in PChip write reached reading 0x%x\n", daddr);
222768SN/A
2232539SN/A    } // uint64_t
224768SN/A
2254870Sstever@eecs.umich.edu    pkt->makeAtomicResponse();
2262539SN/A    return pioDelay;
227768SN/A}
228768SN/A
229857SN/A#define DMA_ADDR_MASK ULL(0x3ffffffff)
230857SN/A
231835SN/AAddr
232835SN/ATsunamiPChip::translatePciToDma(Addr busAddr)
233835SN/A{
234835SN/A    // compare the address to the window base registers
235857SN/A    uint64_t tbaMask = 0;
236857SN/A    uint64_t baMask = 0;
237857SN/A
238835SN/A    uint64_t windowMask = 0;
239835SN/A    uint64_t windowBase = 0;
240857SN/A
241857SN/A    uint64_t pteEntry = 0;
242857SN/A
243857SN/A    Addr pteAddr;
244835SN/A    Addr dmaAddr;
245835SN/A
246896SN/A#if 0
247896SN/A    DPRINTF(IdeDisk, "Translation for bus address: %#x\n", busAddr);
248835SN/A    for (int i = 0; i < 4; i++) {
249896SN/A        DPRINTF(IdeDisk, "(%d) base:%#x mask:%#x\n",
250896SN/A                i, wsba[i], wsm[i]);
251896SN/A
252835SN/A        windowBase = wsba[i];
253896SN/A        windowMask = ~wsm[i] & (ULL(0xfff) << 20);
254835SN/A
255835SN/A        if ((busAddr & windowMask) == (windowBase & windowMask)) {
256896SN/A            DPRINTF(IdeDisk, "Would have matched %d (wb:%#x wm:%#x --> ba&wm:%#x wb&wm:%#x)\n",
257896SN/A                    i, windowBase, windowMask, (busAddr & windowMask),
258896SN/A                    (windowBase & windowMask));
259896SN/A        }
260896SN/A    }
261896SN/A#endif
262857SN/A
263896SN/A    for (int i = 0; i < 4; i++) {
264896SN/A
265896SN/A        windowBase = wsba[i];
266896SN/A        windowMask = ~wsm[i] & (ULL(0xfff) << 20);
267896SN/A
268896SN/A        if ((busAddr & windowMask) == (windowBase & windowMask)) {
269835SN/A
270835SN/A            if (wsba[i] & 0x1) {   // see if enabled
271857SN/A                if (wsba[i] & 0x2) { // see if SG bit is set
272857SN/A                    /** @todo
273857SN/A                        This currently is faked by just doing a direct
274857SN/A                        read from memory, however, to be realistic, this
275857SN/A                        needs to actually do a bus transaction.  The process
276857SN/A                        is explained in the tsunami documentation on page
277857SN/A                        10-12 and basically munges the address to look up a
278857SN/A                        PTE from a table in memory and then uses that mapping
279857SN/A                        to create an address for the SG page
280857SN/A                    */
281835SN/A
282896SN/A                    tbaMask = ~(((wsm[i] & (ULL(0xfff) << 20)) >> 10) | ULL(0x3ff));
283896SN/A                    baMask = (wsm[i] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13);
284857SN/A                    pteAddr = (tba[i] & tbaMask) | ((busAddr & baMask) >> 10);
285857SN/A
2862542SN/A                    pioPort->readBlob(pteAddr, (uint8_t*)&pteEntry, sizeof(uint64_t));
287857SN/A
288896SN/A                    dmaAddr = ((pteEntry & ~ULL(0x1)) << 12) | (busAddr & ULL(0x1fff));
289857SN/A
290857SN/A                } else {
291896SN/A                    baMask = (wsm[i] & (ULL(0xfff) << 20)) | ULL(0xfffff);
292857SN/A                    tbaMask = ~baMask;
293857SN/A                    dmaAddr = (tba[i] & tbaMask) | (busAddr & baMask);
294857SN/A                }
295857SN/A
296857SN/A                return (dmaAddr & DMA_ADDR_MASK);
297835SN/A            }
298835SN/A        }
299835SN/A    }
300835SN/A
301896SN/A    // if no match was found, then return the original address
302896SN/A    return busAddr;
303835SN/A}
3042846SN/AAddr
3052846SN/ATsunamiPChip::calcConfigAddr(int bus, int dev, int func)
3062846SN/A{
3072846SN/A    assert(func < 8);
3082846SN/A    assert(dev < 32);
3092846SN/A    assert(bus == 0);
3102846SN/A
3112846SN/A    return TsunamiPciBus0Config | (func << 8) | (dev << 11);
3122846SN/A}
3132846SN/A
3142846SN/A
315835SN/A
316768SN/Avoid
317768SN/ATsunamiPChip::serialize(std::ostream &os)
318768SN/A{
319896SN/A    SERIALIZE_SCALAR(pctl);
320835SN/A    SERIALIZE_ARRAY(wsba, 4);
321835SN/A    SERIALIZE_ARRAY(wsm, 4);
322835SN/A    SERIALIZE_ARRAY(tba, 4);
323768SN/A}
324768SN/A
325768SN/Avoid
326768SN/ATsunamiPChip::unserialize(Checkpoint *cp, const std::string &section)
327768SN/A{
328896SN/A    UNSERIALIZE_SCALAR(pctl);
329835SN/A    UNSERIALIZE_ARRAY(wsba, 4);
330835SN/A    UNSERIALIZE_ARRAY(wsm, 4);
331835SN/A    UNSERIALIZE_ARRAY(tba, 4);
332768SN/A}
333768SN/A
334909SN/A
335768SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
336768SN/A
3372539SN/A    Param<Addr> pio_addr;
3382539SN/A    Param<Tick> pio_latency;
3392539SN/A    SimObjectParam<Platform *> platform;
3402539SN/A    SimObjectParam<System *> system;
341775SN/A    SimObjectParam<Tsunami *> tsunami;
342768SN/A
343768SN/AEND_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
344768SN/A
345768SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
346768SN/A
3472539SN/A    INIT_PARAM(pio_addr, "Device Address"),
3482539SN/A    INIT_PARAM(pio_latency, "Programmed IO latency"),
3492539SN/A    INIT_PARAM(platform, "platform"),
3502539SN/A    INIT_PARAM(system, "system object"),
3512539SN/A    INIT_PARAM(tsunami, "Tsunami")
352768SN/A
353768SN/AEND_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
354768SN/A
355768SN/ACREATE_SIM_OBJECT(TsunamiPChip)
356768SN/A{
3572539SN/A    TsunamiPChip::Params *p = new TsunamiPChip::Params;
3582539SN/A    p->name = getInstanceName();
3592539SN/A    p->pio_addr = pio_addr;
3602539SN/A    p->pio_delay = pio_latency;
3612539SN/A    p->platform = platform;
3622539SN/A    p->system = system;
3632539SN/A    p->tsunami = tsunami;
3642539SN/A    return new TsunamiPChip(p);
365768SN/A}
366768SN/A
367768SN/AREGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)
368