tsunami_pchip.cc revision 4762
1892SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 3892SN/A * All rights reserved. 4892SN/A * 5892SN/A * Redistribution and use in source and binary forms, with or without 6892SN/A * modification, are permitted provided that the following conditions are 7892SN/A * met: redistributions of source code must retain the above copyright 8892SN/A * notice, this list of conditions and the following disclaimer; 9892SN/A * redistributions in binary form must reproduce the above copyright 10892SN/A * notice, this list of conditions and the following disclaimer in the 11892SN/A * documentation and/or other materials provided with the distribution; 12892SN/A * neither the name of the copyright holders nor the names of its 13892SN/A * contributors may be used to endorse or promote products derived from 14892SN/A * this software without specific prior written permission. 15892SN/A * 16892SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17892SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18892SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19892SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20892SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21892SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22892SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23892SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24892SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25892SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26892SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Ali Saidi 292665SN/A * Andrew Schultz 30892SN/A */ 31768SN/A 321730SN/A/** @file 33768SN/A * Tsunami PChip (pci) 34768SN/A */ 35768SN/A 36768SN/A#include <deque> 37768SN/A#include <string> 38768SN/A#include <vector> 39768SN/A 40768SN/A#include "base/trace.hh" 413540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_pchip.hh" 423540Sgblack@eecs.umich.edu#include "dev/alpha/tsunamireg.h" 433540Sgblack@eecs.umich.edu#include "dev/alpha/tsunami.hh" 442542SN/A#include "mem/packet.hh" 453348SN/A#include "mem/packet_access.hh" 46768SN/A#include "sim/system.hh" 47768SN/A 48768SN/Ausing namespace std; 492107SN/A//Should this be AlphaISA? 502107SN/Ausing namespace TheISA; 51768SN/A 524762Snate@binkert.orgTsunamiPChip::TsunamiPChip(const Params *p) 532542SN/A: BasicPioDevice(p) 54768SN/A{ 553846Shsul@eecs.umich.edu pioSize = 0x1000; 56809SN/A 57835SN/A for (int i = 0; i < 4; i++) { 58835SN/A wsba[i] = 0; 59835SN/A wsm[i] = 0; 60835SN/A tba[i] = 0; 61835SN/A } 62768SN/A 63896SN/A // initialize pchip control register 64896SN/A pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36); 65896SN/A 66775SN/A //Set back pointer in tsunami 672539SN/A p->tsunami->pchip = this; 682539SN/A} 692539SN/A 702539SN/ATick 713349SN/ATsunamiPChip::read(PacketPtr pkt) 722539SN/A{ 732641SN/A assert(pkt->result == Packet::Unknown); 742641SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 752539SN/A 762630SN/A pkt->allocate(); 772641SN/A Addr daddr = (pkt->getAddr() - pioAddr) >> 6;; 782641SN/A assert(pkt->getSize() == sizeof(uint64_t)); 792539SN/A 802539SN/A 812641SN/A DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); 822539SN/A 832539SN/A switch(daddr) { 842539SN/A case TSDEV_PC_WSBA0: 852630SN/A pkt->set(wsba[0]); 862539SN/A break; 872539SN/A case TSDEV_PC_WSBA1: 882630SN/A pkt->set(wsba[1]); 892539SN/A break; 902539SN/A case TSDEV_PC_WSBA2: 912630SN/A pkt->set(wsba[2]); 922539SN/A break; 932539SN/A case TSDEV_PC_WSBA3: 942630SN/A pkt->set(wsba[3]); 952539SN/A break; 962539SN/A case TSDEV_PC_WSM0: 972630SN/A pkt->set(wsm[0]); 982539SN/A break; 992539SN/A case TSDEV_PC_WSM1: 1002630SN/A pkt->set(wsm[1]); 1012539SN/A break; 1022539SN/A case TSDEV_PC_WSM2: 1032630SN/A pkt->set(wsm[2]); 1042539SN/A break; 1052539SN/A case TSDEV_PC_WSM3: 1062630SN/A pkt->set(wsm[3]); 1072539SN/A break; 1082539SN/A case TSDEV_PC_TBA0: 1092630SN/A pkt->set(tba[0]); 1102539SN/A break; 1112539SN/A case TSDEV_PC_TBA1: 1122630SN/A pkt->set(tba[1]); 1132539SN/A break; 1142539SN/A case TSDEV_PC_TBA2: 1152630SN/A pkt->set(tba[2]); 1162539SN/A break; 1172542SN/A case TSDEV_PC_TBA3: 1182630SN/A pkt->set(tba[3]); 1192539SN/A break; 1202539SN/A case TSDEV_PC_PCTL: 1212630SN/A pkt->set(pctl); 1222539SN/A break; 1232539SN/A case TSDEV_PC_PLAT: 1242539SN/A panic("PC_PLAT not implemented\n"); 1252539SN/A case TSDEV_PC_RES: 1262539SN/A panic("PC_RES not implemented\n"); 1272539SN/A case TSDEV_PC_PERROR: 1282630SN/A pkt->set((uint64_t)0x00); 1292539SN/A break; 1302539SN/A case TSDEV_PC_PERRMASK: 1312630SN/A pkt->set((uint64_t)0x00); 1322539SN/A break; 1332539SN/A case TSDEV_PC_PERRSET: 1342539SN/A panic("PC_PERRSET not implemented\n"); 1352539SN/A case TSDEV_PC_TLBIV: 1362539SN/A panic("PC_TLBIV not implemented\n"); 1372539SN/A case TSDEV_PC_TLBIA: 1382630SN/A pkt->set((uint64_t)0x00); // shouldn't be readable, but linux 1392539SN/A break; 1402539SN/A case TSDEV_PC_PMONCTL: 1412539SN/A panic("PC_PMONCTL not implemented\n"); 1422539SN/A case TSDEV_PC_PMONCNT: 1432539SN/A panic("PC_PMONCTN not implemented\n"); 1442539SN/A default: 1452539SN/A panic("Default in PChip Read reached reading 0x%x\n", daddr); 1462539SN/A } 1472641SN/A pkt->result = Packet::Success; 1482539SN/A return pioDelay; 1492539SN/A 150768SN/A} 151768SN/A 1522542SN/ATick 1533349SN/ATsunamiPChip::write(PacketPtr pkt) 154768SN/A{ 1552641SN/A assert(pkt->result == Packet::Unknown); 1562641SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 1572641SN/A Addr daddr = (pkt->getAddr() - pioAddr) >> 6; 158768SN/A 1592641SN/A assert(pkt->getSize() == sizeof(uint64_t)); 160768SN/A 1612641SN/A DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize()); 162768SN/A 1632539SN/A switch(daddr) { 1642539SN/A case TSDEV_PC_WSBA0: 1652630SN/A wsba[0] = pkt->get<uint64_t>(); 1662539SN/A break; 1672539SN/A case TSDEV_PC_WSBA1: 1682630SN/A wsba[1] = pkt->get<uint64_t>(); 1692539SN/A break; 1702539SN/A case TSDEV_PC_WSBA2: 1712630SN/A wsba[2] = pkt->get<uint64_t>(); 1722539SN/A break; 1732539SN/A case TSDEV_PC_WSBA3: 1742630SN/A wsba[3] = pkt->get<uint64_t>(); 1752539SN/A break; 1762539SN/A case TSDEV_PC_WSM0: 1772630SN/A wsm[0] = pkt->get<uint64_t>(); 1782539SN/A break; 1792539SN/A case TSDEV_PC_WSM1: 1802630SN/A wsm[1] = pkt->get<uint64_t>(); 1812539SN/A break; 1822539SN/A case TSDEV_PC_WSM2: 1832630SN/A wsm[2] = pkt->get<uint64_t>(); 1842539SN/A break; 1852539SN/A case TSDEV_PC_WSM3: 1862630SN/A wsm[3] = pkt->get<uint64_t>(); 1872539SN/A break; 1882539SN/A case TSDEV_PC_TBA0: 1892630SN/A tba[0] = pkt->get<uint64_t>(); 1902539SN/A break; 1912539SN/A case TSDEV_PC_TBA1: 1922630SN/A tba[1] = pkt->get<uint64_t>(); 1932539SN/A break; 1942539SN/A case TSDEV_PC_TBA2: 1952630SN/A tba[2] = pkt->get<uint64_t>(); 1962539SN/A break; 1972539SN/A case TSDEV_PC_TBA3: 1982630SN/A tba[3] = pkt->get<uint64_t>(); 1992539SN/A break; 2002539SN/A case TSDEV_PC_PCTL: 2012630SN/A pctl = pkt->get<uint64_t>(); 2022539SN/A break; 2032539SN/A case TSDEV_PC_PLAT: 2042539SN/A panic("PC_PLAT not implemented\n"); 2052539SN/A case TSDEV_PC_RES: 2062539SN/A panic("PC_RES not implemented\n"); 2072539SN/A case TSDEV_PC_PERROR: 2082539SN/A break; 2092539SN/A case TSDEV_PC_PERRMASK: 2102539SN/A panic("PC_PERRMASK not implemented\n"); 2112539SN/A case TSDEV_PC_PERRSET: 2122539SN/A panic("PC_PERRSET not implemented\n"); 2132539SN/A case TSDEV_PC_TLBIV: 2142539SN/A panic("PC_TLBIV not implemented\n"); 2152539SN/A case TSDEV_PC_TLBIA: 2162539SN/A break; // value ignored, supposted to invalidate SG TLB 2172539SN/A case TSDEV_PC_PMONCTL: 2182539SN/A panic("PC_PMONCTL not implemented\n"); 2192539SN/A case TSDEV_PC_PMONCNT: 2202539SN/A panic("PC_PMONCTN not implemented\n"); 2212539SN/A default: 2222549SN/A panic("Default in PChip write reached reading 0x%x\n", daddr); 223768SN/A 2242539SN/A } // uint64_t 225768SN/A 2262641SN/A pkt->result = Packet::Success; 2272539SN/A return pioDelay; 228768SN/A} 229768SN/A 230857SN/A#define DMA_ADDR_MASK ULL(0x3ffffffff) 231857SN/A 232835SN/AAddr 233835SN/ATsunamiPChip::translatePciToDma(Addr busAddr) 234835SN/A{ 235835SN/A // compare the address to the window base registers 236857SN/A uint64_t tbaMask = 0; 237857SN/A uint64_t baMask = 0; 238857SN/A 239835SN/A uint64_t windowMask = 0; 240835SN/A uint64_t windowBase = 0; 241857SN/A 242857SN/A uint64_t pteEntry = 0; 243857SN/A 244857SN/A Addr pteAddr; 245835SN/A Addr dmaAddr; 246835SN/A 247896SN/A#if 0 248896SN/A DPRINTF(IdeDisk, "Translation for bus address: %#x\n", busAddr); 249835SN/A for (int i = 0; i < 4; i++) { 250896SN/A DPRINTF(IdeDisk, "(%d) base:%#x mask:%#x\n", 251896SN/A i, wsba[i], wsm[i]); 252896SN/A 253835SN/A windowBase = wsba[i]; 254896SN/A windowMask = ~wsm[i] & (ULL(0xfff) << 20); 255835SN/A 256835SN/A if ((busAddr & windowMask) == (windowBase & windowMask)) { 257896SN/A DPRINTF(IdeDisk, "Would have matched %d (wb:%#x wm:%#x --> ba&wm:%#x wb&wm:%#x)\n", 258896SN/A i, windowBase, windowMask, (busAddr & windowMask), 259896SN/A (windowBase & windowMask)); 260896SN/A } 261896SN/A } 262896SN/A#endif 263857SN/A 264896SN/A for (int i = 0; i < 4; i++) { 265896SN/A 266896SN/A windowBase = wsba[i]; 267896SN/A windowMask = ~wsm[i] & (ULL(0xfff) << 20); 268896SN/A 269896SN/A if ((busAddr & windowMask) == (windowBase & windowMask)) { 270835SN/A 271835SN/A if (wsba[i] & 0x1) { // see if enabled 272857SN/A if (wsba[i] & 0x2) { // see if SG bit is set 273857SN/A /** @todo 274857SN/A This currently is faked by just doing a direct 275857SN/A read from memory, however, to be realistic, this 276857SN/A needs to actually do a bus transaction. The process 277857SN/A is explained in the tsunami documentation on page 278857SN/A 10-12 and basically munges the address to look up a 279857SN/A PTE from a table in memory and then uses that mapping 280857SN/A to create an address for the SG page 281857SN/A */ 282835SN/A 283896SN/A tbaMask = ~(((wsm[i] & (ULL(0xfff) << 20)) >> 10) | ULL(0x3ff)); 284896SN/A baMask = (wsm[i] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13); 285857SN/A pteAddr = (tba[i] & tbaMask) | ((busAddr & baMask) >> 10); 286857SN/A 2872542SN/A pioPort->readBlob(pteAddr, (uint8_t*)&pteEntry, sizeof(uint64_t)); 288857SN/A 289896SN/A dmaAddr = ((pteEntry & ~ULL(0x1)) << 12) | (busAddr & ULL(0x1fff)); 290857SN/A 291857SN/A } else { 292896SN/A baMask = (wsm[i] & (ULL(0xfff) << 20)) | ULL(0xfffff); 293857SN/A tbaMask = ~baMask; 294857SN/A dmaAddr = (tba[i] & tbaMask) | (busAddr & baMask); 295857SN/A } 296857SN/A 297857SN/A return (dmaAddr & DMA_ADDR_MASK); 298835SN/A } 299835SN/A } 300835SN/A } 301835SN/A 302896SN/A // if no match was found, then return the original address 303896SN/A return busAddr; 304835SN/A} 3052846SN/AAddr 3062846SN/ATsunamiPChip::calcConfigAddr(int bus, int dev, int func) 3072846SN/A{ 3082846SN/A assert(func < 8); 3092846SN/A assert(dev < 32); 3102846SN/A assert(bus == 0); 3112846SN/A 3122846SN/A return TsunamiPciBus0Config | (func << 8) | (dev << 11); 3132846SN/A} 3142846SN/A 3152846SN/A 316835SN/A 317768SN/Avoid 318768SN/ATsunamiPChip::serialize(std::ostream &os) 319768SN/A{ 320896SN/A SERIALIZE_SCALAR(pctl); 321835SN/A SERIALIZE_ARRAY(wsba, 4); 322835SN/A SERIALIZE_ARRAY(wsm, 4); 323835SN/A SERIALIZE_ARRAY(tba, 4); 324768SN/A} 325768SN/A 326768SN/Avoid 327768SN/ATsunamiPChip::unserialize(Checkpoint *cp, const std::string §ion) 328768SN/A{ 329896SN/A UNSERIALIZE_SCALAR(pctl); 330835SN/A UNSERIALIZE_ARRAY(wsba, 4); 331835SN/A UNSERIALIZE_ARRAY(wsm, 4); 332835SN/A UNSERIALIZE_ARRAY(tba, 4); 333768SN/A} 334768SN/A 335909SN/A 3364762Snate@binkert.orgTsunamiPChip * 3374762Snate@binkert.orgTsunamiPChipParams::create() 338768SN/A{ 3394762Snate@binkert.org return new TsunamiPChip(this); 340768SN/A} 341