tsunami_pchip.cc revision 2846
19651SAndreas.Sandberg@ARM.com/* 210605Sgabeblack@google.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 310859Sandreas.sandberg@arm.com * All rights reserved. 49651SAndreas.Sandberg@ARM.com * 59651SAndreas.Sandberg@ARM.com * Redistribution and use in source and binary forms, with or without 69651SAndreas.Sandberg@ARM.com * modification, are permitted provided that the following conditions are 79651SAndreas.Sandberg@ARM.com * met: redistributions of source code must retain the above copyright 89651SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer; 99651SAndreas.Sandberg@ARM.com * redistributions in binary form must reproduce the above copyright 109651SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer in the 119651SAndreas.Sandberg@ARM.com * documentation and/or other materials provided with the distribution; 129651SAndreas.Sandberg@ARM.com * neither the name of the copyright holders nor the names of its 139651SAndreas.Sandberg@ARM.com * contributors may be used to endorse or promote products derived from 149651SAndreas.Sandberg@ARM.com * this software without specific prior written permission. 159651SAndreas.Sandberg@ARM.com * 169651SAndreas.Sandberg@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 179651SAndreas.Sandberg@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 189651SAndreas.Sandberg@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 199651SAndreas.Sandberg@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 209651SAndreas.Sandberg@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 219651SAndreas.Sandberg@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 229651SAndreas.Sandberg@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 239651SAndreas.Sandberg@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 249651SAndreas.Sandberg@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 259651SAndreas.Sandberg@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 269651SAndreas.Sandberg@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 279651SAndreas.Sandberg@ARM.com * 289651SAndreas.Sandberg@ARM.com * Authors: Ali Saidi 299651SAndreas.Sandberg@ARM.com * Andrew Schultz 309651SAndreas.Sandberg@ARM.com */ 319651SAndreas.Sandberg@ARM.com 329651SAndreas.Sandberg@ARM.com/** @file 339651SAndreas.Sandberg@ARM.com * Tsunami PChip (pci) 349651SAndreas.Sandberg@ARM.com */ 359651SAndreas.Sandberg@ARM.com 369651SAndreas.Sandberg@ARM.com#include <deque> 379651SAndreas.Sandberg@ARM.com#include <string> 389651SAndreas.Sandberg@ARM.com#include <vector> 399651SAndreas.Sandberg@ARM.com 409651SAndreas.Sandberg@ARM.com#include "base/trace.hh" 419651SAndreas.Sandberg@ARM.com#include "dev/tsunami_pchip.hh" 429651SAndreas.Sandberg@ARM.com#include "dev/tsunamireg.h" 439651SAndreas.Sandberg@ARM.com#include "dev/tsunami.hh" 449651SAndreas.Sandberg@ARM.com#include "mem/packet.hh" 459651SAndreas.Sandberg@ARM.com#include "sim/builder.hh" 469651SAndreas.Sandberg@ARM.com#include "sim/system.hh" 479651SAndreas.Sandberg@ARM.com 489651SAndreas.Sandberg@ARM.comusing namespace std; 499883Sandreas@sandberg.pp.se//Should this be AlphaISA? 509651SAndreas.Sandberg@ARM.comusing namespace TheISA; 519651SAndreas.Sandberg@ARM.com 529651SAndreas.Sandberg@ARM.comTsunamiPChip::TsunamiPChip(Params *p) 539651SAndreas.Sandberg@ARM.com: BasicPioDevice(p) 549651SAndreas.Sandberg@ARM.com{ 559651SAndreas.Sandberg@ARM.com pioSize = 0xfff; 569651SAndreas.Sandberg@ARM.com 579651SAndreas.Sandberg@ARM.com for (int i = 0; i < 4; i++) { 589651SAndreas.Sandberg@ARM.com wsba[i] = 0; 599651SAndreas.Sandberg@ARM.com wsm[i] = 0; 609651SAndreas.Sandberg@ARM.com tba[i] = 0; 619651SAndreas.Sandberg@ARM.com } 629651SAndreas.Sandberg@ARM.com 639651SAndreas.Sandberg@ARM.com // initialize pchip control register 649651SAndreas.Sandberg@ARM.com pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36); 659651SAndreas.Sandberg@ARM.com 669651SAndreas.Sandberg@ARM.com //Set back pointer in tsunami 679651SAndreas.Sandberg@ARM.com p->tsunami->pchip = this; 689651SAndreas.Sandberg@ARM.com} 699651SAndreas.Sandberg@ARM.com 709651SAndreas.Sandberg@ARM.comTick 719651SAndreas.Sandberg@ARM.comTsunamiPChip::read(Packet *pkt) 729651SAndreas.Sandberg@ARM.com{ 739651SAndreas.Sandberg@ARM.com assert(pkt->result == Packet::Unknown); 749651SAndreas.Sandberg@ARM.com assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 759651SAndreas.Sandberg@ARM.com 769651SAndreas.Sandberg@ARM.com pkt->allocate(); 779651SAndreas.Sandberg@ARM.com Addr daddr = (pkt->getAddr() - pioAddr) >> 6;; 789651SAndreas.Sandberg@ARM.com assert(pkt->getSize() == sizeof(uint64_t)); 799651SAndreas.Sandberg@ARM.com 809651SAndreas.Sandberg@ARM.com 819651SAndreas.Sandberg@ARM.com DPRINTF(Tsunami, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); 829651SAndreas.Sandberg@ARM.com 839651SAndreas.Sandberg@ARM.com switch(daddr) { 849651SAndreas.Sandberg@ARM.com case TSDEV_PC_WSBA0: 859651SAndreas.Sandberg@ARM.com pkt->set(wsba[0]); 869651SAndreas.Sandberg@ARM.com break; 879651SAndreas.Sandberg@ARM.com case TSDEV_PC_WSBA1: 889651SAndreas.Sandberg@ARM.com pkt->set(wsba[1]); 899651SAndreas.Sandberg@ARM.com break; 909651SAndreas.Sandberg@ARM.com case TSDEV_PC_WSBA2: 919651SAndreas.Sandberg@ARM.com pkt->set(wsba[2]); 929651SAndreas.Sandberg@ARM.com break; 939651SAndreas.Sandberg@ARM.com case TSDEV_PC_WSBA3: 949651SAndreas.Sandberg@ARM.com pkt->set(wsba[3]); 959651SAndreas.Sandberg@ARM.com break; 969651SAndreas.Sandberg@ARM.com case TSDEV_PC_WSM0: 979651SAndreas.Sandberg@ARM.com pkt->set(wsm[0]); 989651SAndreas.Sandberg@ARM.com break; 999651SAndreas.Sandberg@ARM.com case TSDEV_PC_WSM1: 1009651SAndreas.Sandberg@ARM.com pkt->set(wsm[1]); 1019651SAndreas.Sandberg@ARM.com break; 1029651SAndreas.Sandberg@ARM.com case TSDEV_PC_WSM2: 1039651SAndreas.Sandberg@ARM.com pkt->set(wsm[2]); 1049651SAndreas.Sandberg@ARM.com break; 1059651SAndreas.Sandberg@ARM.com case TSDEV_PC_WSM3: 1069651SAndreas.Sandberg@ARM.com pkt->set(wsm[3]); 1079651SAndreas.Sandberg@ARM.com break; 1089651SAndreas.Sandberg@ARM.com case TSDEV_PC_TBA0: 1099651SAndreas.Sandberg@ARM.com pkt->set(tba[0]); 1109651SAndreas.Sandberg@ARM.com break; 1119651SAndreas.Sandberg@ARM.com case TSDEV_PC_TBA1: 1129651SAndreas.Sandberg@ARM.com pkt->set(tba[1]); 1139651SAndreas.Sandberg@ARM.com break; 1149651SAndreas.Sandberg@ARM.com case TSDEV_PC_TBA2: 1159651SAndreas.Sandberg@ARM.com pkt->set(tba[2]); 1169651SAndreas.Sandberg@ARM.com break; 1179651SAndreas.Sandberg@ARM.com case TSDEV_PC_TBA3: 1189651SAndreas.Sandberg@ARM.com pkt->set(tba[3]); 1199651SAndreas.Sandberg@ARM.com break; 1209651SAndreas.Sandberg@ARM.com case TSDEV_PC_PCTL: 1219651SAndreas.Sandberg@ARM.com pkt->set(pctl); 1229651SAndreas.Sandberg@ARM.com break; 1239651SAndreas.Sandberg@ARM.com case TSDEV_PC_PLAT: 1249651SAndreas.Sandberg@ARM.com panic("PC_PLAT not implemented\n"); 1259651SAndreas.Sandberg@ARM.com case TSDEV_PC_RES: 1269651SAndreas.Sandberg@ARM.com panic("PC_RES not implemented\n"); 1279651SAndreas.Sandberg@ARM.com case TSDEV_PC_PERROR: 12810605Sgabeblack@google.com pkt->set((uint64_t)0x00); 12910605Sgabeblack@google.com break; 13010605Sgabeblack@google.com case TSDEV_PC_PERRMASK: 13110605Sgabeblack@google.com pkt->set((uint64_t)0x00); 13210605Sgabeblack@google.com break; 13310605Sgabeblack@google.com case TSDEV_PC_PERRSET: 13410605Sgabeblack@google.com panic("PC_PERRSET not implemented\n"); 13510605Sgabeblack@google.com case TSDEV_PC_TLBIV: 13610605Sgabeblack@google.com panic("PC_TLBIV not implemented\n"); 13710605Sgabeblack@google.com case TSDEV_PC_TLBIA: 1389651SAndreas.Sandberg@ARM.com pkt->set((uint64_t)0x00); // shouldn't be readable, but linux 1399651SAndreas.Sandberg@ARM.com break; 1409651SAndreas.Sandberg@ARM.com case TSDEV_PC_PMONCTL: 1419651SAndreas.Sandberg@ARM.com panic("PC_PMONCTL not implemented\n"); 1429651SAndreas.Sandberg@ARM.com case TSDEV_PC_PMONCNT: 1439651SAndreas.Sandberg@ARM.com panic("PC_PMONCTN not implemented\n"); 1449651SAndreas.Sandberg@ARM.com default: 1459651SAndreas.Sandberg@ARM.com panic("Default in PChip Read reached reading 0x%x\n", daddr); 1469651SAndreas.Sandberg@ARM.com } 1479651SAndreas.Sandberg@ARM.com pkt->result = Packet::Success; 1489651SAndreas.Sandberg@ARM.com return pioDelay; 1499651SAndreas.Sandberg@ARM.com 1509651SAndreas.Sandberg@ARM.com} 1519651SAndreas.Sandberg@ARM.com 1529651SAndreas.Sandberg@ARM.comTick 1539651SAndreas.Sandberg@ARM.comTsunamiPChip::write(Packet *pkt) 1549651SAndreas.Sandberg@ARM.com{ 1559883Sandreas@sandberg.pp.se assert(pkt->result == Packet::Unknown); 1569883Sandreas@sandberg.pp.se assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 1579883Sandreas@sandberg.pp.se Addr daddr = (pkt->getAddr() - pioAddr) >> 6; 1589883Sandreas@sandberg.pp.se 1599883Sandreas@sandberg.pp.se assert(pkt->getSize() == sizeof(uint64_t)); 1609883Sandreas@sandberg.pp.se 1619883Sandreas@sandberg.pp.se DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize()); 1629883Sandreas@sandberg.pp.se 1639883Sandreas@sandberg.pp.se switch(daddr) { 1649883Sandreas@sandberg.pp.se case TSDEV_PC_WSBA0: 1659883Sandreas@sandberg.pp.se wsba[0] = pkt->get<uint64_t>(); 1669883Sandreas@sandberg.pp.se break; 1679883Sandreas@sandberg.pp.se case TSDEV_PC_WSBA1: 1689883Sandreas@sandberg.pp.se wsba[1] = pkt->get<uint64_t>(); 1699883Sandreas@sandberg.pp.se break; 1709883Sandreas@sandberg.pp.se case TSDEV_PC_WSBA2: 1719883Sandreas@sandberg.pp.se wsba[2] = pkt->get<uint64_t>(); 1729883Sandreas@sandberg.pp.se break; 1739883Sandreas@sandberg.pp.se case TSDEV_PC_WSBA3: 1749883Sandreas@sandberg.pp.se wsba[3] = pkt->get<uint64_t>(); 1759883Sandreas@sandberg.pp.se break; 1769883Sandreas@sandberg.pp.se case TSDEV_PC_WSM0: 1779883Sandreas@sandberg.pp.se wsm[0] = pkt->get<uint64_t>(); 1789883Sandreas@sandberg.pp.se break; 1799883Sandreas@sandberg.pp.se case TSDEV_PC_WSM1: 1809883Sandreas@sandberg.pp.se wsm[1] = pkt->get<uint64_t>(); 1819883Sandreas@sandberg.pp.se break; 1829883Sandreas@sandberg.pp.se case TSDEV_PC_WSM2: 1839883Sandreas@sandberg.pp.se wsm[2] = pkt->get<uint64_t>(); 1849883Sandreas@sandberg.pp.se break; 1859883Sandreas@sandberg.pp.se case TSDEV_PC_WSM3: 1869883Sandreas@sandberg.pp.se wsm[3] = pkt->get<uint64_t>(); 1879883Sandreas@sandberg.pp.se break; 1889883Sandreas@sandberg.pp.se case TSDEV_PC_TBA0: 1899883Sandreas@sandberg.pp.se tba[0] = pkt->get<uint64_t>(); 1909883Sandreas@sandberg.pp.se break; 1919883Sandreas@sandberg.pp.se case TSDEV_PC_TBA1: 1929883Sandreas@sandberg.pp.se tba[1] = pkt->get<uint64_t>(); 1939883Sandreas@sandberg.pp.se break; 19410842Sandreas.sandberg@arm.com case TSDEV_PC_TBA2: 19510842Sandreas.sandberg@arm.com tba[2] = pkt->get<uint64_t>(); 1969883Sandreas@sandberg.pp.se break; 1979651SAndreas.Sandberg@ARM.com case TSDEV_PC_TBA3: 1989651SAndreas.Sandberg@ARM.com tba[3] = pkt->get<uint64_t>(); 1999651SAndreas.Sandberg@ARM.com break; 2009651SAndreas.Sandberg@ARM.com case TSDEV_PC_PCTL: 2019651SAndreas.Sandberg@ARM.com pctl = pkt->get<uint64_t>(); 2029651SAndreas.Sandberg@ARM.com break; 2039651SAndreas.Sandberg@ARM.com case TSDEV_PC_PLAT: 2049651SAndreas.Sandberg@ARM.com panic("PC_PLAT not implemented\n"); 2059651SAndreas.Sandberg@ARM.com case TSDEV_PC_RES: 2069651SAndreas.Sandberg@ARM.com panic("PC_RES not implemented\n"); 2079651SAndreas.Sandberg@ARM.com case TSDEV_PC_PERROR: 2089883Sandreas@sandberg.pp.se break; 2099883Sandreas@sandberg.pp.se case TSDEV_PC_PERRMASK: 2109883Sandreas@sandberg.pp.se panic("PC_PERRMASK not implemented\n"); 2119883Sandreas@sandberg.pp.se case TSDEV_PC_PERRSET: 2129883Sandreas@sandberg.pp.se panic("PC_PERRSET not implemented\n"); 2139883Sandreas@sandberg.pp.se case TSDEV_PC_TLBIV: 2149883Sandreas@sandberg.pp.se panic("PC_TLBIV not implemented\n"); 2159883Sandreas@sandberg.pp.se case TSDEV_PC_TLBIA: 2169883Sandreas@sandberg.pp.se break; // value ignored, supposted to invalidate SG TLB 2179883Sandreas@sandberg.pp.se case TSDEV_PC_PMONCTL: 2189883Sandreas@sandberg.pp.se panic("PC_PMONCTL not implemented\n"); 2199883Sandreas@sandberg.pp.se case TSDEV_PC_PMONCNT: 2209883Sandreas@sandberg.pp.se panic("PC_PMONCTN not implemented\n"); 2219883Sandreas@sandberg.pp.se default: 2229883Sandreas@sandberg.pp.se panic("Default in PChip write reached reading 0x%x\n", daddr); 2239883Sandreas@sandberg.pp.se 2249883Sandreas@sandberg.pp.se } // uint64_t 2259883Sandreas@sandberg.pp.se 2269883Sandreas@sandberg.pp.se pkt->result = Packet::Success; 2279883Sandreas@sandberg.pp.se return pioDelay; 2289883Sandreas@sandberg.pp.se} 2299883Sandreas@sandberg.pp.se 2309883Sandreas@sandberg.pp.se#define DMA_ADDR_MASK ULL(0x3ffffffff) 2319883Sandreas@sandberg.pp.se 2329883Sandreas@sandberg.pp.seAddr 2339883Sandreas@sandberg.pp.seTsunamiPChip::translatePciToDma(Addr busAddr) 2349883Sandreas@sandberg.pp.se{ 2359883Sandreas@sandberg.pp.se // compare the address to the window base registers 2369883Sandreas@sandberg.pp.se uint64_t tbaMask = 0; 2379883Sandreas@sandberg.pp.se uint64_t baMask = 0; 2389883Sandreas@sandberg.pp.se 2399883Sandreas@sandberg.pp.se uint64_t windowMask = 0; 2409883Sandreas@sandberg.pp.se uint64_t windowBase = 0; 2419883Sandreas@sandberg.pp.se 2429883Sandreas@sandberg.pp.se uint64_t pteEntry = 0; 2439883Sandreas@sandberg.pp.se 2449883Sandreas@sandberg.pp.se Addr pteAddr; 2459883Sandreas@sandberg.pp.se Addr dmaAddr; 2469883Sandreas@sandberg.pp.se 2479883Sandreas@sandberg.pp.se#if 0 2489883Sandreas@sandberg.pp.se DPRINTF(IdeDisk, "Translation for bus address: %#x\n", busAddr); 2499883Sandreas@sandberg.pp.se for (int i = 0; i < 4; i++) { 2509883Sandreas@sandberg.pp.se DPRINTF(IdeDisk, "(%d) base:%#x mask:%#x\n", 2519883Sandreas@sandberg.pp.se i, wsba[i], wsm[i]); 2529883Sandreas@sandberg.pp.se 2539883Sandreas@sandberg.pp.se windowBase = wsba[i]; 2549883Sandreas@sandberg.pp.se windowMask = ~wsm[i] & (ULL(0xfff) << 20); 2559883Sandreas@sandberg.pp.se 2569883Sandreas@sandberg.pp.se if ((busAddr & windowMask) == (windowBase & windowMask)) { 2579883Sandreas@sandberg.pp.se DPRINTF(IdeDisk, "Would have matched %d (wb:%#x wm:%#x --> ba&wm:%#x wb&wm:%#x)\n", 2589883Sandreas@sandberg.pp.se i, windowBase, windowMask, (busAddr & windowMask), 25910842Sandreas.sandberg@arm.com (windowBase & windowMask)); 26010842Sandreas.sandberg@arm.com } 26110842Sandreas.sandberg@arm.com } 2629651SAndreas.Sandberg@ARM.com#endif 2639651SAndreas.Sandberg@ARM.com 2649651SAndreas.Sandberg@ARM.com for (int i = 0; i < 4; i++) { 2659651SAndreas.Sandberg@ARM.com 2669651SAndreas.Sandberg@ARM.com windowBase = wsba[i]; 2679651SAndreas.Sandberg@ARM.com windowMask = ~wsm[i] & (ULL(0xfff) << 20); 2689651SAndreas.Sandberg@ARM.com 2699651SAndreas.Sandberg@ARM.com if ((busAddr & windowMask) == (windowBase & windowMask)) { 2709651SAndreas.Sandberg@ARM.com 2719651SAndreas.Sandberg@ARM.com if (wsba[i] & 0x1) { // see if enabled 2729651SAndreas.Sandberg@ARM.com if (wsba[i] & 0x2) { // see if SG bit is set 2739651SAndreas.Sandberg@ARM.com /** @todo 2749651SAndreas.Sandberg@ARM.com This currently is faked by just doing a direct 2759651SAndreas.Sandberg@ARM.com read from memory, however, to be realistic, this 2769651SAndreas.Sandberg@ARM.com needs to actually do a bus transaction. The process 2779651SAndreas.Sandberg@ARM.com is explained in the tsunami documentation on page 2789651SAndreas.Sandberg@ARM.com 10-12 and basically munges the address to look up a 2799651SAndreas.Sandberg@ARM.com PTE from a table in memory and then uses that mapping 2809651SAndreas.Sandberg@ARM.com to create an address for the SG page 2819651SAndreas.Sandberg@ARM.com */ 2829651SAndreas.Sandberg@ARM.com 2839651SAndreas.Sandberg@ARM.com tbaMask = ~(((wsm[i] & (ULL(0xfff) << 20)) >> 10) | ULL(0x3ff)); 2849651SAndreas.Sandberg@ARM.com baMask = (wsm[i] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13); 2859651SAndreas.Sandberg@ARM.com pteAddr = (tba[i] & tbaMask) | ((busAddr & baMask) >> 10); 2869651SAndreas.Sandberg@ARM.com 2879651SAndreas.Sandberg@ARM.com pioPort->readBlob(pteAddr, (uint8_t*)&pteEntry, sizeof(uint64_t)); 2889651SAndreas.Sandberg@ARM.com 2899651SAndreas.Sandberg@ARM.com dmaAddr = ((pteEntry & ~ULL(0x1)) << 12) | (busAddr & ULL(0x1fff)); 2909651SAndreas.Sandberg@ARM.com 2919651SAndreas.Sandberg@ARM.com } else { 2929651SAndreas.Sandberg@ARM.com baMask = (wsm[i] & (ULL(0xfff) << 20)) | ULL(0xfffff); 2939651SAndreas.Sandberg@ARM.com tbaMask = ~baMask; 2949651SAndreas.Sandberg@ARM.com dmaAddr = (tba[i] & tbaMask) | (busAddr & baMask); 2959651SAndreas.Sandberg@ARM.com } 2969651SAndreas.Sandberg@ARM.com 2979651SAndreas.Sandberg@ARM.com return (dmaAddr & DMA_ADDR_MASK); 2989651SAndreas.Sandberg@ARM.com } 29910605Sgabeblack@google.com } 30010605Sgabeblack@google.com } 30110605Sgabeblack@google.com 30210605Sgabeblack@google.com // if no match was found, then return the original address 3039651SAndreas.Sandberg@ARM.com return busAddr; 3049651SAndreas.Sandberg@ARM.com} 3059651SAndreas.Sandberg@ARM.comAddr 3069651SAndreas.Sandberg@ARM.comTsunamiPChip::calcConfigAddr(int bus, int dev, int func) 3079651SAndreas.Sandberg@ARM.com{ 3089651SAndreas.Sandberg@ARM.com assert(func < 8); 3099651SAndreas.Sandberg@ARM.com assert(dev < 32); 3109651SAndreas.Sandberg@ARM.com assert(bus == 0); 3119651SAndreas.Sandberg@ARM.com 3129651SAndreas.Sandberg@ARM.com return TsunamiPciBus0Config | (func << 8) | (dev << 11); 3139651SAndreas.Sandberg@ARM.com} 3149651SAndreas.Sandberg@ARM.com 3159651SAndreas.Sandberg@ARM.com 3169651SAndreas.Sandberg@ARM.com 3179651SAndreas.Sandberg@ARM.comvoid 3189651SAndreas.Sandberg@ARM.comTsunamiPChip::serialize(std::ostream &os) 3199651SAndreas.Sandberg@ARM.com{ 3209651SAndreas.Sandberg@ARM.com SERIALIZE_SCALAR(pctl); 3219651SAndreas.Sandberg@ARM.com SERIALIZE_ARRAY(wsba, 4); 3229651SAndreas.Sandberg@ARM.com SERIALIZE_ARRAY(wsm, 4); 3239651SAndreas.Sandberg@ARM.com SERIALIZE_ARRAY(tba, 4); 3249651SAndreas.Sandberg@ARM.com} 3259651SAndreas.Sandberg@ARM.com 3269651SAndreas.Sandberg@ARM.comvoid 3279651SAndreas.Sandberg@ARM.comTsunamiPChip::unserialize(Checkpoint *cp, const std::string §ion) 3289651SAndreas.Sandberg@ARM.com{ 3299651SAndreas.Sandberg@ARM.com UNSERIALIZE_SCALAR(pctl); 3309651SAndreas.Sandberg@ARM.com UNSERIALIZE_ARRAY(wsba, 4); 3319651SAndreas.Sandberg@ARM.com UNSERIALIZE_ARRAY(wsm, 4); 3329651SAndreas.Sandberg@ARM.com UNSERIALIZE_ARRAY(tba, 4); 3339651SAndreas.Sandberg@ARM.com} 3349651SAndreas.Sandberg@ARM.com 3359651SAndreas.Sandberg@ARM.com 3369651SAndreas.Sandberg@ARM.comBEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip) 3379651SAndreas.Sandberg@ARM.com 33810605Sgabeblack@google.com Param<Addr> pio_addr; 33910605Sgabeblack@google.com Param<Tick> pio_latency; 34010605Sgabeblack@google.com SimObjectParam<Platform *> platform; 34110605Sgabeblack@google.com SimObjectParam<System *> system; 34210605Sgabeblack@google.com SimObjectParam<Tsunami *> tsunami; 34310605Sgabeblack@google.com 34410605Sgabeblack@google.comEND_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip) 3459651SAndreas.Sandberg@ARM.com 3469651SAndreas.Sandberg@ARM.comBEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip) 3479651SAndreas.Sandberg@ARM.com 3489651SAndreas.Sandberg@ARM.com INIT_PARAM(pio_addr, "Device Address"), 3499651SAndreas.Sandberg@ARM.com INIT_PARAM(pio_latency, "Programmed IO latency"), 3509651SAndreas.Sandberg@ARM.com INIT_PARAM(platform, "platform"), 3519651SAndreas.Sandberg@ARM.com INIT_PARAM(system, "system object"), 35210605Sgabeblack@google.com INIT_PARAM(tsunami, "Tsunami") 35310605Sgabeblack@google.com 35410605Sgabeblack@google.comEND_INIT_SIM_OBJECT_PARAMS(TsunamiPChip) 35510605Sgabeblack@google.com 35610605Sgabeblack@google.comCREATE_SIM_OBJECT(TsunamiPChip) 35710605Sgabeblack@google.com{ 35810605Sgabeblack@google.com TsunamiPChip::Params *p = new TsunamiPChip::Params; 35910605Sgabeblack@google.com p->name = getInstanceName(); 36010605Sgabeblack@google.com p->pio_addr = pio_addr; 36110605Sgabeblack@google.com p->pio_delay = pio_latency; 36210605Sgabeblack@google.com p->platform = platform; 36310605Sgabeblack@google.com p->system = system; 36410605Sgabeblack@google.com p->tsunami = tsunami; 36510605Sgabeblack@google.com return new TsunamiPChip(p); 36610605Sgabeblack@google.com} 36710605Sgabeblack@google.com 36810605Sgabeblack@google.comREGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip) 36910605Sgabeblack@google.com