tsunami_io.hh revision 3943:68e673d2db04
12623SN/A/* 22623SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32623SN/A * All rights reserved. 42623SN/A * 52623SN/A * Redistribution and use in source and binary forms, with or without 62623SN/A * modification, are permitted provided that the following conditions are 72623SN/A * met: redistributions of source code must retain the above copyright 82623SN/A * notice, this list of conditions and the following disclaimer; 92623SN/A * redistributions in binary form must reproduce the above copyright 102623SN/A * notice, this list of conditions and the following disclaimer in the 112623SN/A * documentation and/or other materials provided with the distribution; 122623SN/A * neither the name of the copyright holders nor the names of its 132623SN/A * contributors may be used to endorse or promote products derived from 142623SN/A * this software without specific prior written permission. 152623SN/A * 162623SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192623SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252623SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Ali Saidi 292623SN/A * Andrew Schultz 302623SN/A * Miguel Serrano 313170Sstever@eecs.umich.edu */ 322623SN/A 332623SN/A/** @file 342623SN/A * Tsunami I/O Space mapping including RTC/timer interrupts 352623SN/A */ 362623SN/A 372901Ssaidi@eecs.umich.edu#ifndef __DEV_TSUNAMI_IO_HH__ 382623SN/A#define __DEV_TSUNAMI_IO_HH__ 392623SN/A 402623SN/A#include "dev/io_device.hh" 412623SN/A#include "base/range.hh" 422623SN/A#include "dev/alpha/tsunami.hh" 432623SN/A#include "sim/eventq.hh" 442623SN/A 452623SN/A/** 462623SN/A * Tsunami I/O device is a catch all for all the south bridge stuff we care 472623SN/A * to implement. 482623SN/A */ 492623SN/Aclass TsunamiIO : public BasicPioDevice 502623SN/A{ 512623SN/A private: 522623SN/A struct tm tm; 532623SN/A 542623SN/A protected: 552623SN/A /** Real-Time Clock (MC146818) */ 562623SN/A class RTC 572623SN/A { 582623SN/A private: 592623SN/A /** Event for RTC periodic interrupt */ 602856Srdreslin@umich.edu struct RTCEvent : public Event 612856Srdreslin@umich.edu { 622856Srdreslin@umich.edu /** A pointer back to tsunami to create interrupt the processor. */ 632856Srdreslin@umich.edu Tsunami* tsunami; 642856Srdreslin@umich.edu Tick interval; 652856Srdreslin@umich.edu 662856Srdreslin@umich.edu RTCEvent(Tsunami* t, Tick i); 672856Srdreslin@umich.edu 682856Srdreslin@umich.edu /** Schedule the RTC periodic interrupt */ 692856Srdreslin@umich.edu void scheduleIntr(); 702623SN/A 712623SN/A /** Event process to occur at interrupt*/ 722623SN/A virtual void process(); 732623SN/A 742623SN/A /** Event description */ 752856Srdreslin@umich.edu virtual const char *description(); 762856Srdreslin@umich.edu }; 772856Srdreslin@umich.edu 782623SN/A private: 792856Srdreslin@umich.edu std::string _name; 802856Srdreslin@umich.edu const std::string &name() const { return _name; } 812856Srdreslin@umich.edu 822623SN/A /** RTC periodic interrupt event */ 832623SN/A RTCEvent event; 842623SN/A 852680Sktlim@umich.edu /** Current RTC register address/index */ 862680Sktlim@umich.edu int addr; 872623SN/A 882623SN/A /** should the year be interpreted as BCD? */ 892680Sktlim@umich.edu bool year_is_bcd; 902623SN/A 912623SN/A /** Data for real-time clock function */ 922623SN/A union { 932623SN/A uint8_t clock_data[10]; 942623SN/A 952630SN/A struct { 962623SN/A uint8_t sec; 972623SN/A uint8_t sec_alrm; 982623SN/A uint8_t min; 992623SN/A uint8_t min_alrm; 1002623SN/A uint8_t hour; 1012623SN/A uint8_t hour_alrm; 1022630SN/A uint8_t wday; 1032623SN/A uint8_t mday; 1042623SN/A uint8_t mon; 1052623SN/A uint8_t year; 1062623SN/A }; 1072623SN/A }; 1082623SN/A 1092630SN/A /** RTC status register A */ 1102623SN/A uint8_t stat_regA; 1112623SN/A 1122623SN/A /** RTC status register B */ 1132623SN/A uint8_t stat_regB; 1142623SN/A 1152623SN/A public: 1162623SN/A RTC(const std::string &name, Tsunami* tsunami, 1172626SN/A const std::vector<int> &t, bool bcd, Tick i); 1182626SN/A 1192626SN/A /** RTC address port: write address of RTC RAM data to access */ 1202623SN/A void writeAddr(const uint8_t data); 1212623SN/A 1222623SN/A /** RTC write data */ 1232657Ssaidi@eecs.umich.edu void writeData(const uint8_t data); 1242623SN/A 1252623SN/A /** RTC read data */ 1262623SN/A uint8_t readData(); 1272623SN/A 1282623SN/A /** 1292623SN/A * Serialize this object to the given output stream. 1302623SN/A * @param base The base name of the counter object. 1312623SN/A * @param os The stream to serialize to. 1322623SN/A */ 1332640Sstever@eecs.umich.edu void serialize(const std::string &base, std::ostream &os); 1342623SN/A 1352623SN/A /** 1362623SN/A * Reconstruct the state of this object from a checkpoint. 1372663Sstever@eecs.umich.edu * @param base The base name of the counter object. 1383170Sstever@eecs.umich.edu * @param cp The checkpoint use. 1392641Sstever@eecs.umich.edu * @param section The section name of this object 1402623SN/A */ 1412623SN/A void unserialize(const std::string &base, Checkpoint *cp, 1422663Sstever@eecs.umich.edu const std::string §ion); 1433170Sstever@eecs.umich.edu }; 1442641Sstever@eecs.umich.edu 1452641Sstever@eecs.umich.edu /** Programmable Interval Timer (Intel 8254) */ 1462623SN/A class PITimer 1472623SN/A { 1482663Sstever@eecs.umich.edu /** Counter element for PIT */ 1493170Sstever@eecs.umich.edu class Counter 1502641Sstever@eecs.umich.edu { 1512641Sstever@eecs.umich.edu /** Event for counter interrupt */ 1522623SN/A class CounterEvent : public Event 1532623SN/A { 1542623SN/A private: 1552623SN/A /** Pointer back to Counter */ 1562623SN/A Counter* counter; 1572623SN/A Tick interval; 1582623SN/A 1592623SN/A public: 1602623SN/A CounterEvent(Counter*); 1612623SN/A 1622915Sktlim@umich.edu /** Event process */ 1632915Sktlim@umich.edu virtual void process(); 1643145Shsul@eecs.umich.edu 1652623SN/A /** Event description */ 1662623SN/A virtual const char *description(); 1672623SN/A 1682623SN/A friend class Counter; 1692623SN/A }; 1702623SN/A 1712623SN/A private: 1722915Sktlim@umich.edu std::string _name; 1732915Sktlim@umich.edu const std::string &name() const { return _name; } 1743145Shsul@eecs.umich.edu 1752915Sktlim@umich.edu CounterEvent event; 1762915Sktlim@umich.edu 1772915Sktlim@umich.edu /** Current count value */ 1782915Sktlim@umich.edu uint16_t count; 1792915Sktlim@umich.edu 1802915Sktlim@umich.edu /** Latched count */ 1812926Sktlim@umich.edu uint16_t latched_count; 1822926Sktlim@umich.edu 1832915Sktlim@umich.edu /** Interrupt period */ 1842915Sktlim@umich.edu uint16_t period; 1852915Sktlim@umich.edu 1862915Sktlim@umich.edu /** Current mode of operation */ 1872623SN/A uint8_t mode; 1882623SN/A 1892623SN/A /** Output goes high when the counter reaches zero */ 1902798Sktlim@umich.edu bool output_high; 1912623SN/A 1922798Sktlim@umich.edu /** State of the count latch */ 1932798Sktlim@umich.edu bool latch_on; 1942623SN/A 1952798Sktlim@umich.edu /** Set of values for read_byte and write_byte */ 1962623SN/A enum {LSB, MSB}; 1972623SN/A 1982623SN/A /** Determine which byte of a 16-bit count value to read/write */ 1992623SN/A uint8_t read_byte, write_byte; 2002623SN/A 2012623SN/A public: 2022623SN/A Counter(const std::string &name); 2032623SN/A 2042623SN/A /** Latch the current count (if one is not already latched) */ 2052623SN/A void latchCount(); 2062680Sktlim@umich.edu 2072623SN/A /** Set the read/write mode */ 2082680Sktlim@umich.edu void setRW(int rw_val); 2092680Sktlim@umich.edu 2102680Sktlim@umich.edu /** Set operational mode */ 2112623SN/A void setMode(int mode_val); 2122623SN/A 2132623SN/A /** Set count encoding */ 2142623SN/A void setBCD(int bcd_val); 2152623SN/A 2162623SN/A /** Read a count byte */ 2172623SN/A uint8_t read(); 2182623SN/A 2192623SN/A /** Write a count byte */ 2202623SN/A void write(const uint8_t data); 2212623SN/A 2222623SN/A /** Is the output high? */ 2232683Sktlim@umich.edu bool outputHigh(); 2242623SN/A 2252623SN/A /** 2262623SN/A * Serialize this object to the given output stream. 2272623SN/A * @param base The base name of the counter object. 2282623SN/A * @param os The stream to serialize to. 2292623SN/A */ 2302623SN/A void serialize(const std::string &base, std::ostream &os); 2312623SN/A 2322623SN/A /** 2332623SN/A * Reconstruct the state of this object from a checkpoint. 2342623SN/A * @param base The base name of the counter object. 2352623SN/A * @param cp The checkpoint use. 2362623SN/A * @param section The section name of this object 2372623SN/A */ 2382683Sktlim@umich.edu void unserialize(const std::string &base, Checkpoint *cp, 2392623SN/A const std::string §ion); 2402623SN/A }; 2412626SN/A 2422626SN/A private: 2432626SN/A std::string _name; 2442626SN/A const std::string &name() const { return _name; } 2452626SN/A 2462623SN/A /** PIT has three seperate counters */ 2472623SN/A Counter *counter[3]; 2482623SN/A 2492623SN/A public: 2502623SN/A /** Public way to access individual counters (avoid array accesses) */ 2512623SN/A Counter counter0; 2522623SN/A Counter counter1; 2532623SN/A Counter counter2; 2542623SN/A 2552623SN/A PITimer(const std::string &name); 2563169Sstever@eecs.umich.edu 2573169Sstever@eecs.umich.edu /** Write control word */ 2583169Sstever@eecs.umich.edu void writeControl(const uint8_t data); 2593169Sstever@eecs.umich.edu 2603169Sstever@eecs.umich.edu /** 2612623SN/A * Serialize this object to the given output stream. 2622623SN/A * @param base The base name of the counter object. 2632623SN/A * @param os The stream to serialize to. 2642623SN/A */ 2652623SN/A void serialize(const std::string &base, std::ostream &os); 2662623SN/A 2673169Sstever@eecs.umich.edu /** 2682623SN/A * Reconstruct the state of this object from a checkpoint. 2692623SN/A * @param base The base name of the counter object. 2702623SN/A * @param cp The checkpoint use. 2713169Sstever@eecs.umich.edu * @param section The section name of this object 2722623SN/A */ 2733169Sstever@eecs.umich.edu void unserialize(const std::string &base, Checkpoint *cp, 2742623SN/A const std::string §ion); 2752623SN/A }; 2763169Sstever@eecs.umich.edu 2773169Sstever@eecs.umich.edu /** Mask of the PIC1 */ 2783170Sstever@eecs.umich.edu uint8_t mask1; 2793170Sstever@eecs.umich.edu 2803170Sstever@eecs.umich.edu /** Mask of the PIC2 */ 2813170Sstever@eecs.umich.edu uint8_t mask2; 2822623SN/A 2832623SN/A /** Mode of PIC1. Not used for anything */ 2842623SN/A uint8_t mode1; 2853169Sstever@eecs.umich.edu 2862623SN/A /** Mode of PIC2. Not used for anything */ 2872623SN/A uint8_t mode2; 2882623SN/A 2892623SN/A /** Raw PIC interrupt register before masking */ 2902623SN/A uint8_t picr; //Raw PIC interrput register 2912623SN/A 2922623SN/A /** Is the pic interrupting right now or not. */ 2932623SN/A bool picInterrupting; 2942623SN/A 2952623SN/A /** A pointer to the Tsunami device which be belong to */ 2962623SN/A Tsunami *tsunami; 2972623SN/A 2982623SN/A /** Intel 8253 Periodic Interval Timer */ 2992623SN/A PITimer pitimer; 3002623SN/A 3012623SN/A RTC rtc; 3022623SN/A 3032623SN/A /** The interval is set via two writes to the PIT. 3042623SN/A * This variable contains a flag as to how many writes have happened, and 3052623SN/A * the time so far. 3062623SN/A */ 3072623SN/A uint16_t timerData; 3082623SN/A 3092623SN/A public: 3102623SN/A /** 3112623SN/A * Return the freqency of the RTC 3122623SN/A * @return interrupt rate of the RTC 3132623SN/A */ 3142623SN/A Tick frequency() const; 3152623SN/A 3162623SN/A struct Params : public BasicPioDevice::Params 3172623SN/A { 3182623SN/A Tick frequency; 3192623SN/A Tsunami *tsunami; 3202623SN/A std::vector<int> init_time; 3212623SN/A bool year_is_bcd; 3222623SN/A }; 3232623SN/A 3242623SN/A protected: 3252623SN/A const Params *params() const { return (const Params*)_params; } 3262623SN/A 3272623SN/A public: 3282623SN/A /** 3292623SN/A * Initialize all the data for devices supported by Tsunami I/O. 3302623SN/A * @param p pointer to Params struct 3312623SN/A */ 3322623SN/A TsunamiIO(Params *p); 3332623SN/A 3342623SN/A virtual Tick read(PacketPtr pkt); 3352623SN/A virtual Tick write(PacketPtr pkt); 3362623SN/A 3372623SN/A /** 3383169Sstever@eecs.umich.edu * Post an PIC interrupt to the CPU via the CChip 3393169Sstever@eecs.umich.edu * @param bitvector interrupt to post. 3403169Sstever@eecs.umich.edu */ 3413169Sstever@eecs.umich.edu void postPIC(uint8_t bitvector); 3423169Sstever@eecs.umich.edu 3432623SN/A /** 3442623SN/A * Clear a posted interrupt 3452623SN/A * @param bitvector interrupt to clear 3462623SN/A */ 3472623SN/A void clearPIC(uint8_t bitvector); 3482623SN/A 3493169Sstever@eecs.umich.edu /** 3502623SN/A * Serialize this object to the given output stream. 3512623SN/A * @param os The stream to serialize to. 3522623SN/A */ 3533170Sstever@eecs.umich.edu virtual void serialize(std::ostream &os); 3542623SN/A 3553170Sstever@eecs.umich.edu /** 3563170Sstever@eecs.umich.edu * Reconstruct the state of this object from a checkpoint. 3573170Sstever@eecs.umich.edu * @param cp The checkpoint use. 3582623SN/A * @param section The section name of this object 3593170Sstever@eecs.umich.edu */ 3603170Sstever@eecs.umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 3613170Sstever@eecs.umich.edu 3623170Sstever@eecs.umich.edu}; 3632631SN/A 3643170Sstever@eecs.umich.edu#endif // __DEV_TSUNAMI_IO_HH__ 3653170Sstever@eecs.umich.edu