tsunami_io.hh revision 10631:6d6bfdb036ce
112967Smatteo.andreozzi@arm.com/* 212967Smatteo.andreozzi@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 312967Smatteo.andreozzi@arm.com * All rights reserved. 412967Smatteo.andreozzi@arm.com * 512967Smatteo.andreozzi@arm.com * Redistribution and use in source and binary forms, with or without 612967Smatteo.andreozzi@arm.com * modification, are permitted provided that the following conditions are 712967Smatteo.andreozzi@arm.com * met: redistributions of source code must retain the above copyright 812967Smatteo.andreozzi@arm.com * notice, this list of conditions and the following disclaimer; 912967Smatteo.andreozzi@arm.com * redistributions in binary form must reproduce the above copyright 1012967Smatteo.andreozzi@arm.com * notice, this list of conditions and the following disclaimer in the 1112967Smatteo.andreozzi@arm.com * documentation and/or other materials provided with the distribution; 1212967Smatteo.andreozzi@arm.com * neither the name of the copyright holders nor the names of its 1312967Smatteo.andreozzi@arm.com * contributors may be used to endorse or promote products derived from 1412967Smatteo.andreozzi@arm.com * this software without specific prior written permission. 1512967Smatteo.andreozzi@arm.com * 1612967Smatteo.andreozzi@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712967Smatteo.andreozzi@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812967Smatteo.andreozzi@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912967Smatteo.andreozzi@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012967Smatteo.andreozzi@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112967Smatteo.andreozzi@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212967Smatteo.andreozzi@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312967Smatteo.andreozzi@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412967Smatteo.andreozzi@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512967Smatteo.andreozzi@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612967Smatteo.andreozzi@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712967Smatteo.andreozzi@arm.com * 2812967Smatteo.andreozzi@arm.com * Authors: Ali Saidi 2912967Smatteo.andreozzi@arm.com * Andrew Schultz 3012967Smatteo.andreozzi@arm.com * Miguel Serrano 3112967Smatteo.andreozzi@arm.com */ 3212967Smatteo.andreozzi@arm.com 3312967Smatteo.andreozzi@arm.com/** @file 3412967Smatteo.andreozzi@arm.com * Tsunami I/O Space mapping including RTC/timer interrupts 3512967Smatteo.andreozzi@arm.com */ 3612967Smatteo.andreozzi@arm.com 3712967Smatteo.andreozzi@arm.com#ifndef __DEV_TSUNAMI_IO_HH__ 3812967Smatteo.andreozzi@arm.com#define __DEV_TSUNAMI_IO_HH__ 3912967Smatteo.andreozzi@arm.com 4012967Smatteo.andreozzi@arm.com#include "dev/alpha/tsunami.hh" 4112967Smatteo.andreozzi@arm.com#include "dev/alpha/tsunami_cchip.hh" 4212967Smatteo.andreozzi@arm.com#include "dev/intel_8254_timer.hh" 4312967Smatteo.andreozzi@arm.com#include "dev/io_device.hh" 4412967Smatteo.andreozzi@arm.com#include "dev/mc146818.hh" 4512967Smatteo.andreozzi@arm.com#include "params/TsunamiIO.hh" 4612967Smatteo.andreozzi@arm.com#include "sim/eventq.hh" 4712967Smatteo.andreozzi@arm.com 4812967Smatteo.andreozzi@arm.com/** 4912967Smatteo.andreozzi@arm.com * Tsunami I/O device is a catch all for all the south bridge stuff we care 5012967Smatteo.andreozzi@arm.com * to implement. 5112967Smatteo.andreozzi@arm.com */ 5212967Smatteo.andreozzi@arm.comclass TsunamiIO : public BasicPioDevice 5312967Smatteo.andreozzi@arm.com{ 5412967Smatteo.andreozzi@arm.com 5512967Smatteo.andreozzi@arm.com protected: 5612967Smatteo.andreozzi@arm.com 5712967Smatteo.andreozzi@arm.com class RTC : public MC146818 5812967Smatteo.andreozzi@arm.com { 5912967Smatteo.andreozzi@arm.com public: 6012967Smatteo.andreozzi@arm.com Tsunami *tsunami; 6112967Smatteo.andreozzi@arm.com RTC(const std::string &n, const TsunamiIOParams *p); 6212967Smatteo.andreozzi@arm.com 6312967Smatteo.andreozzi@arm.com protected: 6412967Smatteo.andreozzi@arm.com void handleEvent() 6512967Smatteo.andreozzi@arm.com { 6612967Smatteo.andreozzi@arm.com //Actually interrupt the processor here 6712967Smatteo.andreozzi@arm.com tsunami->cchip->postRTC(); 6812967Smatteo.andreozzi@arm.com } 6912967Smatteo.andreozzi@arm.com }; 7012967Smatteo.andreozzi@arm.com 7112967Smatteo.andreozzi@arm.com /** Mask of the PIC1 */ 7212967Smatteo.andreozzi@arm.com uint8_t mask1; 7312967Smatteo.andreozzi@arm.com 7412967Smatteo.andreozzi@arm.com /** Mask of the PIC2 */ 7512967Smatteo.andreozzi@arm.com uint8_t mask2; 7612967Smatteo.andreozzi@arm.com 7712967Smatteo.andreozzi@arm.com /** Mode of PIC1. Not used for anything */ 7812967Smatteo.andreozzi@arm.com uint8_t mode1; 7912967Smatteo.andreozzi@arm.com 8012967Smatteo.andreozzi@arm.com /** Mode of PIC2. Not used for anything */ 8112967Smatteo.andreozzi@arm.com uint8_t mode2; 8212967Smatteo.andreozzi@arm.com 8312967Smatteo.andreozzi@arm.com /** Raw PIC interrupt register before masking */ 8412967Smatteo.andreozzi@arm.com uint8_t picr; //Raw PIC interrput register 8512967Smatteo.andreozzi@arm.com 8612967Smatteo.andreozzi@arm.com /** Is the pic interrupting right now or not. */ 8712967Smatteo.andreozzi@arm.com bool picInterrupting; 8812967Smatteo.andreozzi@arm.com 8912967Smatteo.andreozzi@arm.com /** A pointer to the Tsunami device which be belong to */ 9012967Smatteo.andreozzi@arm.com Tsunami *tsunami; 9112967Smatteo.andreozzi@arm.com 9212967Smatteo.andreozzi@arm.com /** Intel 8253 Periodic Interval Timer */ 9312967Smatteo.andreozzi@arm.com Intel8254Timer pitimer; 9412967Smatteo.andreozzi@arm.com 9512967Smatteo.andreozzi@arm.com RTC rtc; 9612967Smatteo.andreozzi@arm.com 9712967Smatteo.andreozzi@arm.com uint8_t rtcAddr; 9812967Smatteo.andreozzi@arm.com 9912967Smatteo.andreozzi@arm.com /** The interval is set via two writes to the PIT. 10012967Smatteo.andreozzi@arm.com * This variable contains a flag as to how many writes have happened, and 10112967Smatteo.andreozzi@arm.com * the time so far. 10212967Smatteo.andreozzi@arm.com */ 10312967Smatteo.andreozzi@arm.com uint16_t timerData; 10412967Smatteo.andreozzi@arm.com 10512967Smatteo.andreozzi@arm.com public: 10612967Smatteo.andreozzi@arm.com /** 10712967Smatteo.andreozzi@arm.com * Return the freqency of the RTC 10812967Smatteo.andreozzi@arm.com * @return interrupt rate of the RTC 10912967Smatteo.andreozzi@arm.com */ 11012967Smatteo.andreozzi@arm.com Tick frequency() const; 11112967Smatteo.andreozzi@arm.com 11212967Smatteo.andreozzi@arm.com public: 11312967Smatteo.andreozzi@arm.com typedef TsunamiIOParams Params; 11412967Smatteo.andreozzi@arm.com /** 11512967Smatteo.andreozzi@arm.com * Initialize all the data for devices supported by Tsunami I/O. 11612967Smatteo.andreozzi@arm.com * @param p pointer to Params struct 11712967Smatteo.andreozzi@arm.com */ 11812967Smatteo.andreozzi@arm.com TsunamiIO(const Params *p); 11912967Smatteo.andreozzi@arm.com 12012967Smatteo.andreozzi@arm.com const Params * 12112967Smatteo.andreozzi@arm.com params() const 12212967Smatteo.andreozzi@arm.com { 12312967Smatteo.andreozzi@arm.com return dynamic_cast<const Params *>(_params); 12412967Smatteo.andreozzi@arm.com } 12512967Smatteo.andreozzi@arm.com 12612967Smatteo.andreozzi@arm.com virtual Tick read(PacketPtr pkt); 12712967Smatteo.andreozzi@arm.com virtual Tick write(PacketPtr pkt); 12812967Smatteo.andreozzi@arm.com 12912967Smatteo.andreozzi@arm.com /** 13012967Smatteo.andreozzi@arm.com * Post an PIC interrupt to the CPU via the CChip 13112967Smatteo.andreozzi@arm.com * @param bitvector interrupt to post. 13212967Smatteo.andreozzi@arm.com */ 13312967Smatteo.andreozzi@arm.com void postPIC(uint8_t bitvector); 13412967Smatteo.andreozzi@arm.com 13512967Smatteo.andreozzi@arm.com /** 13612967Smatteo.andreozzi@arm.com * Clear a posted interrupt 13712967Smatteo.andreozzi@arm.com * @param bitvector interrupt to clear 13812967Smatteo.andreozzi@arm.com */ 13912967Smatteo.andreozzi@arm.com void clearPIC(uint8_t bitvector); 14012967Smatteo.andreozzi@arm.com 14112967Smatteo.andreozzi@arm.com /** 14212967Smatteo.andreozzi@arm.com * Serialize this object to the given output stream. 14312967Smatteo.andreozzi@arm.com * @param os The stream to serialize to. 14412967Smatteo.andreozzi@arm.com */ 14512967Smatteo.andreozzi@arm.com virtual void serialize(std::ostream &os); 14612967Smatteo.andreozzi@arm.com 14712967Smatteo.andreozzi@arm.com /** 14812967Smatteo.andreozzi@arm.com * Reconstruct the state of this object from a checkpoint. 14912967Smatteo.andreozzi@arm.com * @param cp The checkpoint use. 15012967Smatteo.andreozzi@arm.com * @param section The section name of this object 15112967Smatteo.andreozzi@arm.com */ 15212967Smatteo.andreozzi@arm.com virtual void unserialize(Checkpoint *cp, const std::string §ion); 15312967Smatteo.andreozzi@arm.com 15412967Smatteo.andreozzi@arm.com /** 15512967Smatteo.andreozzi@arm.com * Start running. 15612967Smatteo.andreozzi@arm.com */ 15712967Smatteo.andreozzi@arm.com virtual void startup(); 15812967Smatteo.andreozzi@arm.com 15912967Smatteo.andreozzi@arm.com}; 16012967Smatteo.andreozzi@arm.com 16112967Smatteo.andreozzi@arm.com#endif // __DEV_TSUNAMI_IO_HH__ 16212967Smatteo.andreozzi@arm.com