tsunami_io.hh revision 2665
12914Ssaidi@eecs.umich.edu/* 28856Sandreas.hansson@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 68856Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 78856Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 88856Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 98856Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 108856Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 118856Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 128856Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 138856Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 142914Ssaidi@eecs.umich.edu * this software without specific prior written permission. 152914Ssaidi@eecs.umich.edu * 162914Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172914Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182914Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192914Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202914Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212914Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222914Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232914Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242914Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252914Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262914Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272914Ssaidi@eecs.umich.edu * 282914Ssaidi@eecs.umich.edu * Authors: Ali Saidi 292914Ssaidi@eecs.umich.edu * Andrew Schultz 302914Ssaidi@eecs.umich.edu * Miguel Serrano 312914Ssaidi@eecs.umich.edu */ 322914Ssaidi@eecs.umich.edu 332914Ssaidi@eecs.umich.edu/** @file 342914Ssaidi@eecs.umich.edu * Tsunami I/O Space mapping including RTC/timer interrupts 352914Ssaidi@eecs.umich.edu */ 362914Ssaidi@eecs.umich.edu 372914Ssaidi@eecs.umich.edu#ifndef __DEV_TSUNAMI_IO_HH__ 382914Ssaidi@eecs.umich.edu#define __DEV_TSUNAMI_IO_HH__ 392914Ssaidi@eecs.umich.edu 402914Ssaidi@eecs.umich.edu#include "dev/io_device.hh" 418856Sandreas.hansson@arm.com#include "base/range.hh" 422914Ssaidi@eecs.umich.edu#include "dev/tsunami.hh" 432914Ssaidi@eecs.umich.edu#include "sim/eventq.hh" 448708Sandreas.hansson@arm.com 452914Ssaidi@eecs.umich.edu/** 462914Ssaidi@eecs.umich.edu * Tsunami I/O device is a catch all for all the south bridge stuff we care 478914Sandreas.hansson@arm.com * to implement. 488914Sandreas.hansson@arm.com */ 498922Swilliam.wang@arm.comclass TsunamiIO : public BasicPioDevice 505740Snate@binkert.org{ 515740Snate@binkert.org private: 525740Snate@binkert.org struct tm tm; 534490Sstever@eecs.umich.edu 544490Sstever@eecs.umich.edu protected: 554490Sstever@eecs.umich.edu /** Real-Time Clock (MC146818) */ 568914Sandreas.hansson@arm.com class RTC 578914Sandreas.hansson@arm.com { 583296Ssaidi@eecs.umich.edu private: 594929Sstever@gmail.com /** Event for RTC periodic interrupt */ 603091Sstever@eecs.umich.edu struct RTCEvent : public Event 613091Sstever@eecs.umich.edu { 623091Sstever@eecs.umich.edu /** A pointer back to tsunami to create interrupt the processor. */ 638975Sandreas.hansson@arm.com Tsunami* tsunami; 643091Sstever@eecs.umich.edu Tick interval; 654670Sstever@eecs.umich.edu 664670Sstever@eecs.umich.edu RTCEvent(Tsunami* t, Tick i); 674670Sstever@eecs.umich.edu 684670Sstever@eecs.umich.edu /** Schedule the RTC periodic interrupt */ 694670Sstever@eecs.umich.edu void scheduleIntr(); 704670Sstever@eecs.umich.edu 714670Sstever@eecs.umich.edu /** Event process to occur at interrupt*/ 724626Sstever@eecs.umich.edu virtual void process(); 733091Sstever@eecs.umich.edu 743175Srdreslin@umich.edu /** Event description */ 754626Sstever@eecs.umich.edu virtual const char *description(); 764670Sstever@eecs.umich.edu }; 774670Sstever@eecs.umich.edu 784626Sstever@eecs.umich.edu private: 798914Sandreas.hansson@arm.com std::string _name; 804626Sstever@eecs.umich.edu const std::string &name() const { return _name; } 814490Sstever@eecs.umich.edu 823309Srdreslin@umich.edu /** RTC periodic interrupt event */ 834670Sstever@eecs.umich.edu RTCEvent event; 843091Sstever@eecs.umich.edu 853091Sstever@eecs.umich.edu /** Current RTC register address/index */ 86 int addr; 87 88 /** Data for real-time clock function */ 89 union { 90 uint8_t clock_data[10]; 91 92 struct { 93 uint8_t sec; 94 uint8_t sec_alrm; 95 uint8_t min; 96 uint8_t min_alrm; 97 uint8_t hour; 98 uint8_t hour_alrm; 99 uint8_t wday; 100 uint8_t mday; 101 uint8_t mon; 102 uint8_t year; 103 }; 104 }; 105 106 /** RTC status register A */ 107 uint8_t stat_regA; 108 109 /** RTC status register B */ 110 uint8_t stat_regB; 111 112 public: 113 RTC(const std::string &name, Tsunami* t, Tick i); 114 115 /** Set the initial RTC time/date */ 116 void set_time(time_t t); 117 118 /** RTC address port: write address of RTC RAM data to access */ 119 void writeAddr(const uint8_t data); 120 121 /** RTC write data */ 122 void writeData(const uint8_t data); 123 124 /** RTC read data */ 125 uint8_t readData(); 126 127 /** 128 * Serialize this object to the given output stream. 129 * @param os The stream to serialize to. 130 */ 131 void serialize(const std::string &base, std::ostream &os); 132 133 /** 134 * Reconstruct the state of this object from a checkpoint. 135 * @param cp The checkpoint use. 136 * @param section The section name of this object 137 */ 138 void unserialize(const std::string &base, Checkpoint *cp, 139 const std::string §ion); 140 }; 141 142 /** Programmable Interval Timer (Intel 8254) */ 143 class PITimer 144 { 145 /** Counter element for PIT */ 146 class Counter 147 { 148 /** Event for counter interrupt */ 149 class CounterEvent : public Event 150 { 151 private: 152 /** Pointer back to Counter */ 153 Counter* counter; 154 Tick interval; 155 156 public: 157 CounterEvent(Counter*); 158 159 /** Event process */ 160 virtual void process(); 161 162 /** Event description */ 163 virtual const char *description(); 164 165 friend class Counter; 166 }; 167 168 private: 169 std::string _name; 170 const std::string &name() const { return _name; } 171 172 CounterEvent event; 173 174 /** Current count value */ 175 uint16_t count; 176 177 /** Latched count */ 178 uint16_t latched_count; 179 180 /** Interrupt period */ 181 uint16_t period; 182 183 /** Current mode of operation */ 184 uint8_t mode; 185 186 /** Output goes high when the counter reaches zero */ 187 bool output_high; 188 189 /** State of the count latch */ 190 bool latch_on; 191 192 /** Set of values for read_byte and write_byte */ 193 enum {LSB, MSB}; 194 195 /** Determine which byte of a 16-bit count value to read/write */ 196 uint8_t read_byte, write_byte; 197 198 public: 199 Counter(const std::string &name); 200 201 /** Latch the current count (if one is not already latched) */ 202 void latchCount(); 203 204 /** Set the read/write mode */ 205 void setRW(int rw_val); 206 207 /** Set operational mode */ 208 void setMode(int mode_val); 209 210 /** Set count encoding */ 211 void setBCD(int bcd_val); 212 213 /** Read a count byte */ 214 uint8_t read(); 215 216 /** Write a count byte */ 217 void write(const uint8_t data); 218 219 /** Is the output high? */ 220 bool outputHigh(); 221 222 /** 223 * Serialize this object to the given output stream. 224 * @param os The stream to serialize to. 225 */ 226 void serialize(const std::string &base, std::ostream &os); 227 228 /** 229 * Reconstruct the state of this object from a checkpoint. 230 * @param cp The checkpoint use. 231 * @param section The section name of this object 232 */ 233 void unserialize(const std::string &base, Checkpoint *cp, 234 const std::string §ion); 235 }; 236 237 private: 238 std::string _name; 239 const std::string &name() const { return _name; } 240 241 /** PIT has three seperate counters */ 242 Counter *counter[3]; 243 244 public: 245 /** Public way to access individual counters (avoid array accesses) */ 246 Counter counter0; 247 Counter counter1; 248 Counter counter2; 249 250 PITimer(const std::string &name); 251 252 /** Write control word */ 253 void writeControl(const uint8_t data); 254 255 /** 256 * Serialize this object to the given output stream. 257 * @param os The stream to serialize to. 258 */ 259 void serialize(const std::string &base, std::ostream &os); 260 261 /** 262 * Reconstruct the state of this object from a checkpoint. 263 * @param cp The checkpoint use. 264 * @param section The section name of this object 265 */ 266 void unserialize(const std::string &base, Checkpoint *cp, 267 const std::string §ion); 268 }; 269 270 /** Mask of the PIC1 */ 271 uint8_t mask1; 272 273 /** Mask of the PIC2 */ 274 uint8_t mask2; 275 276 /** Mode of PIC1. Not used for anything */ 277 uint8_t mode1; 278 279 /** Mode of PIC2. Not used for anything */ 280 uint8_t mode2; 281 282 /** Raw PIC interrupt register before masking */ 283 uint8_t picr; //Raw PIC interrput register 284 285 /** Is the pic interrupting right now or not. */ 286 bool picInterrupting; 287 288 /** A pointer to the Tsunami device which be belong to */ 289 Tsunami *tsunami; 290 291 /** Intel 8253 Periodic Interval Timer */ 292 PITimer pitimer; 293 294 RTC rtc; 295 296 /** The interval is set via two writes to the PIT. 297 * This variable contains a flag as to how many writes have happened, and 298 * the time so far. 299 */ 300 uint16_t timerData; 301 302 public: 303 /** 304 * Return the freqency of the RTC 305 * @return interrupt rate of the RTC 306 */ 307 Tick frequency() const; 308 309 struct Params : public BasicPioDevice::Params 310 { 311 Tick frequency; 312 Tsunami *tsunami; 313 time_t init_time; 314 }; 315 protected: 316 const Params *params() const { return (const Params*)_params; } 317 318 public: 319 /** 320 * Initialize all the data for devices supported by Tsunami I/O. 321 * @param p pointer to Params struct 322 */ 323 TsunamiIO(Params *p); 324 325 virtual Tick read(Packet *pkt); 326 virtual Tick write(Packet *pkt); 327 328 /** 329 * Post an PIC interrupt to the CPU via the CChip 330 * @param bitvector interrupt to post. 331 */ 332 void postPIC(uint8_t bitvector); 333 334 /** 335 * Clear a posted interrupt 336 * @param bitvector interrupt to clear 337 */ 338 void clearPIC(uint8_t bitvector); 339 340 /** 341 * Serialize this object to the given output stream. 342 * @param os The stream to serialize to. 343 */ 344 virtual void serialize(std::ostream &os); 345 346 /** 347 * Reconstruct the state of this object from a checkpoint. 348 * @param cp The checkpoint use. 349 * @param section The section name of this object 350 */ 351 virtual void unserialize(Checkpoint *cp, const std::string §ion); 352 353}; 354 355#endif // __DEV_TSUNAMI_IO_HH__ 356