tsunami_io.hh revision 1401
110448Snilay@cs.wisc.edu/*
210448Snilay@cs.wisc.edu * Copyright (c) 2004 The Regents of The University of Michigan
310448Snilay@cs.wisc.edu * All rights reserved.
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710448Snilay@cs.wisc.edu * met: redistributions of source code must retain the above copyright
810448Snilay@cs.wisc.edu * notice, this list of conditions and the following disclaimer;
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1410448Snilay@cs.wisc.edu * this software without specific prior written permission.
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2810447Snilay@cs.wisc.edu
2910447Snilay@cs.wisc.edu/* @file
3010447Snilay@cs.wisc.edu * Tsunami Fake I/O Space mapping including RTC/timer interrupts
3110447Snilay@cs.wisc.edu */
3210447Snilay@cs.wisc.edu
3310447Snilay@cs.wisc.edu#ifndef __DEV_TSUNAMI_IO_HH__
3410447Snilay@cs.wisc.edu#define __DEV_TSUNAMI_IO_HH__
3510447Snilay@cs.wisc.edu
3610447Snilay@cs.wisc.edu#include "dev/io_device.hh"
3710447Snilay@cs.wisc.edu#include "base/range.hh"
3810447Snilay@cs.wisc.edu#include "dev/tsunami.hh"
3910447Snilay@cs.wisc.edu#include "sim/eventq.hh"
4010447Snilay@cs.wisc.edu
4110447Snilay@cs.wisc.edu/** How often the RTC interrupts */
4210447Snilay@cs.wisc.edustatic const int RTC_RATE  = 1024;
4310447Snilay@cs.wisc.edu
4410447Snilay@cs.wisc.edu/*
4510447Snilay@cs.wisc.edu * Tsunami I/O device is a catch all for all the south bridge stuff we care
4610447Snilay@cs.wisc.edu * to implement.
4710447Snilay@cs.wisc.edu */
4810447Snilay@cs.wisc.educlass TsunamiIO : public PioDevice
4910447Snilay@cs.wisc.edu{
5010447Snilay@cs.wisc.edu  private:
5110447Snilay@cs.wisc.edu    /** The base address of this device */
5210447Snilay@cs.wisc.edu    Addr addr;
5310447Snilay@cs.wisc.edu
5410447Snilay@cs.wisc.edu    /** The size of mappad from the above address */
5510447Snilay@cs.wisc.edu    static const Addr size = 0xff;
5610447Snilay@cs.wisc.edu
5710447Snilay@cs.wisc.edu    struct tm tm;
5810447Snilay@cs.wisc.edu
5910447Snilay@cs.wisc.edu    /**
6010447Snilay@cs.wisc.edu     * In Tsunami RTC only has two i/o ports one for data and one for
6110447Snilay@cs.wisc.edu     * address, so you write the address and then read/write the
6210447Snilay@cs.wisc.edu     * data. This store the address you are going to be reading from
6310447Snilay@cs.wisc.edu     * on a read.
6410447Snilay@cs.wisc.edu     */
6510447Snilay@cs.wisc.edu    uint8_t RTCAddress;
6610447Snilay@cs.wisc.edu
6710447Snilay@cs.wisc.edu  protected:
6810447Snilay@cs.wisc.edu
6910447Snilay@cs.wisc.edu    /**
7010447Snilay@cs.wisc.edu     * The ClockEvent is handles the PIT interrupts
7110447Snilay@cs.wisc.edu     */
7210447Snilay@cs.wisc.edu    class ClockEvent : public Event
7310447Snilay@cs.wisc.edu    {
7410447Snilay@cs.wisc.edu      protected:
7510447Snilay@cs.wisc.edu        /** how often the PIT fires */
7610447Snilay@cs.wisc.edu        Tick interval;
7710447Snilay@cs.wisc.edu        /** The mode of the PIT */
7810447Snilay@cs.wisc.edu        uint8_t mode;
7910447Snilay@cs.wisc.edu        /** The status of the PIT */
8010447Snilay@cs.wisc.edu        uint8_t status;
8110447Snilay@cs.wisc.edu
8210447Snilay@cs.wisc.edu      public:
8310447Snilay@cs.wisc.edu        /**
8410447Snilay@cs.wisc.edu         * Just set the mode to 0
8510447Snilay@cs.wisc.edu         */
8610447Snilay@cs.wisc.edu        ClockEvent();
8710447Snilay@cs.wisc.edu
8810447Snilay@cs.wisc.edu        /**
8910447Snilay@cs.wisc.edu         * processs the timer event
9010447Snilay@cs.wisc.edu         */
9110447Snilay@cs.wisc.edu        virtual void process();
9210447Snilay@cs.wisc.edu
9310447Snilay@cs.wisc.edu        /**
9410447Snilay@cs.wisc.edu         * Returns a description of this event
9510447Snilay@cs.wisc.edu         * @return the description
9610447Snilay@cs.wisc.edu         */
9710447Snilay@cs.wisc.edu        virtual const char *description();
9810447Snilay@cs.wisc.edu
9910447Snilay@cs.wisc.edu        /**
10010447Snilay@cs.wisc.edu         * Schedule a timer interrupt to occur sometime in the future.
10110447Snilay@cs.wisc.edu         */
10210447Snilay@cs.wisc.edu        void Program(int count);
10310447Snilay@cs.wisc.edu
10410447Snilay@cs.wisc.edu        /**
10510447Snilay@cs.wisc.edu         * Write the mode bits of the PIT.
10610447Snilay@cs.wisc.edu         * @param mode the new mode
10710447Snilay@cs.wisc.edu         */
10810447Snilay@cs.wisc.edu        void ChangeMode(uint8_t mode);
10910447Snilay@cs.wisc.edu
11010447Snilay@cs.wisc.edu        /**
11110447Snilay@cs.wisc.edu         * The current PIT status.
11210447Snilay@cs.wisc.edu         * @return the status of the PIT
11310447Snilay@cs.wisc.edu         */
11410447Snilay@cs.wisc.edu        uint8_t Status();
11510447Snilay@cs.wisc.edu
11610447Snilay@cs.wisc.edu        /**
11710447Snilay@cs.wisc.edu         * Serialize this object to the given output stream.
11810447Snilay@cs.wisc.edu         * @param os The stream to serialize to.
11910447Snilay@cs.wisc.edu         */
12010447Snilay@cs.wisc.edu        virtual void serialize(std::ostream &os);
12110447Snilay@cs.wisc.edu
12210447Snilay@cs.wisc.edu
12310447Snilay@cs.wisc.edu        /**
12410447Snilay@cs.wisc.edu         * Reconstruct the state of this object from a checkpoint.
12510447Snilay@cs.wisc.edu         * @param cp The checkpoint use.
12610447Snilay@cs.wisc.edu         * @param section The section name of this object
12710447Snilay@cs.wisc.edu         */
12810447Snilay@cs.wisc.edu        virtual void unserialize(Checkpoint *cp, const std::string &section);
12910447Snilay@cs.wisc.edu     };
13010447Snilay@cs.wisc.edu
13110447Snilay@cs.wisc.edu    /**
13210447Snilay@cs.wisc.edu     * Process RTC timer events and generate interrupts appropriately.
13310447Snilay@cs.wisc.edu     */
13410447Snilay@cs.wisc.edu    class RTCEvent : public Event
13510447Snilay@cs.wisc.edu    {
13610447Snilay@cs.wisc.edu      protected:
13710447Snilay@cs.wisc.edu        /** A pointer back to tsunami to create interrupt the processor. */
13810447Snilay@cs.wisc.edu        Tsunami* tsunami;
13910447Snilay@cs.wisc.edu      public:
14010447Snilay@cs.wisc.edu        /** RTC Event initializes the RTC event by scheduling an event
14110447Snilay@cs.wisc.edu         * RTC_RATE times pre second. */
14210447Snilay@cs.wisc.edu        RTCEvent(Tsunami* t);
14310447Snilay@cs.wisc.edu
14410447Snilay@cs.wisc.edu        /**
14510447Snilay@cs.wisc.edu         * Interrupth the processor and reschedule the event.
14610447Snilay@cs.wisc.edu         */
14710447Snilay@cs.wisc.edu        virtual void process();
14810447Snilay@cs.wisc.edu
14910447Snilay@cs.wisc.edu        /**
15010447Snilay@cs.wisc.edu         * Return a description of this event.
15110447Snilay@cs.wisc.edu         * @return a description
15210447Snilay@cs.wisc.edu         */
15310447Snilay@cs.wisc.edu        virtual const char *description();
15410447Snilay@cs.wisc.edu
15510447Snilay@cs.wisc.edu        /**
15610447Snilay@cs.wisc.edu         * Serialize this object to the given output stream.
15710447Snilay@cs.wisc.edu         * @param os The stream to serialize to.
15810447Snilay@cs.wisc.edu         */
15910447Snilay@cs.wisc.edu        virtual void serialize(std::ostream &os);
16010447Snilay@cs.wisc.edu
16110447Snilay@cs.wisc.edu        /**
16210447Snilay@cs.wisc.edu         * Reconstruct the state of this object from a checkpoint.
16310447Snilay@cs.wisc.edu         * @param cp The checkpoint use.
16410447Snilay@cs.wisc.edu         * @param section The section name of this object
16510447Snilay@cs.wisc.edu         */
16610447Snilay@cs.wisc.edu        virtual void unserialize(Checkpoint *cp, const std::string &section);
16710447Snilay@cs.wisc.edu    };
16810447Snilay@cs.wisc.edu
16910447Snilay@cs.wisc.edu    /** uip UpdateInProgess says that the rtc is updating, but we just fake it
17010447Snilay@cs.wisc.edu     * by alternating it on every read of the bit since we are going to
17110447Snilay@cs.wisc.edu     * override the loop_per_jiffy time that it is trying to use the UIP to
17210447Snilay@cs.wisc.edu     * calculate.
17310447Snilay@cs.wisc.edu     */
17410447Snilay@cs.wisc.edu    uint8_t uip;
17510447Snilay@cs.wisc.edu
17610447Snilay@cs.wisc.edu    /** Mask of the PIC1 */
17710447Snilay@cs.wisc.edu    uint8_t mask1;
17810447Snilay@cs.wisc.edu
17910447Snilay@cs.wisc.edu    /** Mask of the PIC2 */
18010447Snilay@cs.wisc.edu    uint8_t mask2;
18110447Snilay@cs.wisc.edu
18210447Snilay@cs.wisc.edu    /** Mode of PIC1. Not used for anything */
18310447Snilay@cs.wisc.edu    uint8_t mode1;
18410447Snilay@cs.wisc.edu
18510447Snilay@cs.wisc.edu    /** Mode of PIC2. Not used for anything */
18610447Snilay@cs.wisc.edu    uint8_t mode2;
18710447Snilay@cs.wisc.edu
18810447Snilay@cs.wisc.edu    /** Raw PIC interrupt register before masking */
18910447Snilay@cs.wisc.edu    uint8_t picr; //Raw PIC interrput register
19010447Snilay@cs.wisc.edu
19110447Snilay@cs.wisc.edu    /** Is the pic interrupting right now or not. */
19210447Snilay@cs.wisc.edu    bool picInterrupting;
19310447Snilay@cs.wisc.edu
19410447Snilay@cs.wisc.edu    /** A pointer to the Tsunami device which be belong to */
19510447Snilay@cs.wisc.edu    Tsunami *tsunami;
19610447Snilay@cs.wisc.edu
19710447Snilay@cs.wisc.edu    /**
19810447Snilay@cs.wisc.edu     * This timer is initilized, but after I wrote the code
19910447Snilay@cs.wisc.edu     * it doesn't seem to be used again, and best I can tell
20010447Snilay@cs.wisc.edu     * it too is not connected to any interrupt port
20110447Snilay@cs.wisc.edu     */
20210447Snilay@cs.wisc.edu    ClockEvent timer0;
20310447Snilay@cs.wisc.edu
20410447Snilay@cs.wisc.edu    /**
20510447Snilay@cs.wisc.edu     * This timer is used to control the speaker, which
20610447Snilay@cs.wisc.edu     * we normally could care less about, however it is
20710447Snilay@cs.wisc.edu     * also used to calculated the clockspeed and hense
20810447Snilay@cs.wisc.edu     * bogomips which is kinda important to the scheduler
20910447Snilay@cs.wisc.edu     * so we need to implemnt it although after boot I can't
21010447Snilay@cs.wisc.edu     * imagine we would be playing with the PC speaker much
21110447Snilay@cs.wisc.edu     */
21210447Snilay@cs.wisc.edu    ClockEvent timer2;
21310447Snilay@cs.wisc.edu
21410447Snilay@cs.wisc.edu    /** This is the event used to interrupt the cpu like an RTC.  */
21510447Snilay@cs.wisc.edu    RTCEvent rtc;
21610447Snilay@cs.wisc.edu
21710447Snilay@cs.wisc.edu    /** The interval is set via two writes to the PIT.
21810447Snilay@cs.wisc.edu     * This variable contains a flag as to how many writes have happened, and
21910447Snilay@cs.wisc.edu     * the time so far.
22010447Snilay@cs.wisc.edu     */
22110447Snilay@cs.wisc.edu    uint32_t timerData;
22210447Snilay@cs.wisc.edu
22310447Snilay@cs.wisc.edu  public:
22410447Snilay@cs.wisc.edu    /**
22510447Snilay@cs.wisc.edu     * Return the freqency of the RTC
22610447Snilay@cs.wisc.edu     * @return interrupt rate of the RTC
22710447Snilay@cs.wisc.edu     */
22810447Snilay@cs.wisc.edu    Tick  frequency() const { return RTC_RATE; }
22910447Snilay@cs.wisc.edu
23010447Snilay@cs.wisc.edu    /**
23110447Snilay@cs.wisc.edu     * Initialize all the data for devices supported by Tsunami I/O.
23210447Snilay@cs.wisc.edu     * @param name name of this device.
23310447Snilay@cs.wisc.edu     * @param t pointer back to the Tsunami object that we belong to.
23410447Snilay@cs.wisc.edu     * @param init_time Time (as in seconds since 1970) to set RTC to.
23510447Snilay@cs.wisc.edu     * @param a address we are mapped at.
23610447Snilay@cs.wisc.edu     * @param mmu pointer to the memory controller that sends us events.
23710447Snilay@cs.wisc.edu     */
23810447Snilay@cs.wisc.edu    TsunamiIO(const std::string &name, Tsunami *t, time_t init_time,
23910447Snilay@cs.wisc.edu              Addr a, MemoryController *mmu, HierParams *hier, Bus *bus,
24010447Snilay@cs.wisc.edu              Tick pio_latency);
24110447Snilay@cs.wisc.edu
24210447Snilay@cs.wisc.edu    /**
24310447Snilay@cs.wisc.edu     * Create the tm struct from seconds since 1970
24410447Snilay@cs.wisc.edu     */
24510447Snilay@cs.wisc.edu    void set_time(time_t t);
24610447Snilay@cs.wisc.edu
24710447Snilay@cs.wisc.edu    /**
24810447Snilay@cs.wisc.edu      * Process a read to one of the devices we are emulating.
24910447Snilay@cs.wisc.edu      * @param req Contains the address to read from.
25010447Snilay@cs.wisc.edu      * @param data A pointer to write the read data to.
25110447Snilay@cs.wisc.edu      * @return The fault condition of the access.
25210447Snilay@cs.wisc.edu      */
25310447Snilay@cs.wisc.edu    virtual Fault read(MemReqPtr &req, uint8_t *data);
25410447Snilay@cs.wisc.edu
25510447Snilay@cs.wisc.edu    /**
25610447Snilay@cs.wisc.edu      * Process a write to one of the devices we emulate.
25710447Snilay@cs.wisc.edu      * @param req Contains the address to write to.
25810447Snilay@cs.wisc.edu      * @param data The data to write.
25910447Snilay@cs.wisc.edu      * @return The fault condition of the access.
26010447Snilay@cs.wisc.edu      */
26110447Snilay@cs.wisc.edu    virtual Fault write(MemReqPtr &req, const uint8_t *data);
26210447Snilay@cs.wisc.edu
26310447Snilay@cs.wisc.edu    /**
26410447Snilay@cs.wisc.edu     * Post an PIC interrupt to the CPU via the CChip
26510447Snilay@cs.wisc.edu     * @param bitvector interrupt to post.
26610447Snilay@cs.wisc.edu     */
26710447Snilay@cs.wisc.edu    void postPIC(uint8_t bitvector);
26810447Snilay@cs.wisc.edu
26910447Snilay@cs.wisc.edu    /**
27010447Snilay@cs.wisc.edu     * Clear a posted interrupt
27110447Snilay@cs.wisc.edu     * @param bitvector interrupt to clear
27210447Snilay@cs.wisc.edu     */
27310447Snilay@cs.wisc.edu    void clearPIC(uint8_t bitvector);
27410447Snilay@cs.wisc.edu
27510447Snilay@cs.wisc.edu    /**
27610447Snilay@cs.wisc.edu     * Serialize this object to the given output stream.
27710447Snilay@cs.wisc.edu     * @param os The stream to serialize to.
27810447Snilay@cs.wisc.edu     */
27910447Snilay@cs.wisc.edu    virtual void serialize(std::ostream &os);
28010447Snilay@cs.wisc.edu
28110447Snilay@cs.wisc.edu    /**
28210447Snilay@cs.wisc.edu     * Reconstruct the state of this object from a checkpoint.
28310447Snilay@cs.wisc.edu     * @param cp The checkpoint use.
28410447Snilay@cs.wisc.edu     * @param section The section name of this object
28510447Snilay@cs.wisc.edu     */
28610447Snilay@cs.wisc.edu    virtual void unserialize(Checkpoint *cp, const std::string &section);
28710447Snilay@cs.wisc.edu
28810447Snilay@cs.wisc.edu    Tick cacheAccess(MemReqPtr &req);
28910447Snilay@cs.wisc.edu};
29010447Snilay@cs.wisc.edu
29110447Snilay@cs.wisc.edu#endif // __DEV_TSUNAMI_IO_HH__
29210447Snilay@cs.wisc.edu