tsunami_cchip.hh revision 1722
110260SAndrew.Bardsley@arm.com/* 210260SAndrew.Bardsley@arm.com * Copyright (c) 2004 The Regents of The University of Michigan 310260SAndrew.Bardsley@arm.com * All rights reserved. 410260SAndrew.Bardsley@arm.com * 510260SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 610260SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 710260SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 810260SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 910260SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 1010260SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 1110260SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 1210260SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 1310315Snilay@cs.wisc.edu * contributors may be used to endorse or promote products derived from 1410260SAndrew.Bardsley@arm.com * this software without specific prior written permission. 1510260SAndrew.Bardsley@arm.com * 1610260SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711570SCurtis.Dunham@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810260SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911388Ssteve.reinhardt@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010260SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110260SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210315Snilay@cs.wisc.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310260SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410260SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510260SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610260SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710260SAndrew.Bardsley@arm.com */ 2810753Sstever@gmail.com 2911388Ssteve.reinhardt@amd.com/** @file 3010260SAndrew.Bardsley@arm.com * Emulation of the Tsunami CChip CSRs 3111570SCurtis.Dunham@arm.com */ 3211570SCurtis.Dunham@arm.com 3311570SCurtis.Dunham@arm.com#ifndef __TSUNAMI_CCHIP_HH__ 3411570SCurtis.Dunham@arm.com#define __TSUNAMI_CCHIP_HH__ 3510260SAndrew.Bardsley@arm.com 3610260SAndrew.Bardsley@arm.com#include "dev/tsunami.hh" 3711570SCurtis.Dunham@arm.com#include "base/range.hh" 3811570SCurtis.Dunham@arm.com#include "dev/io_device.hh" 3910260SAndrew.Bardsley@arm.com 4010260SAndrew.Bardsley@arm.com/** 4110260SAndrew.Bardsley@arm.com * Tsunami CChip CSR Emulation. This device includes all the interrupt 4210260SAndrew.Bardsley@arm.com * handling code for the chipset. 4310260SAndrew.Bardsley@arm.com */ 4410260SAndrew.Bardsley@arm.comclass TsunamiCChip : public PioDevice 4510260SAndrew.Bardsley@arm.com{ 4610260SAndrew.Bardsley@arm.com private: 4710260SAndrew.Bardsley@arm.com /** The base address of this device */ 4810260SAndrew.Bardsley@arm.com Addr addr; 4910260SAndrew.Bardsley@arm.com 5010260SAndrew.Bardsley@arm.com /** The size of mappad from the above address */ 5110315Snilay@cs.wisc.edu static const Addr size = 0xfffffff; 5210260SAndrew.Bardsley@arm.com 5310315Snilay@cs.wisc.edu protected: 5410260SAndrew.Bardsley@arm.com /** 5510260SAndrew.Bardsley@arm.com * pointer to the tsunami object. 5610260SAndrew.Bardsley@arm.com * This is our access to all the other tsunami 5710260SAndrew.Bardsley@arm.com * devices. 5810260SAndrew.Bardsley@arm.com */ 5910260SAndrew.Bardsley@arm.com Tsunami *tsunami; 6010260SAndrew.Bardsley@arm.com 6110260SAndrew.Bardsley@arm.com /** 6210260SAndrew.Bardsley@arm.com * The dims are device interrupt mask registers. 6310260SAndrew.Bardsley@arm.com * One exists for each CPU, the DRIR X DIM = DIR 6410260SAndrew.Bardsley@arm.com */ 6510260SAndrew.Bardsley@arm.com uint64_t dim[Tsunami::Max_CPUs]; 6610260SAndrew.Bardsley@arm.com 6711570SCurtis.Dunham@arm.com /** 6810260SAndrew.Bardsley@arm.com * The dirs are device interrupt registers. 6910260SAndrew.Bardsley@arm.com * One exists for each CPU, the DRIR X DIM = DIR 7010260SAndrew.Bardsley@arm.com */ 7110260SAndrew.Bardsley@arm.com uint64_t dir[Tsunami::Max_CPUs]; 7210260SAndrew.Bardsley@arm.com 7310260SAndrew.Bardsley@arm.com /** 7410260SAndrew.Bardsley@arm.com * This register contains bits for each PCI interrupt 7510260SAndrew.Bardsley@arm.com * that can occur. 7610260SAndrew.Bardsley@arm.com */ 7710260SAndrew.Bardsley@arm.com uint64_t drir; 7810260SAndrew.Bardsley@arm.com 7910260SAndrew.Bardsley@arm.com /** Indicator of which CPUs have an IPI interrupt */ 8010260SAndrew.Bardsley@arm.com uint64_t ipint; 8110260SAndrew.Bardsley@arm.com 8210260SAndrew.Bardsley@arm.com /** Indicator of which CPUs have an RTC interrupt */ 8310260SAndrew.Bardsley@arm.com uint64_t itint; 8410260SAndrew.Bardsley@arm.com 8510260SAndrew.Bardsley@arm.com public: 8610260SAndrew.Bardsley@arm.com /** 8710260SAndrew.Bardsley@arm.com * Initialize the Tsunami CChip by setting all of the 8810260SAndrew.Bardsley@arm.com * device register to 0. 8910260SAndrew.Bardsley@arm.com * @param name name of this device. 9010260SAndrew.Bardsley@arm.com * @param t pointer back to the Tsunami object that we belong to. 9110260SAndrew.Bardsley@arm.com * @param a address we are mapped at. 9210260SAndrew.Bardsley@arm.com * @param mmu pointer to the memory controller that sends us events. 9310260SAndrew.Bardsley@arm.com * @param hier object to store parameters universal the device hierarchy 9410260SAndrew.Bardsley@arm.com * @param bus The bus that this device is attached to 9510260SAndrew.Bardsley@arm.com */ 9610260SAndrew.Bardsley@arm.com TsunamiCChip(const std::string &name, Tsunami *t, Addr a, 9710260SAndrew.Bardsley@arm.com MemoryController *mmu, HierParams *hier, Bus *bus, 9810260SAndrew.Bardsley@arm.com Tick pio_latency); 9910260SAndrew.Bardsley@arm.com 10010260SAndrew.Bardsley@arm.com /** 10110260SAndrew.Bardsley@arm.com * Process a read to the CChip. 10210260SAndrew.Bardsley@arm.com * @param req Contains the address to read from. 10310260SAndrew.Bardsley@arm.com * @param data A pointer to write the read data to. 10410260SAndrew.Bardsley@arm.com * @return The fault condition of the access. 10510260SAndrew.Bardsley@arm.com */ 10610260SAndrew.Bardsley@arm.com virtual Fault read(MemReqPtr &req, uint8_t *data); 10710260SAndrew.Bardsley@arm.com 10810260SAndrew.Bardsley@arm.com 10910260SAndrew.Bardsley@arm.com /** 11010260SAndrew.Bardsley@arm.com * Process a write to the CChip. 11110260SAndrew.Bardsley@arm.com * @param req Contains the address to write to. 11211570SCurtis.Dunham@arm.com * @param data The data to write. 11311570SCurtis.Dunham@arm.com * @return The fault condition of the access. 11411570SCurtis.Dunham@arm.com */ 11511570SCurtis.Dunham@arm.com virtual Fault write(MemReqPtr &req, const uint8_t *data); 11610260SAndrew.Bardsley@arm.com 11710260SAndrew.Bardsley@arm.com /** 11810260SAndrew.Bardsley@arm.com * post an RTC interrupt to the CPU 11910315Snilay@cs.wisc.edu */ 12010260SAndrew.Bardsley@arm.com void postRTC(); 12110260SAndrew.Bardsley@arm.com 12211570SCurtis.Dunham@arm.com /** 12310260SAndrew.Bardsley@arm.com * post an interrupt to the CPU. 12410260SAndrew.Bardsley@arm.com * @param interrupt the interrupt number to post (0-64) 12510260SAndrew.Bardsley@arm.com */ 12610260SAndrew.Bardsley@arm.com void postDRIR(uint32_t interrupt); 12710260SAndrew.Bardsley@arm.com 12810260SAndrew.Bardsley@arm.com /** 12910900Snilay@cs.wisc.edu * clear an interrupt previously posted to the CPU. 13010260SAndrew.Bardsley@arm.com * @param interrupt the interrupt number to post (0-64) 13110260SAndrew.Bardsley@arm.com */ 13210260SAndrew.Bardsley@arm.com void clearDRIR(uint32_t interrupt); 13310260SAndrew.Bardsley@arm.com 13410260SAndrew.Bardsley@arm.com /** 13510260SAndrew.Bardsley@arm.com * post an ipi interrupt to the CPU. 13610260SAndrew.Bardsley@arm.com * @param ipintr the cpu number to clear(bitvector) 13710260SAndrew.Bardsley@arm.com */ 13811570SCurtis.Dunham@arm.com void clearIPI(uint64_t ipintr); 13911570SCurtis.Dunham@arm.com 14011570SCurtis.Dunham@arm.com /** 14111570SCurtis.Dunham@arm.com * clear a timer interrupt previously posted to the CPU. 14211570SCurtis.Dunham@arm.com * @param interrupt the cpu number to clear(bitvector) 14311570SCurtis.Dunham@arm.com */ 14410260SAndrew.Bardsley@arm.com void clearITI(uint64_t itintr); 14510260SAndrew.Bardsley@arm.com 14610260SAndrew.Bardsley@arm.com /** 14710260SAndrew.Bardsley@arm.com * request an interrupt be posted to the CPU. 14810260SAndrew.Bardsley@arm.com * @param ipreq the cpu number to interrupt(bitvector) 14911570SCurtis.Dunham@arm.com */ 15010260SAndrew.Bardsley@arm.com void reqIPI(uint64_t ipreq); 15110260SAndrew.Bardsley@arm.com 15211103Snilay@cs.wisc.edu 15310260SAndrew.Bardsley@arm.com /** 15411680SCurtis.Dunham@arm.com * Serialize this object to the given output stream. 15510260SAndrew.Bardsley@arm.com * @param os The stream to serialize to. 15610260SAndrew.Bardsley@arm.com */ 15711388Ssteve.reinhardt@amd.com virtual void serialize(std::ostream &os); 15811570SCurtis.Dunham@arm.com 15910636Snilay@cs.wisc.edu /** 16010260SAndrew.Bardsley@arm.com * Reconstruct the state of this object from a checkpoint. 16110260SAndrew.Bardsley@arm.com * @param cp The checkpoint use. 16210900Snilay@cs.wisc.edu * @param section The section name of this object 16310260SAndrew.Bardsley@arm.com */ 16410260SAndrew.Bardsley@arm.com virtual void unserialize(Checkpoint *cp, const std::string §ion); 16511570SCurtis.Dunham@arm.com 16611570SCurtis.Dunham@arm.com /** 16711570SCurtis.Dunham@arm.com * Return how long this access will take. 16811570SCurtis.Dunham@arm.com * @param req the memory request to calcuate 16910260SAndrew.Bardsley@arm.com * @return Tick when the request is done 17010260SAndrew.Bardsley@arm.com */ 17110260SAndrew.Bardsley@arm.com Tick cacheAccess(MemReqPtr &req); 17210260SAndrew.Bardsley@arm.com}; 17310260SAndrew.Bardsley@arm.com 17410260SAndrew.Bardsley@arm.com#endif // __TSUNAMI_CCHIP_HH__ 17510260SAndrew.Bardsley@arm.com