tsunami_cchip.hh revision 1722
14309Sgblack@eecs.umich.edu/* 24309Sgblack@eecs.umich.edu * Copyright (c) 2004 The Regents of The University of Michigan 34309Sgblack@eecs.umich.edu * All rights reserved. 44309Sgblack@eecs.umich.edu * 54309Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 64309Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 74309Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 84309Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 94309Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 104309Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 114309Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 124309Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 134309Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 144309Sgblack@eecs.umich.edu * this software without specific prior written permission. 154309Sgblack@eecs.umich.edu * 164309Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174309Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184309Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194309Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204309Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214309Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224309Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234309Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244309Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254309Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264309Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274309Sgblack@eecs.umich.edu */ 284309Sgblack@eecs.umich.edu 294309Sgblack@eecs.umich.edu/** @file 304309Sgblack@eecs.umich.edu * Emulation of the Tsunami CChip CSRs 314309Sgblack@eecs.umich.edu */ 324309Sgblack@eecs.umich.edu 334309Sgblack@eecs.umich.edu#ifndef __TSUNAMI_CCHIP_HH__ 344309Sgblack@eecs.umich.edu#define __TSUNAMI_CCHIP_HH__ 354309Sgblack@eecs.umich.edu 364309Sgblack@eecs.umich.edu#include "dev/tsunami.hh" 374309Sgblack@eecs.umich.edu#include "base/range.hh" 384309Sgblack@eecs.umich.edu#include "dev/io_device.hh" 394309Sgblack@eecs.umich.edu 404309Sgblack@eecs.umich.edu/** 414309Sgblack@eecs.umich.edu * Tsunami CChip CSR Emulation. This device includes all the interrupt 424309Sgblack@eecs.umich.edu * handling code for the chipset. 434309Sgblack@eecs.umich.edu */ 444309Sgblack@eecs.umich.educlass TsunamiCChip : public PioDevice 454309Sgblack@eecs.umich.edu{ 464309Sgblack@eecs.umich.edu private: 474309Sgblack@eecs.umich.edu /** The base address of this device */ 484309Sgblack@eecs.umich.edu Addr addr; 494309Sgblack@eecs.umich.edu 504309Sgblack@eecs.umich.edu /** The size of mappad from the above address */ 514309Sgblack@eecs.umich.edu static const Addr size = 0xfffffff; 524309Sgblack@eecs.umich.edu 534309Sgblack@eecs.umich.edu protected: 544309Sgblack@eecs.umich.edu /** 554309Sgblack@eecs.umich.edu * pointer to the tsunami object. 564309Sgblack@eecs.umich.edu * This is our access to all the other tsunami 574309Sgblack@eecs.umich.edu * devices. 584533Sgblack@eecs.umich.edu */ 594679Sgblack@eecs.umich.edu Tsunami *tsunami; 604679Sgblack@eecs.umich.edu 614679Sgblack@eecs.umich.edu /** 624533Sgblack@eecs.umich.edu * The dims are device interrupt mask registers. 634533Sgblack@eecs.umich.edu * One exists for each CPU, the DRIR X DIM = DIR 644537Sgblack@eecs.umich.edu */ 654533Sgblack@eecs.umich.edu uint64_t dim[Tsunami::Max_CPUs]; 664528Sgblack@eecs.umich.edu 674528Sgblack@eecs.umich.edu /** 684528Sgblack@eecs.umich.edu * The dirs are device interrupt registers. 694528Sgblack@eecs.umich.edu * One exists for each CPU, the DRIR X DIM = DIR 704528Sgblack@eecs.umich.edu */ 714605Sgblack@eecs.umich.edu uint64_t dir[Tsunami::Max_CPUs]; 724528Sgblack@eecs.umich.edu 734528Sgblack@eecs.umich.edu /** 744528Sgblack@eecs.umich.edu * This register contains bits for each PCI interrupt 754615Sgblack@eecs.umich.edu * that can occur. 764615Sgblack@eecs.umich.edu */ 774615Sgblack@eecs.umich.edu uint64_t drir; 784615Sgblack@eecs.umich.edu 794615Sgblack@eecs.umich.edu /** Indicator of which CPUs have an IPI interrupt */ 804615Sgblack@eecs.umich.edu uint64_t ipint; 814615Sgblack@eecs.umich.edu 824615Sgblack@eecs.umich.edu /** Indicator of which CPUs have an RTC interrupt */ 834615Sgblack@eecs.umich.edu uint64_t itint; 844615Sgblack@eecs.umich.edu 854615Sgblack@eecs.umich.edu public: 864615Sgblack@eecs.umich.edu /** 874863Sgblack@eecs.umich.edu * Initialize the Tsunami CChip by setting all of the 884615Sgblack@eecs.umich.edu * device register to 0. 894615Sgblack@eecs.umich.edu * @param name name of this device. 904615Sgblack@eecs.umich.edu * @param t pointer back to the Tsunami object that we belong to. 914615Sgblack@eecs.umich.edu * @param a address we are mapped at. 924953Sgblack@eecs.umich.edu * @param mmu pointer to the memory controller that sends us events. 934615Sgblack@eecs.umich.edu * @param hier object to store parameters universal the device hierarchy 944615Sgblack@eecs.umich.edu * @param bus The bus that this device is attached to 954863Sgblack@eecs.umich.edu */ 964863Sgblack@eecs.umich.edu TsunamiCChip(const std::string &name, Tsunami *t, Addr a, 974863Sgblack@eecs.umich.edu MemoryController *mmu, HierParams *hier, Bus *bus, 984863Sgblack@eecs.umich.edu Tick pio_latency); 994863Sgblack@eecs.umich.edu 1004863Sgblack@eecs.umich.edu /** 1014863Sgblack@eecs.umich.edu * Process a read to the CChip. 1024620Sgblack@eecs.umich.edu * @param req Contains the address to read from. 1034620Sgblack@eecs.umich.edu * @param data A pointer to write the read data to. 1044620Sgblack@eecs.umich.edu * @return The fault condition of the access. 1054615Sgblack@eecs.umich.edu */ 1064686Sgblack@eecs.umich.edu virtual Fault read(MemReqPtr &req, uint8_t *data); 1074686Sgblack@eecs.umich.edu 1084686Sgblack@eecs.umich.edu 1094686Sgblack@eecs.umich.edu /** 1104953Sgblack@eecs.umich.edu * Process a write to the CChip. 1114686Sgblack@eecs.umich.edu * @param req Contains the address to write to. 1124686Sgblack@eecs.umich.edu * @param data The data to write. 1134686Sgblack@eecs.umich.edu * @return The fault condition of the access. 1144686Sgblack@eecs.umich.edu */ 1154953Sgblack@eecs.umich.edu virtual Fault write(MemReqPtr &req, const uint8_t *data); 1164953Sgblack@eecs.umich.edu 1174686Sgblack@eecs.umich.edu /** 1184686Sgblack@eecs.umich.edu * post an RTC interrupt to the CPU 1194686Sgblack@eecs.umich.edu */ 1204686Sgblack@eecs.umich.edu void postRTC(); 1214615Sgblack@eecs.umich.edu 1224615Sgblack@eecs.umich.edu /** 1234615Sgblack@eecs.umich.edu * post an interrupt to the CPU. 1244615Sgblack@eecs.umich.edu * @param interrupt the interrupt number to post (0-64) 1254615Sgblack@eecs.umich.edu */ 1264615Sgblack@eecs.umich.edu void postDRIR(uint32_t interrupt); 1274615Sgblack@eecs.umich.edu 1285008Sgblack@eecs.umich.edu /** 1295008Sgblack@eecs.umich.edu * clear an interrupt previously posted to the CPU. 1305008Sgblack@eecs.umich.edu * @param interrupt the interrupt number to post (0-64) 1315008Sgblack@eecs.umich.edu */ 1325008Sgblack@eecs.umich.edu void clearDRIR(uint32_t interrupt); 1334528Sgblack@eecs.umich.edu 1344528Sgblack@eecs.umich.edu /** 135 * post an ipi interrupt to the CPU. 136 * @param ipintr the cpu number to clear(bitvector) 137 */ 138 void clearIPI(uint64_t ipintr); 139 140 /** 141 * clear a timer interrupt previously posted to the CPU. 142 * @param interrupt the cpu number to clear(bitvector) 143 */ 144 void clearITI(uint64_t itintr); 145 146 /** 147 * request an interrupt be posted to the CPU. 148 * @param ipreq the cpu number to interrupt(bitvector) 149 */ 150 void reqIPI(uint64_t ipreq); 151 152 153 /** 154 * Serialize this object to the given output stream. 155 * @param os The stream to serialize to. 156 */ 157 virtual void serialize(std::ostream &os); 158 159 /** 160 * Reconstruct the state of this object from a checkpoint. 161 * @param cp The checkpoint use. 162 * @param section The section name of this object 163 */ 164 virtual void unserialize(Checkpoint *cp, const std::string §ion); 165 166 /** 167 * Return how long this access will take. 168 * @param req the memory request to calcuate 169 * @return Tick when the request is done 170 */ 171 Tick cacheAccess(MemReqPtr &req); 172}; 173 174#endif // __TSUNAMI_CCHIP_HH__ 175