tsunami_cchip.cc revision 768 
1/* $Id$ */
2
3/* @file
4 * Tsunami CChip (processor, memory, or IO)
5 */
6
7#include <deque>
8#include <string>
9#include <vector>
10
11#include "base/trace.hh"
12#include "cpu/exec_context.hh"
13#include "dev/console.hh"
14#include "dev/etherdev.hh"
15#include "dev/scsi_ctrl.hh"
16#include "dev/tlaser_clock.hh"
17#include "dev/tsunami_cchip.hh"
18#include "dev/tsunamireg.h"
19#include "dev/tsunami.hh"
20#include "mem/functional_mem/memory_control.hh"
21#include "sim/builder.hh"
22#include "sim/system.hh"
23
24using namespace std;
25
26TsunamiCChip::TsunamiCChip(const string &name, /*Tsunami *t,*/
27                       Addr addr, Addr mask, MemoryController *mmu)
28    : MmapDevice(name, addr, mask, mmu)/*, tsunami(t) */
29{
30    for(int i=0; i < Tsunami::Max_CPUs; i++) {
31        dim[i] = 0;
32        dir[i] = 0;
33    }
34
35    drir = 0;
36}
37
38Fault
39TsunamiCChip::read(MemReqPtr req, uint8_t *data)
40{
41    DPRINTF(Tsunami, "read  va=%#x size=%d\n",
42            req->vaddr, req->size);
43
44    Addr daddr = (req->paddr & addr_mask) >> 6;
45//    ExecContext *xc = req->xc;
46//    int cpuid = xc->cpu_id;
47
48    switch (req->size) {
49
50      case sizeof(uint64_t):
51          switch(daddr) {
52              case TSDEV_CC_CSR:
53                  *(uint64_t*)data = 0x0;
54                  return No_Fault;
55              case TSDEV_CC_MTR:
56                  panic("TSDEV_CC_MTR not implemeted\n");
57                   return No_Fault;
58              case TSDEV_CC_MISC:
59                  panic("TSDEV_CC_MISC not implemented\n");
60                  return No_Fault;
61              case TSDEV_CC_AAR0:
62              case TSDEV_CC_AAR1:
63              case TSDEV_CC_AAR2:
64              case TSDEV_CC_AAR3:
65                  panic("TSDEV_CC_AARx not implemeted\n");
66                  return No_Fault;
67              case TSDEV_CC_DIM0:
68                  *(uint64_t*)data = dim[0];
69                  return No_Fault;
70              case TSDEV_CC_DIM1:
71                  *(uint64_t*)data = dim[1];
72                  return No_Fault;
73              case TSDEV_CC_DIM2:
74                  *(uint64_t*)data = dim[2];
75                  return No_Fault;
76              case TSDEV_CC_DIM3:
77                  *(uint64_t*)data = dim[3];
78                  return No_Fault;
79              case TSDEV_CC_DIR0:
80                  *(uint64_t*)data = dir[0];
81                  return No_Fault;
82              case TSDEV_CC_DIR1:
83                  *(uint64_t*)data = dir[1];
84                  return No_Fault;
85              case TSDEV_CC_DIR2:
86                  *(uint64_t*)data = dir[2];
87                  return No_Fault;
88              case TSDEV_CC_DIR3:
89                  *(uint64_t*)data = dir[3];
90                  return No_Fault;
91              case TSDEV_CC_DRIR:
92                  *(uint64_t*)data = drir;
93                  return No_Fault;
94              case TSDEV_CC_PRBEN:
95                  panic("TSDEV_CC_PRBEN not implemented\n");
96                  return No_Fault;
97              case TSDEV_CC_IIC0:
98              case TSDEV_CC_IIC1:
99              case TSDEV_CC_IIC2:
100              case TSDEV_CC_IIC3:
101                  panic("TSDEV_CC_IICx not implemented\n");
102                  return No_Fault;
103              case TSDEV_CC_MPR0:
104              case TSDEV_CC_MPR1:
105              case TSDEV_CC_MPR2:
106              case TSDEV_CC_MPR3:
107                  panic("TSDEV_CC_MPRx not implemented\n");
108                  return No_Fault;
109              default:
110                  panic("default in cchip read reached, accessing 0x%x\n");
111           } // uint64_t
112
113      break;
114      case sizeof(uint32_t):
115      case sizeof(uint16_t):
116      case sizeof(uint8_t):
117      default:
118        panic("invalid access size(?) for tsunami register!\n");
119    }
120    DPRINTFN("Tsunami CChip ERROR: read  daddr=%#x size=%d\n", daddr, req->size);
121
122    return No_Fault;
123}
124
125Fault
126TsunamiCChip::write(MemReqPtr req, const uint8_t *data)
127{
128    DPRINTF(Tsunami, "write - va=%#x size=%d \n",
129            req->vaddr, req->size);
130
131    Addr daddr = (req->paddr & addr_mask) >> 6;
132
133    switch (req->size) {
134
135      case sizeof(uint64_t):
136          switch(daddr) {
137              case TSDEV_CC_CSR:
138                  panic("TSDEV_CC_CSR write\n");
139                  return No_Fault;
140              case TSDEV_CC_MTR:
141                  panic("TSDEV_CC_MTR write not implemented\n");
142                   return No_Fault;
143              case TSDEV_CC_MISC:
144                  panic("TSDEV_CC_MISC write not implemented\n");
145                  return No_Fault;
146              case TSDEV_CC_AAR0:
147              case TSDEV_CC_AAR1:
148              case TSDEV_CC_AAR2:
149              case TSDEV_CC_AAR3:
150                  panic("TSDEV_CC_AARx write not implemeted\n");
151                  return No_Fault;
152              case TSDEV_CC_DIM0:
153                   dim[0] = *(uint64_t*)data;
154                  return No_Fault;
155              case TSDEV_CC_DIM1:
156                  dim[1] = *(uint64_t*)data;
157                  return No_Fault;
158              case TSDEV_CC_DIM2:
159                  dim[2] = *(uint64_t*)data;
160                  return No_Fault;
161              case TSDEV_CC_DIM3:
162                  dim[3] = *(uint64_t*)data;
163                  return No_Fault;
164              case TSDEV_CC_DIR0:
165              case TSDEV_CC_DIR1:
166              case TSDEV_CC_DIR2:
167              case TSDEV_CC_DIR3:
168                  panic("TSDEV_CC_DIR write not implemented\n");
169                  return No_Fault;
170              case TSDEV_CC_DRIR:
171                  panic("TSDEV_CC_DRIR write not implemented\n");
172                  return No_Fault;
173              case TSDEV_CC_PRBEN:
174                  panic("TSDEV_CC_PRBEN write not implemented\n");
175                  return No_Fault;
176              case TSDEV_CC_IIC0:
177              case TSDEV_CC_IIC1:
178              case TSDEV_CC_IIC2:
179              case TSDEV_CC_IIC3:
180                  panic("TSDEV_CC_IICx write not implemented\n");
181                  return No_Fault;
182              case TSDEV_CC_MPR0:
183              case TSDEV_CC_MPR1:
184              case TSDEV_CC_MPR2:
185              case TSDEV_CC_MPR3:
186                  panic("TSDEV_CC_MPRx write not implemented\n");
187                  return No_Fault;
188              default:
189                  panic("default in cchip read reached, accessing 0x%x\n");
190          }
191
192      break;
193      case sizeof(uint32_t):
194      case sizeof(uint16_t):
195      case sizeof(uint8_t):
196      default:
197        panic("invalid access size(?) for tsunami register!\n");
198    }
199
200    DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
201
202    return No_Fault;
203}
204
205void
206TsunamiCChip::serialize(std::ostream &os)
207{
208    // code should be written
209}
210
211void
212TsunamiCChip::unserialize(Checkpoint *cp, const std::string &section)
213{
214    //code should be written
215}
216
217BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
218
219 //   SimObjectParam<Tsunami *> tsunami;
220    SimObjectParam<MemoryController *> mmu;
221    Param<Addr> addr;
222    Param<Addr> mask;
223
224END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
225
226BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
227
228//    INIT_PARAM(tsunami, "Tsunami"),
229    INIT_PARAM(mmu, "Memory Controller"),
230    INIT_PARAM(addr, "Device Address"),
231    INIT_PARAM(mask, "Address Mask")
232
233END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
234
235CREATE_SIM_OBJECT(TsunamiCChip)
236{
237    return new TsunamiCChip(getInstanceName(), /*tsunami,*/ addr, mask, mmu);
238}
239
240REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)
241