tsunami_cchip.cc revision 768
110259SAndrew.Bardsley@arm.com/* $Id$ */ 213954Sgiacomo.gabrielli@arm.com 310259SAndrew.Bardsley@arm.com/* @file 410259SAndrew.Bardsley@arm.com * Tsunami CChip (processor, memory, or IO) 510259SAndrew.Bardsley@arm.com */ 610259SAndrew.Bardsley@arm.com 710259SAndrew.Bardsley@arm.com#include <deque> 810259SAndrew.Bardsley@arm.com#include <string> 910259SAndrew.Bardsley@arm.com#include <vector> 1010259SAndrew.Bardsley@arm.com 1110259SAndrew.Bardsley@arm.com#include "base/trace.hh" 1210259SAndrew.Bardsley@arm.com#include "cpu/exec_context.hh" 1310259SAndrew.Bardsley@arm.com#include "dev/console.hh" 1410259SAndrew.Bardsley@arm.com#include "dev/etherdev.hh" 1510259SAndrew.Bardsley@arm.com#include "dev/scsi_ctrl.hh" 1610259SAndrew.Bardsley@arm.com#include "dev/tlaser_clock.hh" 1710259SAndrew.Bardsley@arm.com#include "dev/tsunami_cchip.hh" 1810259SAndrew.Bardsley@arm.com#include "dev/tsunamireg.h" 1910259SAndrew.Bardsley@arm.com#include "dev/tsunami.hh" 2010259SAndrew.Bardsley@arm.com#include "mem/functional_mem/memory_control.hh" 2110259SAndrew.Bardsley@arm.com#include "sim/builder.hh" 2210259SAndrew.Bardsley@arm.com#include "sim/system.hh" 2310259SAndrew.Bardsley@arm.com 2410259SAndrew.Bardsley@arm.comusing namespace std; 2510259SAndrew.Bardsley@arm.com 2610259SAndrew.Bardsley@arm.comTsunamiCChip::TsunamiCChip(const string &name, /*Tsunami *t,*/ 2710259SAndrew.Bardsley@arm.com Addr addr, Addr mask, MemoryController *mmu) 2810259SAndrew.Bardsley@arm.com : MmapDevice(name, addr, mask, mmu)/*, tsunami(t) */ 2910259SAndrew.Bardsley@arm.com{ 3010259SAndrew.Bardsley@arm.com for(int i=0; i < Tsunami::Max_CPUs; i++) { 3110259SAndrew.Bardsley@arm.com dim[i] = 0; 3210259SAndrew.Bardsley@arm.com dir[i] = 0; 3310259SAndrew.Bardsley@arm.com } 3410259SAndrew.Bardsley@arm.com 3510259SAndrew.Bardsley@arm.com drir = 0; 3610259SAndrew.Bardsley@arm.com} 3710259SAndrew.Bardsley@arm.com 3810259SAndrew.Bardsley@arm.comFault 3910259SAndrew.Bardsley@arm.comTsunamiCChip::read(MemReqPtr req, uint8_t *data) 4011793Sbrandon.potter@amd.com{ 4111793Sbrandon.potter@amd.com DPRINTF(Tsunami, "read va=%#x size=%d\n", 4210259SAndrew.Bardsley@arm.com req->vaddr, req->size); 4310259SAndrew.Bardsley@arm.com 4410259SAndrew.Bardsley@arm.com Addr daddr = (req->paddr & addr_mask) >> 6; 4510259SAndrew.Bardsley@arm.com// ExecContext *xc = req->xc; 4610259SAndrew.Bardsley@arm.com// int cpuid = xc->cpu_id; 4710259SAndrew.Bardsley@arm.com 4810259SAndrew.Bardsley@arm.com switch (req->size) { 4910259SAndrew.Bardsley@arm.com 5010259SAndrew.Bardsley@arm.com case sizeof(uint64_t): 5110259SAndrew.Bardsley@arm.com switch(daddr) { 5210259SAndrew.Bardsley@arm.com case TSDEV_CC_CSR: 5310259SAndrew.Bardsley@arm.com *(uint64_t*)data = 0x0; 5410259SAndrew.Bardsley@arm.com return No_Fault; 5510259SAndrew.Bardsley@arm.com case TSDEV_CC_MTR: 5610259SAndrew.Bardsley@arm.com panic("TSDEV_CC_MTR not implemeted\n"); 5710259SAndrew.Bardsley@arm.com return No_Fault; 5810259SAndrew.Bardsley@arm.com case TSDEV_CC_MISC: 5910259SAndrew.Bardsley@arm.com panic("TSDEV_CC_MISC not implemented\n"); 6010259SAndrew.Bardsley@arm.com return No_Fault; 6110259SAndrew.Bardsley@arm.com case TSDEV_CC_AAR0: 6210259SAndrew.Bardsley@arm.com case TSDEV_CC_AAR1: 6310259SAndrew.Bardsley@arm.com case TSDEV_CC_AAR2: 6410259SAndrew.Bardsley@arm.com case TSDEV_CC_AAR3: 6510259SAndrew.Bardsley@arm.com panic("TSDEV_CC_AARx not implemeted\n"); 6610259SAndrew.Bardsley@arm.com return No_Fault; 6710259SAndrew.Bardsley@arm.com case TSDEV_CC_DIM0: 6810259SAndrew.Bardsley@arm.com *(uint64_t*)data = dim[0]; 6910259SAndrew.Bardsley@arm.com return No_Fault; 7010259SAndrew.Bardsley@arm.com case TSDEV_CC_DIM1: 7110259SAndrew.Bardsley@arm.com *(uint64_t*)data = dim[1]; 7210259SAndrew.Bardsley@arm.com return No_Fault; 7310259SAndrew.Bardsley@arm.com case TSDEV_CC_DIM2: 7410259SAndrew.Bardsley@arm.com *(uint64_t*)data = dim[2]; 7510259SAndrew.Bardsley@arm.com return No_Fault; 7610259SAndrew.Bardsley@arm.com case TSDEV_CC_DIM3: 7710259SAndrew.Bardsley@arm.com *(uint64_t*)data = dim[3]; 7810259SAndrew.Bardsley@arm.com return No_Fault; 7910259SAndrew.Bardsley@arm.com case TSDEV_CC_DIR0: 8010259SAndrew.Bardsley@arm.com *(uint64_t*)data = dir[0]; 8110259SAndrew.Bardsley@arm.com return No_Fault; 8210259SAndrew.Bardsley@arm.com case TSDEV_CC_DIR1: 8310259SAndrew.Bardsley@arm.com *(uint64_t*)data = dir[1]; 8410259SAndrew.Bardsley@arm.com return No_Fault; 8510259SAndrew.Bardsley@arm.com case TSDEV_CC_DIR2: 8610259SAndrew.Bardsley@arm.com *(uint64_t*)data = dir[2]; 8710259SAndrew.Bardsley@arm.com return No_Fault; 8810259SAndrew.Bardsley@arm.com case TSDEV_CC_DIR3: 8910259SAndrew.Bardsley@arm.com *(uint64_t*)data = dir[3]; 9011567Smitch.hayenga@arm.com return No_Fault; 9111567Smitch.hayenga@arm.com case TSDEV_CC_DRIR: 9211567Smitch.hayenga@arm.com *(uint64_t*)data = drir; 9311567Smitch.hayenga@arm.com return No_Fault; 9410259SAndrew.Bardsley@arm.com case TSDEV_CC_PRBEN: 9510259SAndrew.Bardsley@arm.com panic("TSDEV_CC_PRBEN not implemented\n"); 9610259SAndrew.Bardsley@arm.com return No_Fault; 9710259SAndrew.Bardsley@arm.com case TSDEV_CC_IIC0: 9810259SAndrew.Bardsley@arm.com case TSDEV_CC_IIC1: 9910259SAndrew.Bardsley@arm.com case TSDEV_CC_IIC2: 10010259SAndrew.Bardsley@arm.com case TSDEV_CC_IIC3: 10110259SAndrew.Bardsley@arm.com panic("TSDEV_CC_IICx not implemented\n"); 10210259SAndrew.Bardsley@arm.com return No_Fault; 10310259SAndrew.Bardsley@arm.com case TSDEV_CC_MPR0: 10410259SAndrew.Bardsley@arm.com case TSDEV_CC_MPR1: 10510259SAndrew.Bardsley@arm.com case TSDEV_CC_MPR2: 10610259SAndrew.Bardsley@arm.com case TSDEV_CC_MPR3: 10710259SAndrew.Bardsley@arm.com panic("TSDEV_CC_MPRx not implemented\n"); 10810259SAndrew.Bardsley@arm.com return No_Fault; 10910259SAndrew.Bardsley@arm.com default: 11010259SAndrew.Bardsley@arm.com panic("default in cchip read reached, accessing 0x%x\n"); 11110259SAndrew.Bardsley@arm.com } // uint64_t 11210259SAndrew.Bardsley@arm.com 11310259SAndrew.Bardsley@arm.com break; 11410259SAndrew.Bardsley@arm.com case sizeof(uint32_t): 11510259SAndrew.Bardsley@arm.com case sizeof(uint16_t): 11610259SAndrew.Bardsley@arm.com case sizeof(uint8_t): 11710259SAndrew.Bardsley@arm.com default: 11810259SAndrew.Bardsley@arm.com panic("invalid access size(?) for tsunami register!\n"); 11910259SAndrew.Bardsley@arm.com } 12010259SAndrew.Bardsley@arm.com DPRINTFN("Tsunami CChip ERROR: read daddr=%#x size=%d\n", daddr, req->size); 12110259SAndrew.Bardsley@arm.com 12210259SAndrew.Bardsley@arm.com return No_Fault; 12310259SAndrew.Bardsley@arm.com} 12410259SAndrew.Bardsley@arm.com 12510259SAndrew.Bardsley@arm.comFault 12610259SAndrew.Bardsley@arm.comTsunamiCChip::write(MemReqPtr req, const uint8_t *data) 12710259SAndrew.Bardsley@arm.com{ 12810259SAndrew.Bardsley@arm.com DPRINTF(Tsunami, "write - va=%#x size=%d \n", 12910259SAndrew.Bardsley@arm.com req->vaddr, req->size); 13010259SAndrew.Bardsley@arm.com 13110259SAndrew.Bardsley@arm.com Addr daddr = (req->paddr & addr_mask) >> 6; 13210259SAndrew.Bardsley@arm.com 13310259SAndrew.Bardsley@arm.com switch (req->size) { 13410259SAndrew.Bardsley@arm.com 13510259SAndrew.Bardsley@arm.com case sizeof(uint64_t): 13610259SAndrew.Bardsley@arm.com switch(daddr) { 13710259SAndrew.Bardsley@arm.com case TSDEV_CC_CSR: 13810259SAndrew.Bardsley@arm.com panic("TSDEV_CC_CSR write\n"); 13910259SAndrew.Bardsley@arm.com return No_Fault; 14010259SAndrew.Bardsley@arm.com case TSDEV_CC_MTR: 14110259SAndrew.Bardsley@arm.com panic("TSDEV_CC_MTR write not implemented\n"); 14210259SAndrew.Bardsley@arm.com return No_Fault; 14310259SAndrew.Bardsley@arm.com case TSDEV_CC_MISC: 14410259SAndrew.Bardsley@arm.com panic("TSDEV_CC_MISC write not implemented\n"); 14510259SAndrew.Bardsley@arm.com return No_Fault; 14610259SAndrew.Bardsley@arm.com case TSDEV_CC_AAR0: 14710259SAndrew.Bardsley@arm.com case TSDEV_CC_AAR1: 14810259SAndrew.Bardsley@arm.com case TSDEV_CC_AAR2: 14910814Sandreas.hansson@arm.com case TSDEV_CC_AAR3: 15010259SAndrew.Bardsley@arm.com panic("TSDEV_CC_AARx write not implemeted\n"); 15110259SAndrew.Bardsley@arm.com return No_Fault; 15210259SAndrew.Bardsley@arm.com case TSDEV_CC_DIM0: 15310259SAndrew.Bardsley@arm.com dim[0] = *(uint64_t*)data; 15410259SAndrew.Bardsley@arm.com return No_Fault; 15510259SAndrew.Bardsley@arm.com case TSDEV_CC_DIM1: 15610259SAndrew.Bardsley@arm.com dim[1] = *(uint64_t*)data; 15710259SAndrew.Bardsley@arm.com return No_Fault; 15810259SAndrew.Bardsley@arm.com case TSDEV_CC_DIM2: 15910259SAndrew.Bardsley@arm.com dim[2] = *(uint64_t*)data; 16010259SAndrew.Bardsley@arm.com return No_Fault; 16110259SAndrew.Bardsley@arm.com case TSDEV_CC_DIM3: 16210259SAndrew.Bardsley@arm.com dim[3] = *(uint64_t*)data; 16310259SAndrew.Bardsley@arm.com return No_Fault; 16410259SAndrew.Bardsley@arm.com case TSDEV_CC_DIR0: 16510259SAndrew.Bardsley@arm.com case TSDEV_CC_DIR1: 16610259SAndrew.Bardsley@arm.com case TSDEV_CC_DIR2: 16710259SAndrew.Bardsley@arm.com case TSDEV_CC_DIR3: 16810259SAndrew.Bardsley@arm.com panic("TSDEV_CC_DIR write not implemented\n"); 16911567Smitch.hayenga@arm.com return No_Fault; 17011567Smitch.hayenga@arm.com case TSDEV_CC_DRIR: 17111567Smitch.hayenga@arm.com panic("TSDEV_CC_DRIR write not implemented\n"); 17210259SAndrew.Bardsley@arm.com return No_Fault; 17311567Smitch.hayenga@arm.com case TSDEV_CC_PRBEN: 17411567Smitch.hayenga@arm.com panic("TSDEV_CC_PRBEN write not implemented\n"); 17511567Smitch.hayenga@arm.com return No_Fault; 17611567Smitch.hayenga@arm.com case TSDEV_CC_IIC0: 17711567Smitch.hayenga@arm.com case TSDEV_CC_IIC1: 17811567Smitch.hayenga@arm.com case TSDEV_CC_IIC2: 17911567Smitch.hayenga@arm.com case TSDEV_CC_IIC3: 18011567Smitch.hayenga@arm.com panic("TSDEV_CC_IICx write not implemented\n"); 18111567Smitch.hayenga@arm.com return No_Fault; 18211567Smitch.hayenga@arm.com case TSDEV_CC_MPR0: 18311567Smitch.hayenga@arm.com case TSDEV_CC_MPR1: 18411567Smitch.hayenga@arm.com case TSDEV_CC_MPR2: 18511567Smitch.hayenga@arm.com case TSDEV_CC_MPR3: 18611567Smitch.hayenga@arm.com panic("TSDEV_CC_MPRx write not implemented\n"); 18711567Smitch.hayenga@arm.com return No_Fault; 18811567Smitch.hayenga@arm.com default: 18911567Smitch.hayenga@arm.com panic("default in cchip read reached, accessing 0x%x\n"); 19011567Smitch.hayenga@arm.com } 19110259SAndrew.Bardsley@arm.com 19210259SAndrew.Bardsley@arm.com break; 19310259SAndrew.Bardsley@arm.com case sizeof(uint32_t): 19411567Smitch.hayenga@arm.com case sizeof(uint16_t): 19510259SAndrew.Bardsley@arm.com case sizeof(uint8_t): 19610259SAndrew.Bardsley@arm.com default: 19711567Smitch.hayenga@arm.com panic("invalid access size(?) for tsunami register!\n"); 19811567Smitch.hayenga@arm.com } 19910259SAndrew.Bardsley@arm.com 20011567Smitch.hayenga@arm.com DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size); 20110259SAndrew.Bardsley@arm.com 20210259SAndrew.Bardsley@arm.com return No_Fault; 20310259SAndrew.Bardsley@arm.com} 20410259SAndrew.Bardsley@arm.com 20510259SAndrew.Bardsley@arm.comvoid 20610259SAndrew.Bardsley@arm.comTsunamiCChip::serialize(std::ostream &os) 20711567Smitch.hayenga@arm.com{ 20810259SAndrew.Bardsley@arm.com // code should be written 20911567Smitch.hayenga@arm.com} 21011567Smitch.hayenga@arm.com 21110259SAndrew.Bardsley@arm.comvoid 21211567Smitch.hayenga@arm.comTsunamiCChip::unserialize(Checkpoint *cp, const std::string §ion) 21310259SAndrew.Bardsley@arm.com{ 21410259SAndrew.Bardsley@arm.com //code should be written 21510259SAndrew.Bardsley@arm.com} 21610259SAndrew.Bardsley@arm.com 21710259SAndrew.Bardsley@arm.comBEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip) 21810259SAndrew.Bardsley@arm.com 21910259SAndrew.Bardsley@arm.com // SimObjectParam<Tsunami *> tsunami; 22010259SAndrew.Bardsley@arm.com SimObjectParam<MemoryController *> mmu; 22110259SAndrew.Bardsley@arm.com Param<Addr> addr; 22212489Sgiacomo.travaglini@arm.com Param<Addr> mask; 22312489Sgiacomo.travaglini@arm.com 22410259SAndrew.Bardsley@arm.comEND_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip) 22510259SAndrew.Bardsley@arm.com 22610259SAndrew.Bardsley@arm.comBEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip) 22710259SAndrew.Bardsley@arm.com 22812489Sgiacomo.travaglini@arm.com// INIT_PARAM(tsunami, "Tsunami"), 22912489Sgiacomo.travaglini@arm.com INIT_PARAM(mmu, "Memory Controller"), 23010259SAndrew.Bardsley@arm.com INIT_PARAM(addr, "Device Address"), 23110259SAndrew.Bardsley@arm.com INIT_PARAM(mask, "Address Mask") 23210259SAndrew.Bardsley@arm.com 23310259SAndrew.Bardsley@arm.comEND_INIT_SIM_OBJECT_PARAMS(TsunamiCChip) 23410259SAndrew.Bardsley@arm.com 23510259SAndrew.Bardsley@arm.comCREATE_SIM_OBJECT(TsunamiCChip) 23610259SAndrew.Bardsley@arm.com{ 23710259SAndrew.Bardsley@arm.com return new TsunamiCChip(getInstanceName(), /*tsunami,*/ addr, mask, mmu); 23810259SAndrew.Bardsley@arm.com} 23910259SAndrew.Bardsley@arm.com 24010259SAndrew.Bardsley@arm.comREGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip) 24110259SAndrew.Bardsley@arm.com