tsunami_cchip.cc revision 768
13901Ssaidi@eecs.umich.edu/* $Id$ */
23388Sgblack@eecs.umich.edu
33388Sgblack@eecs.umich.edu/* @file
43388Sgblack@eecs.umich.edu * Tsunami CChip (processor, memory, or IO)
53388Sgblack@eecs.umich.edu */
63388Sgblack@eecs.umich.edu
73388Sgblack@eecs.umich.edu#include <deque>
83388Sgblack@eecs.umich.edu#include <string>
93388Sgblack@eecs.umich.edu#include <vector>
103388Sgblack@eecs.umich.edu
113388Sgblack@eecs.umich.edu#include "base/trace.hh"
123388Sgblack@eecs.umich.edu#include "cpu/exec_context.hh"
133388Sgblack@eecs.umich.edu#include "dev/console.hh"
143388Sgblack@eecs.umich.edu#include "dev/etherdev.hh"
153388Sgblack@eecs.umich.edu#include "dev/scsi_ctrl.hh"
163388Sgblack@eecs.umich.edu#include "dev/tlaser_clock.hh"
173388Sgblack@eecs.umich.edu#include "dev/tsunami_cchip.hh"
183388Sgblack@eecs.umich.edu#include "dev/tsunamireg.h"
193388Sgblack@eecs.umich.edu#include "dev/tsunami.hh"
203388Sgblack@eecs.umich.edu#include "mem/functional_mem/memory_control.hh"
213388Sgblack@eecs.umich.edu#include "sim/builder.hh"
223388Sgblack@eecs.umich.edu#include "sim/system.hh"
233388Sgblack@eecs.umich.edu
243388Sgblack@eecs.umich.eduusing namespace std;
253388Sgblack@eecs.umich.edu
263388Sgblack@eecs.umich.eduTsunamiCChip::TsunamiCChip(const string &name, /*Tsunami *t,*/
273388Sgblack@eecs.umich.edu                       Addr addr, Addr mask, MemoryController *mmu)
283388Sgblack@eecs.umich.edu    : MmapDevice(name, addr, mask, mmu)/*, tsunami(t) */
293388Sgblack@eecs.umich.edu{
303270SN/A    for(int i=0; i < Tsunami::Max_CPUs; i++) {
313270SN/A        dim[i] = 0;
323270SN/A        dir[i] = 0;
333270SN/A    }
343270SN/A
353270SN/A    drir = 0;
363270SN/A}
373270SN/A
383270SN/AFault
393270SN/ATsunamiCChip::read(MemReqPtr req, uint8_t *data)
403270SN/A{
413270SN/A    DPRINTF(Tsunami, "read  va=%#x size=%d\n",
423270SN/A            req->vaddr, req->size);
433270SN/A
443388Sgblack@eecs.umich.edu    Addr daddr = (req->paddr & addr_mask) >> 6;
453388Sgblack@eecs.umich.edu//    ExecContext *xc = req->xc;
463270SN/A//    int cpuid = xc->cpu_id;
473270SN/A
483270SN/A    switch (req->size) {
493270SN/A
503270SN/A      case sizeof(uint64_t):
513270SN/A          switch(daddr) {
523270SN/A              case TSDEV_CC_CSR:
533270SN/A                  *(uint64_t*)data = 0x0;
543388Sgblack@eecs.umich.edu                  return No_Fault;
553388Sgblack@eecs.umich.edu              case TSDEV_CC_MTR:
563270SN/A                  panic("TSDEV_CC_MTR not implemeted\n");
573270SN/A                   return No_Fault;
583270SN/A              case TSDEV_CC_MISC:
593440Sgblack@eecs.umich.edu                  panic("TSDEV_CC_MISC not implemented\n");
603270SN/A                  return No_Fault;
613270SN/A              case TSDEV_CC_AAR0:
623270SN/A              case TSDEV_CC_AAR1:
633270SN/A              case TSDEV_CC_AAR2:
643270SN/A              case TSDEV_CC_AAR3:
653270SN/A                  panic("TSDEV_CC_AARx not implemeted\n");
663440Sgblack@eecs.umich.edu                  return No_Fault;
673270SN/A              case TSDEV_CC_DIM0:
683270SN/A                  *(uint64_t*)data = dim[0];
693270SN/A                  return No_Fault;
703270SN/A              case TSDEV_CC_DIM1:
713270SN/A                  *(uint64_t*)data = dim[1];
723270SN/A                  return No_Fault;
733270SN/A              case TSDEV_CC_DIM2:
743270SN/A                  *(uint64_t*)data = dim[2];
753270SN/A                  return No_Fault;
763270SN/A              case TSDEV_CC_DIM3:
773270SN/A                  *(uint64_t*)data = dim[3];
783270SN/A                  return No_Fault;
793270SN/A              case TSDEV_CC_DIR0:
803270SN/A                  *(uint64_t*)data = dir[0];
813270SN/A                  return No_Fault;
823270SN/A              case TSDEV_CC_DIR1:
833270SN/A                  *(uint64_t*)data = dir[1];
843270SN/A                  return No_Fault;
853270SN/A              case TSDEV_CC_DIR2:
863270SN/A                  *(uint64_t*)data = dir[2];
873270SN/A                  return No_Fault;
883270SN/A              case TSDEV_CC_DIR3:
893270SN/A                  *(uint64_t*)data = dir[3];
903270SN/A                  return No_Fault;
913270SN/A              case TSDEV_CC_DRIR:
923270SN/A                  *(uint64_t*)data = drir;
933270SN/A                  return No_Fault;
943270SN/A              case TSDEV_CC_PRBEN:
953280SN/A                  panic("TSDEV_CC_PRBEN not implemented\n");
963270SN/A                  return No_Fault;
973270SN/A              case TSDEV_CC_IIC0:
983270SN/A              case TSDEV_CC_IIC1:
993270SN/A              case TSDEV_CC_IIC2:
1003270SN/A              case TSDEV_CC_IIC3:
1013270SN/A                  panic("TSDEV_CC_IICx not implemented\n");
1023270SN/A                  return No_Fault;
1037741Sgblack@eecs.umich.edu              case TSDEV_CC_MPR0:
1043270SN/A              case TSDEV_CC_MPR1:
1053270SN/A              case TSDEV_CC_MPR2:
1063270SN/A              case TSDEV_CC_MPR3:
1073270SN/A                  panic("TSDEV_CC_MPRx not implemented\n");
1083270SN/A                  return No_Fault;
1093270SN/A              default:
1103270SN/A                  panic("default in cchip read reached, accessing 0x%x\n");
1113270SN/A           } // uint64_t
1127741Sgblack@eecs.umich.edu
1133270SN/A      break;
1143270SN/A      case sizeof(uint32_t):
1153270SN/A      case sizeof(uint16_t):
1163270SN/A      case sizeof(uint8_t):
1173270SN/A      default:
1183270SN/A        panic("invalid access size(?) for tsunami register!\n");
1193270SN/A    }
1203280SN/A    DPRINTFN("Tsunami CChip ERROR: read  daddr=%#x size=%d\n", daddr, req->size);
1213270SN/A
1223270SN/A    return No_Fault;
1233270SN/A}
1243270SN/A
1253270SN/AFault
1263270SN/ATsunamiCChip::write(MemReqPtr req, const uint8_t *data)
1273270SN/A{
1287741Sgblack@eecs.umich.edu    DPRINTF(Tsunami, "write - va=%#x size=%d \n",
1293379SN/A            req->vaddr, req->size);
1303270SN/A
1313270SN/A    Addr daddr = (req->paddr & addr_mask) >> 6;
1323270SN/A
1333379SN/A    switch (req->size) {
1347741Sgblack@eecs.umich.edu
1353270SN/A      case sizeof(uint64_t):
1363270SN/A          switch(daddr) {
1373270SN/A              case TSDEV_CC_CSR:
1387741Sgblack@eecs.umich.edu                  panic("TSDEV_CC_CSR write\n");
1393270SN/A                  return No_Fault;
1403270SN/A              case TSDEV_CC_MTR:
1413270SN/A                  panic("TSDEV_CC_MTR write not implemented\n");
1423270SN/A                   return No_Fault;
1433270SN/A              case TSDEV_CC_MISC:
1443270SN/A                  panic("TSDEV_CC_MISC write not implemented\n");
1453270SN/A                  return No_Fault;
1463270SN/A              case TSDEV_CC_AAR0:
1473270SN/A              case TSDEV_CC_AAR1:
1483270SN/A              case TSDEV_CC_AAR2:
1493270SN/A              case TSDEV_CC_AAR3:
1503270SN/A                  panic("TSDEV_CC_AARx write not implemeted\n");
1513270SN/A                  return No_Fault;
1523270SN/A              case TSDEV_CC_DIM0:
1533270SN/A                   dim[0] = *(uint64_t*)data;
1543270SN/A                  return No_Fault;
1557741Sgblack@eecs.umich.edu              case TSDEV_CC_DIM1:
1563280SN/A                  dim[1] = *(uint64_t*)data;
1573270SN/A                  return No_Fault;
1583274SN/A              case TSDEV_CC_DIM2:
1593270SN/A                  dim[2] = *(uint64_t*)data;
1603270SN/A                  return No_Fault;
1613274SN/A              case TSDEV_CC_DIM3:
1627741Sgblack@eecs.umich.edu                  dim[3] = *(uint64_t*)data;
1633280SN/A                  return No_Fault;
1643270SN/A              case TSDEV_CC_DIR0:
1653391Sgblack@eecs.umich.edu              case TSDEV_CC_DIR1:
1663391Sgblack@eecs.umich.edu              case TSDEV_CC_DIR2:
1673270SN/A              case TSDEV_CC_DIR3:
1683270SN/A                  panic("TSDEV_CC_DIR write not implemented\n");
1693270SN/A                  return No_Fault;
1703270SN/A              case TSDEV_CC_DRIR:
1713274SN/A                  panic("TSDEV_CC_DRIR write not implemented\n");
1727741Sgblack@eecs.umich.edu                  return No_Fault;
1733280SN/A              case TSDEV_CC_PRBEN:
1743270SN/A                  panic("TSDEV_CC_PRBEN write not implemented\n");
1753391Sgblack@eecs.umich.edu                  return No_Fault;
1763391Sgblack@eecs.umich.edu              case TSDEV_CC_IIC0:
1773270SN/A              case TSDEV_CC_IIC1:
1783270SN/A              case TSDEV_CC_IIC2:
1793270SN/A              case TSDEV_CC_IIC3:
1803270SN/A                  panic("TSDEV_CC_IICx write not implemented\n");
1813274SN/A                  return No_Fault;
1827741Sgblack@eecs.umich.edu              case TSDEV_CC_MPR0:
1833280SN/A              case TSDEV_CC_MPR1:
1843270SN/A              case TSDEV_CC_MPR2:
1853391Sgblack@eecs.umich.edu              case TSDEV_CC_MPR3:
1863391Sgblack@eecs.umich.edu                  panic("TSDEV_CC_MPRx write not implemented\n");
1873270SN/A                  return No_Fault;
1883270SN/A              default:
1893270SN/A                  panic("default in cchip read reached, accessing 0x%x\n");
1903270SN/A          }
1913274SN/A
1927741Sgblack@eecs.umich.edu      break;
1933280SN/A      case sizeof(uint32_t):
1943270SN/A      case sizeof(uint16_t):
1953391Sgblack@eecs.umich.edu      case sizeof(uint8_t):
1963391Sgblack@eecs.umich.edu      default:
1973270SN/A        panic("invalid access size(?) for tsunami register!\n");
1983270SN/A    }
1993270SN/A
2003270SN/A    DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
2013274SN/A
2027741Sgblack@eecs.umich.edu    return No_Fault;
2033280SN/A}
2043270SN/A
2053391Sgblack@eecs.umich.eduvoid
2063391Sgblack@eecs.umich.eduTsunamiCChip::serialize(std::ostream &os)
2073270SN/A{
2083270SN/A    // code should be written
2093270SN/A}
2103270SN/A
2113274SN/Avoid
2127741Sgblack@eecs.umich.eduTsunamiCChip::unserialize(Checkpoint *cp, const std::string &section)
2133280SN/A{
2143270SN/A    //code should be written
2153391Sgblack@eecs.umich.edu}
2163391Sgblack@eecs.umich.edu
2173270SN/ABEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
2183270SN/A
2193270SN/A //   SimObjectParam<Tsunami *> tsunami;
2203270SN/A    SimObjectParam<MemoryController *> mmu;
2213274SN/A    Param<Addr> addr;
2227741Sgblack@eecs.umich.edu    Param<Addr> mask;
2233280SN/A
2243270SN/AEND_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
2253391Sgblack@eecs.umich.edu
2263391Sgblack@eecs.umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
2273270SN/A
2283270SN/A//    INIT_PARAM(tsunami, "Tsunami"),
2293270SN/A    INIT_PARAM(mmu, "Memory Controller"),
2303270SN/A    INIT_PARAM(addr, "Device Address"),
2313274SN/A    INIT_PARAM(mask, "Address Mask")
2327741Sgblack@eecs.umich.edu
2333280SN/AEND_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
2343270SN/A
2353391Sgblack@eecs.umich.eduCREATE_SIM_OBJECT(TsunamiCChip)
2363391Sgblack@eecs.umich.edu{
2373270SN/A    return new TsunamiCChip(getInstanceName(), /*tsunami,*/ addr, mask, mmu);
2383270SN/A}
2393270SN/A
2403270SN/AREGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)
2413270SN/A