backdoor.cc revision 3348
1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 * Ali Saidi 30 * Steve Reinhardt 31 * Erik Hallnor 32 */ 33 34/** @file 35 * Alpha Console Definition 36 */ 37 38#include <cstddef> 39#include <string> 40 41#include "arch/alpha/system.hh" 42#include "base/inifile.hh" 43#include "base/str.hh" 44#include "base/trace.hh" 45#include "cpu/base.hh" 46#include "cpu/thread_context.hh" 47#include "dev/alpha_console.hh" 48#include "dev/platform.hh" 49#include "dev/simconsole.hh" 50#include "dev/simple_disk.hh" 51#include "mem/packet.hh" 52#include "mem/packet_access.hh" 53#include "mem/physical.hh" 54#include "sim/builder.hh" 55#include "sim/sim_object.hh" 56 57using namespace std; 58using namespace AlphaISA; 59 60AlphaConsole::AlphaConsole(Params *p) 61 : BasicPioDevice(p), disk(p->disk), 62 console(params()->cons), system(params()->alpha_sys), cpu(params()->cpu) 63{ 64 65 pioSize = sizeof(struct AlphaAccess); 66 67 alphaAccess = new Access(); 68 alphaAccess->last_offset = pioSize - 1; 69 70 alphaAccess->version = ALPHA_ACCESS_VERSION; 71 alphaAccess->diskUnit = 1; 72 73 alphaAccess->diskCount = 0; 74 alphaAccess->diskPAddr = 0; 75 alphaAccess->diskBlock = 0; 76 alphaAccess->diskOperation = 0; 77 alphaAccess->outputChar = 0; 78 alphaAccess->inputChar = 0; 79 bzero(alphaAccess->cpuStack, sizeof(alphaAccess->cpuStack)); 80 81} 82 83void 84AlphaConsole::startup() 85{ 86 system->setAlphaAccess(pioAddr); 87 alphaAccess->numCPUs = system->getNumCPUs(); 88 alphaAccess->kernStart = system->getKernelStart(); 89 alphaAccess->kernEnd = system->getKernelEnd(); 90 alphaAccess->entryPoint = system->getKernelEntry(); 91 alphaAccess->mem_size = system->physmem->size(); 92 alphaAccess->cpuClock = cpu->frequency() / 1000000; // In MHz 93 alphaAccess->intrClockFrequency = params()->platform->intrFrequency(); 94} 95 96Tick 97AlphaConsole::read(Packet *pkt) 98{ 99 100 /** XXX Do we want to push the addr munging to a bus brige or something? So 101 * the device has it's physical address and then the bridge adds on whatever 102 * machine dependent address swizzle is required? 103 */ 104 105 assert(pkt->result == Packet::Unknown); 106 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 107 108 Addr daddr = pkt->getAddr() - pioAddr; 109 110 pkt->allocate(); 111 112 switch (pkt->getSize()) 113 { 114 case sizeof(uint32_t): 115 switch (daddr) 116 { 117 case offsetof(AlphaAccess, last_offset): 118 pkt->set(alphaAccess->last_offset); 119 break; 120 case offsetof(AlphaAccess, version): 121 pkt->set(alphaAccess->version); 122 break; 123 case offsetof(AlphaAccess, numCPUs): 124 pkt->set(alphaAccess->numCPUs); 125 break; 126 case offsetof(AlphaAccess, intrClockFrequency): 127 pkt->set(alphaAccess->intrClockFrequency); 128 break; 129 default: 130 /* Old console code read in everyting as a 32bit int 131 * we now break that for better error checking. 132 */ 133 pkt->result = Packet::BadAddress; 134 } 135 DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, 136 pkt->get<uint32_t>()); 137 break; 138 case sizeof(uint64_t): 139 switch (daddr) 140 { 141 case offsetof(AlphaAccess, inputChar): 142 pkt->set(console->console_in()); 143 break; 144 case offsetof(AlphaAccess, cpuClock): 145 pkt->set(alphaAccess->cpuClock); 146 break; 147 case offsetof(AlphaAccess, mem_size): 148 pkt->set(alphaAccess->mem_size); 149 break; 150 case offsetof(AlphaAccess, kernStart): 151 pkt->set(alphaAccess->kernStart); 152 break; 153 case offsetof(AlphaAccess, kernEnd): 154 pkt->set(alphaAccess->kernEnd); 155 break; 156 case offsetof(AlphaAccess, entryPoint): 157 pkt->set(alphaAccess->entryPoint); 158 break; 159 case offsetof(AlphaAccess, diskUnit): 160 pkt->set(alphaAccess->diskUnit); 161 break; 162 case offsetof(AlphaAccess, diskCount): 163 pkt->set(alphaAccess->diskCount); 164 break; 165 case offsetof(AlphaAccess, diskPAddr): 166 pkt->set(alphaAccess->diskPAddr); 167 break; 168 case offsetof(AlphaAccess, diskBlock): 169 pkt->set(alphaAccess->diskBlock); 170 break; 171 case offsetof(AlphaAccess, diskOperation): 172 pkt->set(alphaAccess->diskOperation); 173 break; 174 case offsetof(AlphaAccess, outputChar): 175 pkt->set(alphaAccess->outputChar); 176 break; 177 default: 178 int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) / 179 sizeof(alphaAccess->cpuStack[0]); 180 181 if (cpunum >= 0 && cpunum < 64) 182 pkt->set(alphaAccess->cpuStack[cpunum]); 183 else 184 panic("Unknown 64bit access, %#x\n", daddr); 185 } 186 DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, 187 pkt->get<uint64_t>()); 188 break; 189 default: 190 pkt->result = Packet::BadAddress; 191 } 192 if (pkt->result == Packet::Unknown) 193 pkt->result = Packet::Success; 194 return pioDelay; 195} 196 197Tick 198AlphaConsole::write(Packet *pkt) 199{ 200 assert(pkt->result == Packet::Unknown); 201 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 202 Addr daddr = pkt->getAddr() - pioAddr; 203 204 uint64_t val = pkt->get<uint64_t>(); 205 assert(pkt->getSize() == sizeof(uint64_t)); 206 207 switch (daddr) { 208 case offsetof(AlphaAccess, diskUnit): 209 alphaAccess->diskUnit = val; 210 break; 211 212 case offsetof(AlphaAccess, diskCount): 213 alphaAccess->diskCount = val; 214 break; 215 216 case offsetof(AlphaAccess, diskPAddr): 217 alphaAccess->diskPAddr = val; 218 break; 219 220 case offsetof(AlphaAccess, diskBlock): 221 alphaAccess->diskBlock = val; 222 break; 223 224 case offsetof(AlphaAccess, diskOperation): 225 if (val == 0x13) 226 disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock, 227 alphaAccess->diskCount); 228 else 229 panic("Invalid disk operation!"); 230 231 break; 232 233 case offsetof(AlphaAccess, outputChar): 234 console->out((char)(val & 0xff)); 235 break; 236 237 default: 238 int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) / 239 sizeof(alphaAccess->cpuStack[0]); 240 warn("%d: Trying to launch CPU number %d!", curTick, cpunum); 241 assert(val > 0 && "Must not access primary cpu"); 242 if (cpunum >= 0 && cpunum < 64) 243 alphaAccess->cpuStack[cpunum] = val; 244 else 245 panic("Unknown 64bit access, %#x\n", daddr); 246 } 247 248 pkt->result = Packet::Success; 249 250 return pioDelay; 251} 252 253void 254AlphaConsole::Access::serialize(ostream &os) 255{ 256 SERIALIZE_SCALAR(last_offset); 257 SERIALIZE_SCALAR(version); 258 SERIALIZE_SCALAR(numCPUs); 259 SERIALIZE_SCALAR(mem_size); 260 SERIALIZE_SCALAR(cpuClock); 261 SERIALIZE_SCALAR(intrClockFrequency); 262 SERIALIZE_SCALAR(kernStart); 263 SERIALIZE_SCALAR(kernEnd); 264 SERIALIZE_SCALAR(entryPoint); 265 SERIALIZE_SCALAR(diskUnit); 266 SERIALIZE_SCALAR(diskCount); 267 SERIALIZE_SCALAR(diskPAddr); 268 SERIALIZE_SCALAR(diskBlock); 269 SERIALIZE_SCALAR(diskOperation); 270 SERIALIZE_SCALAR(outputChar); 271 SERIALIZE_SCALAR(inputChar); 272 SERIALIZE_ARRAY(cpuStack,64); 273} 274 275void 276AlphaConsole::Access::unserialize(Checkpoint *cp, const std::string §ion) 277{ 278 UNSERIALIZE_SCALAR(last_offset); 279 UNSERIALIZE_SCALAR(version); 280 UNSERIALIZE_SCALAR(numCPUs); 281 UNSERIALIZE_SCALAR(mem_size); 282 UNSERIALIZE_SCALAR(cpuClock); 283 UNSERIALIZE_SCALAR(intrClockFrequency); 284 UNSERIALIZE_SCALAR(kernStart); 285 UNSERIALIZE_SCALAR(kernEnd); 286 UNSERIALIZE_SCALAR(entryPoint); 287 UNSERIALIZE_SCALAR(diskUnit); 288 UNSERIALIZE_SCALAR(diskCount); 289 UNSERIALIZE_SCALAR(diskPAddr); 290 UNSERIALIZE_SCALAR(diskBlock); 291 UNSERIALIZE_SCALAR(diskOperation); 292 UNSERIALIZE_SCALAR(outputChar); 293 UNSERIALIZE_SCALAR(inputChar); 294 UNSERIALIZE_ARRAY(cpuStack, 64); 295} 296 297void 298AlphaConsole::serialize(ostream &os) 299{ 300 alphaAccess->serialize(os); 301} 302 303void 304AlphaConsole::unserialize(Checkpoint *cp, const std::string §ion) 305{ 306 alphaAccess->unserialize(cp, section); 307} 308 309BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole) 310 311 SimObjectParam<SimConsole *> sim_console; 312 SimObjectParam<SimpleDisk *> disk; 313 Param<Addr> pio_addr; 314 SimObjectParam<AlphaSystem *> system; 315 SimObjectParam<BaseCPU *> cpu; 316 SimObjectParam<Platform *> platform; 317 Param<Tick> pio_latency; 318 319END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole) 320 321BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole) 322 323 INIT_PARAM(sim_console, "The Simulator Console"), 324 INIT_PARAM(disk, "Simple Disk"), 325 INIT_PARAM(pio_addr, "Device Address"), 326 INIT_PARAM(system, "system object"), 327 INIT_PARAM(cpu, "Processor"), 328 INIT_PARAM(platform, "platform"), 329 INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000) 330 331END_INIT_SIM_OBJECT_PARAMS(AlphaConsole) 332 333CREATE_SIM_OBJECT(AlphaConsole) 334{ 335 AlphaConsole::Params *p = new AlphaConsole::Params; 336 p->name = getInstanceName(); 337 p->platform = platform; 338 p->pio_addr = pio_addr; 339 p->pio_delay = pio_latency; 340 p->cons = sim_console; 341 p->disk = disk; 342 p->alpha_sys = system; 343 p->system = system; 344 p->cpu = cpu; 345 return new AlphaConsole(p); 346} 347 348REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole) 349