backdoor.cc revision 4395
110448Snilay@cs.wisc.edu/* 210448Snilay@cs.wisc.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 310448Snilay@cs.wisc.edu * All rights reserved. 410448Snilay@cs.wisc.edu * 510448Snilay@cs.wisc.edu * Redistribution and use in source and binary forms, with or without 610448Snilay@cs.wisc.edu * modification, are permitted provided that the following conditions are 710448Snilay@cs.wisc.edu * met: redistributions of source code must retain the above copyright 810448Snilay@cs.wisc.edu * notice, this list of conditions and the following disclaimer; 910448Snilay@cs.wisc.edu * redistributions in binary form must reproduce the above copyright 1010448Snilay@cs.wisc.edu * notice, this list of conditions and the following disclaimer in the 1110448Snilay@cs.wisc.edu * documentation and/or other materials provided with the distribution; 1210448Snilay@cs.wisc.edu * neither the name of the copyright holders nor the names of its 1310448Snilay@cs.wisc.edu * contributors may be used to endorse or promote products derived from 1410448Snilay@cs.wisc.edu * this software without specific prior written permission. 1510448Snilay@cs.wisc.edu * 1610448Snilay@cs.wisc.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710448Snilay@cs.wisc.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810448Snilay@cs.wisc.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910448Snilay@cs.wisc.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010448Snilay@cs.wisc.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110448Snilay@cs.wisc.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210447Snilay@cs.wisc.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310447Snilay@cs.wisc.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410447Snilay@cs.wisc.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510447Snilay@cs.wisc.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610447Snilay@cs.wisc.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710447Snilay@cs.wisc.edu * 2810447Snilay@cs.wisc.edu * Authors: Nathan Binkert 2910447Snilay@cs.wisc.edu * Ali Saidi 3010447Snilay@cs.wisc.edu * Steve Reinhardt 3110447Snilay@cs.wisc.edu * Erik Hallnor 3210447Snilay@cs.wisc.edu */ 3310447Snilay@cs.wisc.edu 3410447Snilay@cs.wisc.edu/** @file 3510447Snilay@cs.wisc.edu * Alpha Console Definition 3610447Snilay@cs.wisc.edu */ 3710447Snilay@cs.wisc.edu 3810447Snilay@cs.wisc.edu#include <cstddef> 3910447Snilay@cs.wisc.edu#include <string> 4010447Snilay@cs.wisc.edu 4110447Snilay@cs.wisc.edu#include "arch/alpha/system.hh" 4210447Snilay@cs.wisc.edu#include "base/inifile.hh" 4310447Snilay@cs.wisc.edu#include "base/str.hh" 4410447Snilay@cs.wisc.edu#include "base/trace.hh" 4510447Snilay@cs.wisc.edu#include "cpu/base.hh" 4610447Snilay@cs.wisc.edu#include "cpu/thread_context.hh" 4710447Snilay@cs.wisc.edu#include "dev/alpha/console.hh" 4810447Snilay@cs.wisc.edu#include "dev/platform.hh" 4910447Snilay@cs.wisc.edu#include "dev/simconsole.hh" 5010447Snilay@cs.wisc.edu#include "dev/simple_disk.hh" 5110447Snilay@cs.wisc.edu#include "mem/packet.hh" 5210447Snilay@cs.wisc.edu#include "mem/packet_access.hh" 5310447Snilay@cs.wisc.edu#include "mem/physical.hh" 5410447Snilay@cs.wisc.edu#include "sim/builder.hh" 5510447Snilay@cs.wisc.edu#include "sim/sim_object.hh" 5610447Snilay@cs.wisc.edu 5710447Snilay@cs.wisc.eduusing namespace std; 5810447Snilay@cs.wisc.eduusing namespace AlphaISA; 5910447Snilay@cs.wisc.edu 6010447Snilay@cs.wisc.eduAlphaConsole::AlphaConsole(Params *p) 6110447Snilay@cs.wisc.edu : BasicPioDevice(p), disk(p->disk), 6210447Snilay@cs.wisc.edu console(params()->cons), system(params()->alpha_sys), cpu(params()->cpu) 6310447Snilay@cs.wisc.edu{ 6410447Snilay@cs.wisc.edu 6510447Snilay@cs.wisc.edu pioSize = sizeof(struct AlphaAccess); 6610447Snilay@cs.wisc.edu 6710447Snilay@cs.wisc.edu alphaAccess = new Access(); 6810447Snilay@cs.wisc.edu alphaAccess->last_offset = pioSize - 1; 6910447Snilay@cs.wisc.edu 7010447Snilay@cs.wisc.edu alphaAccess->version = ALPHA_ACCESS_VERSION; 7110447Snilay@cs.wisc.edu alphaAccess->diskUnit = 1; 7210447Snilay@cs.wisc.edu 7310447Snilay@cs.wisc.edu alphaAccess->diskCount = 0; 7410447Snilay@cs.wisc.edu alphaAccess->diskPAddr = 0; 7510447Snilay@cs.wisc.edu alphaAccess->diskBlock = 0; 7610447Snilay@cs.wisc.edu alphaAccess->diskOperation = 0; 7710447Snilay@cs.wisc.edu alphaAccess->outputChar = 0; 7810447Snilay@cs.wisc.edu alphaAccess->inputChar = 0; 7910447Snilay@cs.wisc.edu std::memset(alphaAccess->cpuStack, 0, sizeof(alphaAccess->cpuStack)); 8010447Snilay@cs.wisc.edu 8110447Snilay@cs.wisc.edu} 8210447Snilay@cs.wisc.edu 8310447Snilay@cs.wisc.eduvoid 8410447Snilay@cs.wisc.eduAlphaConsole::startup() 8510447Snilay@cs.wisc.edu{ 8610447Snilay@cs.wisc.edu system->setAlphaAccess(pioAddr); 8710447Snilay@cs.wisc.edu alphaAccess->numCPUs = system->getNumCPUs(); 8810447Snilay@cs.wisc.edu alphaAccess->kernStart = system->getKernelStart(); 8910447Snilay@cs.wisc.edu alphaAccess->kernEnd = system->getKernelEnd(); 9010447Snilay@cs.wisc.edu alphaAccess->entryPoint = system->getKernelEntry(); 9110447Snilay@cs.wisc.edu alphaAccess->mem_size = system->physmem->size(); 9210447Snilay@cs.wisc.edu alphaAccess->cpuClock = cpu->frequency() / 1000000; // In MHz 9310447Snilay@cs.wisc.edu alphaAccess->intrClockFrequency = params()->platform->intrFrequency(); 9410447Snilay@cs.wisc.edu} 9510447Snilay@cs.wisc.edu 9610447Snilay@cs.wisc.eduTick 9710447Snilay@cs.wisc.eduAlphaConsole::read(PacketPtr pkt) 9810447Snilay@cs.wisc.edu{ 9910447Snilay@cs.wisc.edu 10010447Snilay@cs.wisc.edu /** XXX Do we want to push the addr munging to a bus brige or something? So 10110447Snilay@cs.wisc.edu * the device has it's physical address and then the bridge adds on whatever 10210447Snilay@cs.wisc.edu * machine dependent address swizzle is required? 10310447Snilay@cs.wisc.edu */ 10410447Snilay@cs.wisc.edu 10510447Snilay@cs.wisc.edu assert(pkt->result == Packet::Unknown); 10610447Snilay@cs.wisc.edu assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 10710447Snilay@cs.wisc.edu 10810447Snilay@cs.wisc.edu Addr daddr = pkt->getAddr() - pioAddr; 10910447Snilay@cs.wisc.edu 11010447Snilay@cs.wisc.edu pkt->allocate(); 11110447Snilay@cs.wisc.edu 11210447Snilay@cs.wisc.edu switch (pkt->getSize()) 11310447Snilay@cs.wisc.edu { 11410447Snilay@cs.wisc.edu case sizeof(uint32_t): 11510447Snilay@cs.wisc.edu switch (daddr) 11610447Snilay@cs.wisc.edu { 11710447Snilay@cs.wisc.edu case offsetof(AlphaAccess, last_offset): 11810447Snilay@cs.wisc.edu pkt->set(alphaAccess->last_offset); 11910447Snilay@cs.wisc.edu break; 12010447Snilay@cs.wisc.edu case offsetof(AlphaAccess, version): 12110447Snilay@cs.wisc.edu pkt->set(alphaAccess->version); 12210447Snilay@cs.wisc.edu break; 12310447Snilay@cs.wisc.edu case offsetof(AlphaAccess, numCPUs): 12410447Snilay@cs.wisc.edu pkt->set(alphaAccess->numCPUs); 12510447Snilay@cs.wisc.edu break; 12610447Snilay@cs.wisc.edu case offsetof(AlphaAccess, intrClockFrequency): 12710447Snilay@cs.wisc.edu pkt->set(alphaAccess->intrClockFrequency); 12810447Snilay@cs.wisc.edu break; 12910447Snilay@cs.wisc.edu default: 13010447Snilay@cs.wisc.edu /* Old console code read in everyting as a 32bit int 13110447Snilay@cs.wisc.edu * we now break that for better error checking. 13210447Snilay@cs.wisc.edu */ 13310447Snilay@cs.wisc.edu pkt->result = Packet::BadAddress; 13410447Snilay@cs.wisc.edu } 13510447Snilay@cs.wisc.edu DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, 13610447Snilay@cs.wisc.edu pkt->get<uint32_t>()); 13710447Snilay@cs.wisc.edu break; 13810447Snilay@cs.wisc.edu case sizeof(uint64_t): 13910447Snilay@cs.wisc.edu switch (daddr) 14010447Snilay@cs.wisc.edu { 14110447Snilay@cs.wisc.edu case offsetof(AlphaAccess, inputChar): 14210447Snilay@cs.wisc.edu pkt->set(console->console_in()); 14310447Snilay@cs.wisc.edu break; 14410447Snilay@cs.wisc.edu case offsetof(AlphaAccess, cpuClock): 14510447Snilay@cs.wisc.edu pkt->set(alphaAccess->cpuClock); 14610447Snilay@cs.wisc.edu break; 14710447Snilay@cs.wisc.edu case offsetof(AlphaAccess, mem_size): 14810447Snilay@cs.wisc.edu pkt->set(alphaAccess->mem_size); 14910447Snilay@cs.wisc.edu break; 15010447Snilay@cs.wisc.edu case offsetof(AlphaAccess, kernStart): 15110447Snilay@cs.wisc.edu pkt->set(alphaAccess->kernStart); 15210447Snilay@cs.wisc.edu break; 15310447Snilay@cs.wisc.edu case offsetof(AlphaAccess, kernEnd): 15410447Snilay@cs.wisc.edu pkt->set(alphaAccess->kernEnd); 15510447Snilay@cs.wisc.edu break; 15610447Snilay@cs.wisc.edu case offsetof(AlphaAccess, entryPoint): 15710447Snilay@cs.wisc.edu pkt->set(alphaAccess->entryPoint); 15810447Snilay@cs.wisc.edu break; 15910447Snilay@cs.wisc.edu case offsetof(AlphaAccess, diskUnit): 16010447Snilay@cs.wisc.edu pkt->set(alphaAccess->diskUnit); 16110447Snilay@cs.wisc.edu break; 16210447Snilay@cs.wisc.edu case offsetof(AlphaAccess, diskCount): 16310447Snilay@cs.wisc.edu pkt->set(alphaAccess->diskCount); 16410447Snilay@cs.wisc.edu break; 16510447Snilay@cs.wisc.edu case offsetof(AlphaAccess, diskPAddr): 16610447Snilay@cs.wisc.edu pkt->set(alphaAccess->diskPAddr); 16710447Snilay@cs.wisc.edu break; 16810447Snilay@cs.wisc.edu case offsetof(AlphaAccess, diskBlock): 16910447Snilay@cs.wisc.edu pkt->set(alphaAccess->diskBlock); 17010447Snilay@cs.wisc.edu break; 17110447Snilay@cs.wisc.edu case offsetof(AlphaAccess, diskOperation): 17210447Snilay@cs.wisc.edu pkt->set(alphaAccess->diskOperation); 17310447Snilay@cs.wisc.edu break; 17410447Snilay@cs.wisc.edu case offsetof(AlphaAccess, outputChar): 17510447Snilay@cs.wisc.edu pkt->set(alphaAccess->outputChar); 17610447Snilay@cs.wisc.edu break; 17710447Snilay@cs.wisc.edu default: 17810447Snilay@cs.wisc.edu int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) / 17910447Snilay@cs.wisc.edu sizeof(alphaAccess->cpuStack[0]); 18010447Snilay@cs.wisc.edu 18110447Snilay@cs.wisc.edu if (cpunum >= 0 && cpunum < 64) 18210447Snilay@cs.wisc.edu pkt->set(alphaAccess->cpuStack[cpunum]); 18310447Snilay@cs.wisc.edu else 18410447Snilay@cs.wisc.edu panic("Unknown 64bit access, %#x\n", daddr); 18510447Snilay@cs.wisc.edu } 18610447Snilay@cs.wisc.edu DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, 18710447Snilay@cs.wisc.edu pkt->get<uint64_t>()); 18810447Snilay@cs.wisc.edu break; 18910447Snilay@cs.wisc.edu default: 19010447Snilay@cs.wisc.edu pkt->result = Packet::BadAddress; 19110447Snilay@cs.wisc.edu } 19210447Snilay@cs.wisc.edu if (pkt->result == Packet::Unknown) 19310447Snilay@cs.wisc.edu pkt->result = Packet::Success; 19410447Snilay@cs.wisc.edu return pioDelay; 19510447Snilay@cs.wisc.edu} 19610447Snilay@cs.wisc.edu 19710447Snilay@cs.wisc.eduTick 19810447Snilay@cs.wisc.eduAlphaConsole::write(PacketPtr pkt) 19910447Snilay@cs.wisc.edu{ 20010447Snilay@cs.wisc.edu assert(pkt->result == Packet::Unknown); 20110447Snilay@cs.wisc.edu assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 20210447Snilay@cs.wisc.edu Addr daddr = pkt->getAddr() - pioAddr; 20310447Snilay@cs.wisc.edu 20410447Snilay@cs.wisc.edu uint64_t val = pkt->get<uint64_t>(); 20510447Snilay@cs.wisc.edu assert(pkt->getSize() == sizeof(uint64_t)); 20610447Snilay@cs.wisc.edu 20710447Snilay@cs.wisc.edu switch (daddr) { 20810447Snilay@cs.wisc.edu case offsetof(AlphaAccess, diskUnit): 20910447Snilay@cs.wisc.edu alphaAccess->diskUnit = val; 21010447Snilay@cs.wisc.edu break; 21110447Snilay@cs.wisc.edu 21210447Snilay@cs.wisc.edu case offsetof(AlphaAccess, diskCount): 21310447Snilay@cs.wisc.edu alphaAccess->diskCount = val; 21410447Snilay@cs.wisc.edu break; 21510447Snilay@cs.wisc.edu 21610447Snilay@cs.wisc.edu case offsetof(AlphaAccess, diskPAddr): 21710447Snilay@cs.wisc.edu alphaAccess->diskPAddr = val; 21810447Snilay@cs.wisc.edu break; 21910447Snilay@cs.wisc.edu 22010447Snilay@cs.wisc.edu case offsetof(AlphaAccess, diskBlock): 22110447Snilay@cs.wisc.edu alphaAccess->diskBlock = val; 22210447Snilay@cs.wisc.edu break; 22310447Snilay@cs.wisc.edu 22410447Snilay@cs.wisc.edu case offsetof(AlphaAccess, diskOperation): 22510447Snilay@cs.wisc.edu if (val == 0x13) 22610447Snilay@cs.wisc.edu disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock, 22710447Snilay@cs.wisc.edu alphaAccess->diskCount); 22810447Snilay@cs.wisc.edu else 22910447Snilay@cs.wisc.edu panic("Invalid disk operation!"); 23010447Snilay@cs.wisc.edu 23110447Snilay@cs.wisc.edu break; 23210447Snilay@cs.wisc.edu 23310447Snilay@cs.wisc.edu case offsetof(AlphaAccess, outputChar): 23410447Snilay@cs.wisc.edu console->out((char)(val & 0xff)); 23510447Snilay@cs.wisc.edu break; 23610447Snilay@cs.wisc.edu 23710447Snilay@cs.wisc.edu default: 23810447Snilay@cs.wisc.edu int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) / 23910447Snilay@cs.wisc.edu sizeof(alphaAccess->cpuStack[0]); 24010447Snilay@cs.wisc.edu warn("%d: Trying to launch CPU number %d!", curTick, cpunum); 24110447Snilay@cs.wisc.edu assert(val > 0 && "Must not access primary cpu"); 24210447Snilay@cs.wisc.edu if (cpunum >= 0 && cpunum < 64) 24310447Snilay@cs.wisc.edu alphaAccess->cpuStack[cpunum] = val; 24410447Snilay@cs.wisc.edu else 24510447Snilay@cs.wisc.edu panic("Unknown 64bit access, %#x\n", daddr); 24610447Snilay@cs.wisc.edu } 24710447Snilay@cs.wisc.edu 24810447Snilay@cs.wisc.edu pkt->result = Packet::Success; 24910447Snilay@cs.wisc.edu 25010447Snilay@cs.wisc.edu return pioDelay; 25110447Snilay@cs.wisc.edu} 25210447Snilay@cs.wisc.edu 25310447Snilay@cs.wisc.eduvoid 25410447Snilay@cs.wisc.eduAlphaConsole::Access::serialize(ostream &os) 25510447Snilay@cs.wisc.edu{ 25610447Snilay@cs.wisc.edu SERIALIZE_SCALAR(last_offset); 25710447Snilay@cs.wisc.edu SERIALIZE_SCALAR(version); 25810447Snilay@cs.wisc.edu SERIALIZE_SCALAR(numCPUs); 25910447Snilay@cs.wisc.edu SERIALIZE_SCALAR(mem_size); 26010447Snilay@cs.wisc.edu SERIALIZE_SCALAR(cpuClock); 26110447Snilay@cs.wisc.edu SERIALIZE_SCALAR(intrClockFrequency); 26210447Snilay@cs.wisc.edu SERIALIZE_SCALAR(kernStart); 26310447Snilay@cs.wisc.edu SERIALIZE_SCALAR(kernEnd); 26410447Snilay@cs.wisc.edu SERIALIZE_SCALAR(entryPoint); 26510447Snilay@cs.wisc.edu SERIALIZE_SCALAR(diskUnit); 26610447Snilay@cs.wisc.edu SERIALIZE_SCALAR(diskCount); 26710447Snilay@cs.wisc.edu SERIALIZE_SCALAR(diskPAddr); 26810447Snilay@cs.wisc.edu SERIALIZE_SCALAR(diskBlock); 26910447Snilay@cs.wisc.edu SERIALIZE_SCALAR(diskOperation); 27010447Snilay@cs.wisc.edu SERIALIZE_SCALAR(outputChar); 27110447Snilay@cs.wisc.edu SERIALIZE_SCALAR(inputChar); 27210447Snilay@cs.wisc.edu SERIALIZE_ARRAY(cpuStack,64); 27310447Snilay@cs.wisc.edu} 27410447Snilay@cs.wisc.edu 27510447Snilay@cs.wisc.eduvoid 27610447Snilay@cs.wisc.eduAlphaConsole::Access::unserialize(Checkpoint *cp, const std::string §ion) 27710447Snilay@cs.wisc.edu{ 27810447Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(last_offset); 27910447Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(version); 28010447Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(numCPUs); 28110447Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(mem_size); 28210447Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(cpuClock); 28310447Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(intrClockFrequency); 28410447Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(kernStart); 28510447Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(kernEnd); 28610447Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(entryPoint); 28710447Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(diskUnit); 28810447Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(diskCount); 28910447Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(diskPAddr); 29010447Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(diskBlock); 29110447Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(diskOperation); 29210447Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(outputChar); 29310447Snilay@cs.wisc.edu UNSERIALIZE_SCALAR(inputChar); 29410447Snilay@cs.wisc.edu UNSERIALIZE_ARRAY(cpuStack, 64); 29510447Snilay@cs.wisc.edu} 29610447Snilay@cs.wisc.edu 29710447Snilay@cs.wisc.eduvoid 29810447Snilay@cs.wisc.eduAlphaConsole::serialize(ostream &os) 29910447Snilay@cs.wisc.edu{ 30010447Snilay@cs.wisc.edu alphaAccess->serialize(os); 30110447Snilay@cs.wisc.edu} 30210447Snilay@cs.wisc.edu 30310447Snilay@cs.wisc.eduvoid 30410447Snilay@cs.wisc.eduAlphaConsole::unserialize(Checkpoint *cp, const std::string §ion) 30510447Snilay@cs.wisc.edu{ 30610447Snilay@cs.wisc.edu alphaAccess->unserialize(cp, section); 30710447Snilay@cs.wisc.edu} 30810447Snilay@cs.wisc.edu 30910447Snilay@cs.wisc.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole) 31010447Snilay@cs.wisc.edu 31110447Snilay@cs.wisc.edu SimObjectParam<SimConsole *> sim_console; 31210447Snilay@cs.wisc.edu SimObjectParam<SimpleDisk *> disk; 31310447Snilay@cs.wisc.edu Param<Addr> pio_addr; 31410447Snilay@cs.wisc.edu SimObjectParam<AlphaSystem *> system; 31510447Snilay@cs.wisc.edu SimObjectParam<BaseCPU *> cpu; 31610447Snilay@cs.wisc.edu SimObjectParam<Platform *> platform; 31710447Snilay@cs.wisc.edu Param<Tick> pio_latency; 31810447Snilay@cs.wisc.edu 31910447Snilay@cs.wisc.eduEND_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole) 32010447Snilay@cs.wisc.edu 32110447Snilay@cs.wisc.eduBEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole) 32210447Snilay@cs.wisc.edu 32310447Snilay@cs.wisc.edu INIT_PARAM(sim_console, "The Simulator Console"), 32410447Snilay@cs.wisc.edu INIT_PARAM(disk, "Simple Disk"), 32510447Snilay@cs.wisc.edu INIT_PARAM(pio_addr, "Device Address"), 32610447Snilay@cs.wisc.edu INIT_PARAM(system, "system object"), 32710447Snilay@cs.wisc.edu INIT_PARAM(cpu, "Processor"), 32810447Snilay@cs.wisc.edu INIT_PARAM(platform, "platform"), 32910447Snilay@cs.wisc.edu INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000) 33010447Snilay@cs.wisc.edu 331END_INIT_SIM_OBJECT_PARAMS(AlphaConsole) 332 333CREATE_SIM_OBJECT(AlphaConsole) 334{ 335 AlphaConsole::Params *p = new AlphaConsole::Params; 336 p->name = getInstanceName(); 337 p->platform = platform; 338 p->pio_addr = pio_addr; 339 p->pio_delay = pio_latency; 340 p->cons = sim_console; 341 p->disk = disk; 342 p->alpha_sys = system; 343 p->system = system; 344 p->cpu = cpu; 345 return new AlphaConsole(p); 346} 347 348REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole) 349