backdoor.cc revision 2549 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file
30 * Alpha Console Definition
31 */
32
33#include <cstddef>
34#include <cstdio>
35#include <string>
36
37#include "arch/alpha/system.hh"
38#include "base/inifile.hh"
39#include "base/str.hh"
40#include "base/trace.hh"
41#include "cpu/base.hh"
42#include "cpu/exec_context.hh"
43#include "dev/alpha_console.hh"
44#include "dev/platform.hh"
45#include "dev/simconsole.hh"
46#include "dev/simple_disk.hh"
47#include "mem/physical.hh"
48#include "sim/builder.hh"
49#include "sim/sim_object.hh"
50
51using namespace std;
52using namespace AlphaISA;
53
54AlphaConsole::AlphaConsole(Params *p)
55    : BasicPioDevice(p), disk(p->disk),
56      console(params()->cons), system(params()->alpha_sys), cpu(params()->cpu)
57{
58
59    pioSize = sizeof(struct AlphaAccess);
60
61    alphaAccess = new Access();
62    alphaAccess->last_offset = pioSize - 1;
63
64    alphaAccess->version = ALPHA_ACCESS_VERSION;
65    alphaAccess->diskUnit = 1;
66
67    alphaAccess->diskCount = 0;
68    alphaAccess->diskPAddr = 0;
69    alphaAccess->diskBlock = 0;
70    alphaAccess->diskOperation = 0;
71    alphaAccess->outputChar = 0;
72    alphaAccess->inputChar = 0;
73    bzero(alphaAccess->cpuStack, sizeof(alphaAccess->cpuStack));
74
75}
76
77void
78AlphaConsole::startup()
79{
80    system->setAlphaAccess(pioAddr);
81    alphaAccess->numCPUs = system->getNumCPUs();
82    alphaAccess->kernStart = system->getKernelStart();
83    alphaAccess->kernEnd = system->getKernelEnd();
84    alphaAccess->entryPoint = system->getKernelEntry();
85    alphaAccess->mem_size = system->physmem->size();
86    alphaAccess->cpuClock = cpu->frequency() / 1000000; // In MHz
87    alphaAccess->intrClockFrequency = params()->platform->intrFrequency();
88}
89
90Tick
91AlphaConsole::read(Packet &pkt)
92{
93
94    /** XXX Do we want to push the addr munging to a bus brige or something? So
95     * the device has it's physical address and then the bridge adds on whatever
96     * machine dependent address swizzle is required?
97     */
98
99    assert(pkt.result == Unknown);
100    assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
101
102    pkt.time = curTick + pioDelay;
103    Addr daddr = pkt.addr - pioAddr;
104
105    uint32_t *data32;
106    uint64_t *data64;
107
108    switch (pkt.size)
109    {
110        case sizeof(uint32_t):
111            if (!pkt.data) {
112                data32 = new uint32_t;
113                pkt.data = (uint8_t*)data32;
114            } else
115                data32 = (uint32_t*)pkt.data;
116
117            switch (daddr)
118            {
119                case offsetof(AlphaAccess, last_offset):
120                    *data32 = alphaAccess->last_offset;
121                    break;
122                case offsetof(AlphaAccess, version):
123                    *data32 = alphaAccess->version;
124                    break;
125                case offsetof(AlphaAccess, numCPUs):
126                    *data32 = alphaAccess->numCPUs;
127                    break;
128                case offsetof(AlphaAccess, intrClockFrequency):
129                    *data32 = alphaAccess->intrClockFrequency;
130                    break;
131                default:
132                    /* Old console code read in everyting as a 32bit int
133                     * we now break that for better error checking.
134                     */
135                    pkt.result = BadAddress;
136            }
137            DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, *data32);
138            break;
139        case sizeof(uint64_t):
140            if (!pkt.data) {
141                data64 = new uint64_t;
142                pkt.data = (uint8_t*)data64;
143            } else
144                data64 = (uint64_t*)pkt.data;
145            switch (daddr)
146            {
147                case offsetof(AlphaAccess, inputChar):
148                    *data64 = console->console_in();
149                    break;
150                case offsetof(AlphaAccess, cpuClock):
151                    *data64 = alphaAccess->cpuClock;
152                    break;
153                case offsetof(AlphaAccess, mem_size):
154                    *data64 = alphaAccess->mem_size;
155                    break;
156                case offsetof(AlphaAccess, kernStart):
157                    *data64 = alphaAccess->kernStart;
158                    break;
159                case offsetof(AlphaAccess, kernEnd):
160                    *data64 = alphaAccess->kernEnd;
161                    break;
162                case offsetof(AlphaAccess, entryPoint):
163                    *data64 = alphaAccess->entryPoint;
164                    break;
165                case offsetof(AlphaAccess, diskUnit):
166                    *data64 = alphaAccess->diskUnit;
167                    break;
168                case offsetof(AlphaAccess, diskCount):
169                    *data64 = alphaAccess->diskCount;
170                    break;
171                case offsetof(AlphaAccess, diskPAddr):
172                    *data64 = alphaAccess->diskPAddr;
173                    break;
174                case offsetof(AlphaAccess, diskBlock):
175                    *data64 = alphaAccess->diskBlock;
176                    break;
177                case offsetof(AlphaAccess, diskOperation):
178                    *data64 = alphaAccess->diskOperation;
179                    break;
180                case offsetof(AlphaAccess, outputChar):
181                    *data64 = alphaAccess->outputChar;
182                    break;
183                default:
184                    int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
185                                 sizeof(alphaAccess->cpuStack[0]);
186
187                    if (cpunum >= 0 && cpunum < 64)
188                        *data64 = alphaAccess->cpuStack[cpunum];
189                    else
190                        panic("Unknown 64bit access, %#x\n", daddr);
191            }
192            DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, *data64);
193            break;
194        default:
195            pkt.result = BadAddress;
196    }
197    if (pkt.result == Unknown) pkt.result = Success;
198    return pioDelay;
199}
200
201Tick
202AlphaConsole::write(Packet &pkt)
203{
204    pkt.time = curTick + pioDelay;
205
206    assert(pkt.result == Unknown);
207    assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
208    Addr daddr = pkt.addr - pioAddr;
209
210    uint64_t val = *(uint64_t *)pkt.data;
211    assert(pkt.size == sizeof(uint64_t));
212
213    switch (daddr) {
214      case offsetof(AlphaAccess, diskUnit):
215        alphaAccess->diskUnit = val;
216        break;
217
218      case offsetof(AlphaAccess, diskCount):
219        alphaAccess->diskCount = val;
220        break;
221
222      case offsetof(AlphaAccess, diskPAddr):
223        alphaAccess->diskPAddr = val;
224        break;
225
226      case offsetof(AlphaAccess, diskBlock):
227        alphaAccess->diskBlock = val;
228        break;
229
230      case offsetof(AlphaAccess, diskOperation):
231        if (val == 0x13)
232            disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock,
233                       alphaAccess->diskCount);
234        else
235            panic("Invalid disk operation!");
236
237        break;
238
239      case offsetof(AlphaAccess, outputChar):
240        console->out((char)(val & 0xff));
241        break;
242
243      default:
244        int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
245                     sizeof(alphaAccess->cpuStack[0]);
246        warn("%d: Trying to launch CPU number %d!", curTick, cpunum);
247        assert(val > 0 && "Must not access primary cpu");
248        if (cpunum >= 0 && cpunum < 64)
249            alphaAccess->cpuStack[cpunum] = val;
250        else
251            panic("Unknown 64bit access, %#x\n", daddr);
252    }
253
254    pkt.result = Success;
255
256    return pioDelay;
257}
258
259void
260AlphaConsole::Access::serialize(ostream &os)
261{
262    SERIALIZE_SCALAR(last_offset);
263    SERIALIZE_SCALAR(version);
264    SERIALIZE_SCALAR(numCPUs);
265    SERIALIZE_SCALAR(mem_size);
266    SERIALIZE_SCALAR(cpuClock);
267    SERIALIZE_SCALAR(intrClockFrequency);
268    SERIALIZE_SCALAR(kernStart);
269    SERIALIZE_SCALAR(kernEnd);
270    SERIALIZE_SCALAR(entryPoint);
271    SERIALIZE_SCALAR(diskUnit);
272    SERIALIZE_SCALAR(diskCount);
273    SERIALIZE_SCALAR(diskPAddr);
274    SERIALIZE_SCALAR(diskBlock);
275    SERIALIZE_SCALAR(diskOperation);
276    SERIALIZE_SCALAR(outputChar);
277    SERIALIZE_SCALAR(inputChar);
278    SERIALIZE_ARRAY(cpuStack,64);
279}
280
281void
282AlphaConsole::Access::unserialize(Checkpoint *cp, const std::string &section)
283{
284    UNSERIALIZE_SCALAR(last_offset);
285    UNSERIALIZE_SCALAR(version);
286    UNSERIALIZE_SCALAR(numCPUs);
287    UNSERIALIZE_SCALAR(mem_size);
288    UNSERIALIZE_SCALAR(cpuClock);
289    UNSERIALIZE_SCALAR(intrClockFrequency);
290    UNSERIALIZE_SCALAR(kernStart);
291    UNSERIALIZE_SCALAR(kernEnd);
292    UNSERIALIZE_SCALAR(entryPoint);
293    UNSERIALIZE_SCALAR(diskUnit);
294    UNSERIALIZE_SCALAR(diskCount);
295    UNSERIALIZE_SCALAR(diskPAddr);
296    UNSERIALIZE_SCALAR(diskBlock);
297    UNSERIALIZE_SCALAR(diskOperation);
298    UNSERIALIZE_SCALAR(outputChar);
299    UNSERIALIZE_SCALAR(inputChar);
300    UNSERIALIZE_ARRAY(cpuStack, 64);
301}
302
303void
304AlphaConsole::serialize(ostream &os)
305{
306    alphaAccess->serialize(os);
307}
308
309void
310AlphaConsole::unserialize(Checkpoint *cp, const std::string &section)
311{
312    alphaAccess->unserialize(cp, section);
313}
314
315BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
316
317    SimObjectParam<SimConsole *> sim_console;
318    SimObjectParam<SimpleDisk *> disk;
319    Param<Addr> pio_addr;
320    SimObjectParam<AlphaSystem *> system;
321    SimObjectParam<BaseCPU *> cpu;
322    SimObjectParam<Platform *> platform;
323    Param<Tick> pio_latency;
324
325END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
326
327BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
328
329    INIT_PARAM(sim_console, "The Simulator Console"),
330    INIT_PARAM(disk, "Simple Disk"),
331    INIT_PARAM(pio_addr, "Device Address"),
332    INIT_PARAM(system, "system object"),
333    INIT_PARAM(cpu, "Processor"),
334    INIT_PARAM(platform, "platform"),
335    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000)
336
337END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
338
339CREATE_SIM_OBJECT(AlphaConsole)
340{
341    AlphaConsole::Params *p = new AlphaConsole::Params;
342    p->name = getInstanceName();
343    p->platform = platform;
344    p->pio_addr = pio_addr;
345    p->pio_delay = pio_latency;
346    p->cons = sim_console;
347    p->disk = disk;
348    p->alpha_sys = system;
349    p->system = system;
350    p->cpu = cpu;
351    return new AlphaConsole(p);
352}
353
354REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)
355