backdoor.cc revision 2522 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file
30 * Alpha Console Definition
31 */
32
33#include <cstddef>
34#include <cstdio>
35#include <string>
36
37#include "arch/alpha/system.hh"
38#include "base/inifile.hh"
39#include "base/str.hh"
40#include "base/trace.hh"
41#include "cpu/base.hh"
42#include "cpu/exec_context.hh"
43#include "dev/alpha_console.hh"
44#include "dev/platform.hh"
45#include "dev/simconsole.hh"
46#include "dev/simple_disk.hh"
47#include "mem/physical.hh"
48#include "sim/builder.hh"
49#include "sim/sim_object.hh"
50
51using namespace std;
52using namespace AlphaISA;
53
54AlphaConsole::AlphaConsole(Params *p)
55    : BasicPioDevice(p), disk(p->disk),
56      console(params()->cons), system(params()->alpha_sys), cpu(params()->cpu)
57{
58
59    pioSize = sizeof(struct AlphaAccess);
60
61    alphaAccess = new Access();
62    alphaAccess->last_offset = pioSize - 1;
63
64    alphaAccess->version = ALPHA_ACCESS_VERSION;
65    alphaAccess->diskUnit = 1;
66
67    alphaAccess->diskCount = 0;
68    alphaAccess->diskPAddr = 0;
69    alphaAccess->diskBlock = 0;
70    alphaAccess->diskOperation = 0;
71    alphaAccess->outputChar = 0;
72    alphaAccess->inputChar = 0;
73    bzero(alphaAccess->cpuStack, sizeof(alphaAccess->cpuStack));
74
75    system->setAlphaAccess(pioAddr);
76}
77
78void
79AlphaConsole::startup()
80{
81    alphaAccess->numCPUs = system->getNumCPUs();
82    alphaAccess->kernStart = system->getKernelStart();
83    alphaAccess->kernEnd = system->getKernelEnd();
84    alphaAccess->entryPoint = system->getKernelEntry();
85    alphaAccess->mem_size = system->physmem->size();
86    alphaAccess->cpuClock = cpu->frequency() / 1000000; // In MHz
87    alphaAccess->intrClockFrequency = params()->platform->intrFrequency();
88}
89
90void
91AlphaConsole::addressRanges(AddrRangeList &range_list)
92{
93    assert(pioSize != 0);
94    range_list.clear();
95    range_list.push_back(RangeSize(pioAddr, sizeof(struct AlphaAccess)));
96}
97
98
99Tick
100AlphaConsole::read(Packet &pkt)
101{
102
103    /** XXX Do we want to push the addr munging to a bus brige or something? So
104     * the device has it's physical address and then the bridge adds on whatever
105     * machine dependent address swizzle is required?
106     */
107
108    assert(pkt.result == Unknown);
109    assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
110
111    pkt.time = curTick + pioDelay;
112    Addr daddr = pkt.addr - pioAddr;
113
114    uint32_t *data32;
115    uint64_t *data64;
116
117    switch (pkt.size)
118    {
119        case sizeof(uint32_t):
120            if (!pkt.data) {
121                data32 = new uint32_t;
122                pkt.data = (uint8_t*)data32;
123            }
124            else
125                data32 = (uint32_t*)pkt.data;
126
127            switch (daddr)
128            {
129                case offsetof(AlphaAccess, last_offset):
130                    *data32 = alphaAccess->last_offset;
131                    break;
132                case offsetof(AlphaAccess, version):
133                    *data32 = alphaAccess->version;
134                    break;
135                case offsetof(AlphaAccess, numCPUs):
136                    *data32 = alphaAccess->numCPUs;
137                    break;
138                case offsetof(AlphaAccess, intrClockFrequency):
139                    *data32 = alphaAccess->intrClockFrequency;
140                    break;
141                default:
142                    /* Old console code read in everyting as a 32bit int
143                     * we now break that for better error checking.
144                     */
145                    pkt.result = BadAddress;
146            }
147            DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, *data32);
148            break;
149        case sizeof(uint64_t):
150            if (!pkt.data) {
151                data64 = new uint64_t;
152                pkt.data = (uint8_t*)data64;
153            }
154            else
155                data64 = (uint64_t*)pkt.data;
156            switch (daddr)
157            {
158                case offsetof(AlphaAccess, inputChar):
159                    *data64 = console->console_in();
160                    break;
161                case offsetof(AlphaAccess, cpuClock):
162                    *data64 = alphaAccess->cpuClock;
163                    break;
164                case offsetof(AlphaAccess, mem_size):
165                    *data64 = alphaAccess->mem_size;
166                    break;
167                case offsetof(AlphaAccess, kernStart):
168                    *data64 = alphaAccess->kernStart;
169                    break;
170                case offsetof(AlphaAccess, kernEnd):
171                    *data64 = alphaAccess->kernEnd;
172                    break;
173                case offsetof(AlphaAccess, entryPoint):
174                    *data64 = alphaAccess->entryPoint;
175                    break;
176                case offsetof(AlphaAccess, diskUnit):
177                    *data64 = alphaAccess->diskUnit;
178                    break;
179                case offsetof(AlphaAccess, diskCount):
180                    *data64 = alphaAccess->diskCount;
181                    break;
182                case offsetof(AlphaAccess, diskPAddr):
183                    *data64 = alphaAccess->diskPAddr;
184                    break;
185                case offsetof(AlphaAccess, diskBlock):
186                    *data64 = alphaAccess->diskBlock;
187                    break;
188                case offsetof(AlphaAccess, diskOperation):
189                    *data64 = alphaAccess->diskOperation;
190                    break;
191                case offsetof(AlphaAccess, outputChar):
192                    *data64 = alphaAccess->outputChar;
193                    break;
194                default:
195                    int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
196                                 sizeof(alphaAccess->cpuStack[0]);
197
198                    if (cpunum >= 0 && cpunum < 64)
199                        *data64 = alphaAccess->cpuStack[cpunum];
200                    else
201                        panic("Unknown 64bit access, %#x\n", daddr);
202            }
203            DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, *data64);
204            break;
205        default:
206            pkt.result = BadAddress;
207    }
208    if (pkt.result == Unknown) pkt.result = Success;
209    return pioDelay;
210}
211
212Tick
213AlphaConsole::write(Packet &pkt)
214{
215    pkt.time = curTick + pioDelay;
216
217    assert(pkt.result == Unknown);
218    assert(pkt.addr >= pioAddr && pkt.addr < pioAddr + pioSize);
219    Addr daddr = pkt.addr - pioAddr;
220
221    uint64_t val = *(uint64_t *)pkt.data;
222    assert(pkt.size == sizeof(uint64_t));
223
224    switch (daddr) {
225      case offsetof(AlphaAccess, diskUnit):
226        alphaAccess->diskUnit = val;
227        break;
228
229      case offsetof(AlphaAccess, diskCount):
230        alphaAccess->diskCount = val;
231        break;
232
233      case offsetof(AlphaAccess, diskPAddr):
234        alphaAccess->diskPAddr = val;
235        break;
236
237      case offsetof(AlphaAccess, diskBlock):
238        alphaAccess->diskBlock = val;
239        break;
240
241      case offsetof(AlphaAccess, diskOperation):
242        if (val == 0x13)
243            disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock,
244                       alphaAccess->diskCount);
245        else
246            panic("Invalid disk operation!");
247
248        break;
249
250      case offsetof(AlphaAccess, outputChar):
251        console->out((char)(val & 0xff));
252        break;
253
254      default:
255        int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
256                     sizeof(alphaAccess->cpuStack[0]);
257        warn("%d: Trying to launch CPU number %d!", curTick, cpunum);
258        assert(val > 0 && "Must not access primary cpu");
259        if (cpunum >= 0 && cpunum < 64)
260            alphaAccess->cpuStack[cpunum] = val;
261        else
262            panic("Unknown 64bit access, %#x\n", daddr);
263    }
264
265    pkt.result = Success;
266
267    return pioDelay;
268}
269
270void
271AlphaConsole::Access::serialize(ostream &os)
272{
273    SERIALIZE_SCALAR(last_offset);
274    SERIALIZE_SCALAR(version);
275    SERIALIZE_SCALAR(numCPUs);
276    SERIALIZE_SCALAR(mem_size);
277    SERIALIZE_SCALAR(cpuClock);
278    SERIALIZE_SCALAR(intrClockFrequency);
279    SERIALIZE_SCALAR(kernStart);
280    SERIALIZE_SCALAR(kernEnd);
281    SERIALIZE_SCALAR(entryPoint);
282    SERIALIZE_SCALAR(diskUnit);
283    SERIALIZE_SCALAR(diskCount);
284    SERIALIZE_SCALAR(diskPAddr);
285    SERIALIZE_SCALAR(diskBlock);
286    SERIALIZE_SCALAR(diskOperation);
287    SERIALIZE_SCALAR(outputChar);
288    SERIALIZE_SCALAR(inputChar);
289    SERIALIZE_ARRAY(cpuStack,64);
290}
291
292void
293AlphaConsole::Access::unserialize(Checkpoint *cp, const std::string &section)
294{
295    UNSERIALIZE_SCALAR(last_offset);
296    UNSERIALIZE_SCALAR(version);
297    UNSERIALIZE_SCALAR(numCPUs);
298    UNSERIALIZE_SCALAR(mem_size);
299    UNSERIALIZE_SCALAR(cpuClock);
300    UNSERIALIZE_SCALAR(intrClockFrequency);
301    UNSERIALIZE_SCALAR(kernStart);
302    UNSERIALIZE_SCALAR(kernEnd);
303    UNSERIALIZE_SCALAR(entryPoint);
304    UNSERIALIZE_SCALAR(diskUnit);
305    UNSERIALIZE_SCALAR(diskCount);
306    UNSERIALIZE_SCALAR(diskPAddr);
307    UNSERIALIZE_SCALAR(diskBlock);
308    UNSERIALIZE_SCALAR(diskOperation);
309    UNSERIALIZE_SCALAR(outputChar);
310    UNSERIALIZE_SCALAR(inputChar);
311    UNSERIALIZE_ARRAY(cpuStack, 64);
312}
313
314void
315AlphaConsole::serialize(ostream &os)
316{
317    alphaAccess->serialize(os);
318}
319
320void
321AlphaConsole::unserialize(Checkpoint *cp, const std::string &section)
322{
323    alphaAccess->unserialize(cp, section);
324}
325
326BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
327
328    SimObjectParam<SimConsole *> sim_console;
329    SimObjectParam<SimpleDisk *> disk;
330    Param<Addr> addr;
331    SimObjectParam<AlphaSystem *> system;
332    SimObjectParam<BaseCPU *> cpu;
333    SimObjectParam<Platform *> platform;
334    Param<Tick> pio_latency;
335
336END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
337
338BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
339
340    INIT_PARAM(sim_console, "The Simulator Console"),
341    INIT_PARAM(disk, "Simple Disk"),
342    INIT_PARAM(addr, "Device Address"),
343    INIT_PARAM(system, "system object"),
344    INIT_PARAM(cpu, "Processor"),
345    INIT_PARAM(platform, "platform"),
346    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000)
347
348END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
349
350CREATE_SIM_OBJECT(AlphaConsole)
351{
352    AlphaConsole::Params *p = new AlphaConsole::Params;
353    p->name = getInstanceName();
354    p->platform = platform;
355    p->pio_addr = addr;
356    p->pio_delay = pio_latency;
357    p->cons = sim_console;
358    p->disk = disk;
359    p->alpha_sys = system;
360    p->system = system;
361    p->cpu = cpu;
362    return new AlphaConsole(p);
363}
364
365REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)
366