backdoor.cc revision 2114 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file
30 * Alpha Console Definition
31 */
32
33#include <cstddef>
34#include <cstdio>
35#include <string>
36
37#include "base/inifile.hh"
38#include "base/str.hh"
39#include "base/trace.hh"
40#include "cpu/base.hh"
41#include "cpu/exec_context.hh"
42#include "dev/alpha_console.hh"
43#include "dev/simconsole.hh"
44#include "dev/simple_disk.hh"
45#include "dev/tsunami_io.hh"
46#include "mem/bus/bus.hh"
47#include "mem/bus/pio_interface.hh"
48#include "mem/bus/pio_interface_impl.hh"
49#include "mem/functional/memory_control.hh"
50#include "mem/functional/physical.hh"
51#include "sim/builder.hh"
52#include "sim/sim_object.hh"
53#include "sim/system.hh"
54
55using namespace std;
56
57AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
58                           System *s, BaseCPU *c, Platform *p,
59                           MemoryController *mmu, Addr a,
60                           HierParams *hier, Bus *pio_bus)
61    : PioDevice(name, p), disk(d), console(cons), system(s), cpu(c), addr(a)
62{
63    mmu->add_child(this, RangeSize(addr, size));
64
65    if (pio_bus) {
66        pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this,
67                                       &AlphaConsole::cacheAccess);
68        pioInterface->addAddrRange(RangeSize(addr, size));
69    }
70
71    alphaAccess = new Access;
72    alphaAccess->last_offset = size - 1;
73
74    alphaAccess->version = ALPHA_ACCESS_VERSION;
75    alphaAccess->diskUnit = 1;
76
77    alphaAccess->diskCount = 0;
78    alphaAccess->diskPAddr = 0;
79    alphaAccess->diskBlock = 0;
80    alphaAccess->diskOperation = 0;
81    alphaAccess->outputChar = 0;
82    alphaAccess->inputChar = 0;
83    bzero(alphaAccess->cpuStack, sizeof(alphaAccess->cpuStack));
84
85    system->setAlphaAccess(addr);
86}
87
88void
89AlphaConsole::startup()
90{
91    alphaAccess->numCPUs = system->getNumCPUs();
92    alphaAccess->kernStart = system->getKernelStart();
93    alphaAccess->kernEnd = system->getKernelEnd();
94    alphaAccess->entryPoint = system->getKernelEntry();
95    alphaAccess->mem_size = system->physmem->size();
96    alphaAccess->cpuClock = cpu->frequency() / 1000000; // In MHz
97    alphaAccess->intrClockFrequency = platform->intrFrequency();
98}
99
100Fault
101AlphaConsole::read(MemReqPtr &req, uint8_t *data)
102{
103    memset(data, 0, req->size);
104
105    Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
106
107    switch (req->size)
108    {
109        case sizeof(uint32_t):
110            DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr,
111                    *(uint32_t*)data);
112            switch (daddr)
113            {
114                case offsetof(AlphaAccess, last_offset):
115                    *(uint32_t*)data = alphaAccess->last_offset;
116                    break;
117                case offsetof(AlphaAccess, version):
118                    *(uint32_t*)data = alphaAccess->version;
119                    break;
120                case offsetof(AlphaAccess, numCPUs):
121                    *(uint32_t*)data = alphaAccess->numCPUs;
122                    break;
123                case offsetof(AlphaAccess, intrClockFrequency):
124                    *(uint32_t*)data = alphaAccess->intrClockFrequency;
125                    break;
126                default:
127                    // Old console code read in everyting as a 32bit int
128                    *(uint32_t*)data = *(uint32_t*)(consoleData + daddr);
129
130            }
131            break;
132        case sizeof(uint64_t):
133            DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr,
134                    *(uint64_t*)data);
135            switch (daddr)
136            {
137                case offsetof(AlphaAccess, inputChar):
138                    *(uint64_t*)data = console->console_in();
139                    break;
140                case offsetof(AlphaAccess, cpuClock):
141                    *(uint64_t*)data = alphaAccess->cpuClock;
142                    break;
143                case offsetof(AlphaAccess, mem_size):
144                    *(uint64_t*)data = alphaAccess->mem_size;
145                    break;
146                case offsetof(AlphaAccess, kernStart):
147                    *(uint64_t*)data = alphaAccess->kernStart;
148                    break;
149                case offsetof(AlphaAccess, kernEnd):
150                    *(uint64_t*)data = alphaAccess->kernEnd;
151                    break;
152                case offsetof(AlphaAccess, entryPoint):
153                    *(uint64_t*)data = alphaAccess->entryPoint;
154                    break;
155                case offsetof(AlphaAccess, diskUnit):
156                    *(uint64_t*)data = alphaAccess->diskUnit;
157                    break;
158                case offsetof(AlphaAccess, diskCount):
159                    *(uint64_t*)data = alphaAccess->diskCount;
160                    break;
161                case offsetof(AlphaAccess, diskPAddr):
162                    *(uint64_t*)data = alphaAccess->diskPAddr;
163                    break;
164                case offsetof(AlphaAccess, diskBlock):
165                    *(uint64_t*)data = alphaAccess->diskBlock;
166                    break;
167                case offsetof(AlphaAccess, diskOperation):
168                    *(uint64_t*)data = alphaAccess->diskOperation;
169                    break;
170                case offsetof(AlphaAccess, outputChar):
171                    *(uint64_t*)data = alphaAccess->outputChar;
172                    break;
173                default:
174                    int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
175                                 sizeof(alphaAccess->cpuStack[0]);
176
177                    if (cpunum >= 0 && cpunum < 64)
178                        *(uint64_t*)data = alphaAccess->cpuStack[cpunum];
179                    else
180                        panic("Unknown 64bit access, %#x\n", daddr);
181            }
182            break;
183        default:
184            return Machine_Check_Fault;
185    }
186
187    return No_Fault;
188}
189
190Fault
191AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
192{
193    uint64_t val;
194
195    switch (req->size) {
196      case sizeof(uint32_t):
197        val = *(uint32_t *)data;
198        break;
199
200      case sizeof(uint64_t):
201        val = *(uint64_t *)data;
202        break;
203      default:
204        return Machine_Check_Fault;
205    }
206
207    Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
208    ExecContext *other_xc;
209
210    switch (daddr) {
211      case offsetof(AlphaAccess, diskUnit):
212        alphaAccess->diskUnit = val;
213        break;
214
215      case offsetof(AlphaAccess, diskCount):
216        alphaAccess->diskCount = val;
217        break;
218
219      case offsetof(AlphaAccess, diskPAddr):
220        alphaAccess->diskPAddr = val;
221        break;
222
223      case offsetof(AlphaAccess, diskBlock):
224        alphaAccess->diskBlock = val;
225        break;
226
227      case offsetof(AlphaAccess, diskOperation):
228        if (val == 0x13)
229            disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock,
230                       alphaAccess->diskCount);
231        else
232            panic("Invalid disk operation!");
233
234        break;
235
236      case offsetof(AlphaAccess, outputChar):
237        console->out((char)(val & 0xff));
238        break;
239
240        other_xc->activate(); //Start the cpu
241        break;
242
243      default:
244        int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
245                     sizeof(alphaAccess->cpuStack[0]);
246        warn("%d: Trying to launch CPU number %d!", curTick, cpunum);
247        assert(val > 0 && "Must not access primary cpu");
248        if (cpunum >= 0 && cpunum < 64)
249            alphaAccess->cpuStack[cpunum] = val;
250        else
251            panic("Unknown 64bit access, %#x\n", daddr);
252    }
253
254    return No_Fault;
255}
256
257Tick
258AlphaConsole::cacheAccess(MemReqPtr &req)
259{
260    return curTick + 1000;
261}
262
263void
264AlphaConsole::Access::serialize(ostream &os)
265{
266    SERIALIZE_SCALAR(last_offset);
267    SERIALIZE_SCALAR(version);
268    SERIALIZE_SCALAR(numCPUs);
269    SERIALIZE_SCALAR(mem_size);
270    SERIALIZE_SCALAR(cpuClock);
271    SERIALIZE_SCALAR(intrClockFrequency);
272    SERIALIZE_SCALAR(kernStart);
273    SERIALIZE_SCALAR(kernEnd);
274    SERIALIZE_SCALAR(entryPoint);
275    SERIALIZE_SCALAR(diskUnit);
276    SERIALIZE_SCALAR(diskCount);
277    SERIALIZE_SCALAR(diskPAddr);
278    SERIALIZE_SCALAR(diskBlock);
279    SERIALIZE_SCALAR(diskOperation);
280    SERIALIZE_SCALAR(outputChar);
281    SERIALIZE_SCALAR(inputChar);
282    SERIALIZE_ARRAY(cpuStack,64);
283}
284
285void
286AlphaConsole::Access::unserialize(Checkpoint *cp, const std::string &section)
287{
288    UNSERIALIZE_SCALAR(last_offset);
289    UNSERIALIZE_SCALAR(version);
290    UNSERIALIZE_SCALAR(numCPUs);
291    UNSERIALIZE_SCALAR(mem_size);
292    UNSERIALIZE_SCALAR(cpuClock);
293    UNSERIALIZE_SCALAR(intrClockFrequency);
294    UNSERIALIZE_SCALAR(kernStart);
295    UNSERIALIZE_SCALAR(kernEnd);
296    UNSERIALIZE_SCALAR(entryPoint);
297    UNSERIALIZE_SCALAR(diskUnit);
298    UNSERIALIZE_SCALAR(diskCount);
299    UNSERIALIZE_SCALAR(diskPAddr);
300    UNSERIALIZE_SCALAR(diskBlock);
301    UNSERIALIZE_SCALAR(diskOperation);
302    UNSERIALIZE_SCALAR(outputChar);
303    UNSERIALIZE_SCALAR(inputChar);
304    UNSERIALIZE_ARRAY(cpuStack, 64);
305}
306
307void
308AlphaConsole::serialize(ostream &os)
309{
310    alphaAccess->serialize(os);
311}
312
313void
314AlphaConsole::unserialize(Checkpoint *cp, const std::string &section)
315{
316    alphaAccess->unserialize(cp, section);
317}
318
319BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
320
321    SimObjectParam<SimConsole *> sim_console;
322    SimObjectParam<SimpleDisk *> disk;
323    SimObjectParam<MemoryController *> mmu;
324    Param<Addr> addr;
325    SimObjectParam<System *> system;
326    SimObjectParam<BaseCPU *> cpu;
327    SimObjectParam<Platform *> platform;
328    SimObjectParam<Bus*> pio_bus;
329    Param<Tick> pio_latency;
330    SimObjectParam<HierParams *> hier;
331
332END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
333
334BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
335
336    INIT_PARAM(sim_console, "The Simulator Console"),
337    INIT_PARAM(disk, "Simple Disk"),
338    INIT_PARAM(mmu, "Memory Controller"),
339    INIT_PARAM(addr, "Device Address"),
340    INIT_PARAM(system, "system object"),
341    INIT_PARAM(cpu, "Processor"),
342    INIT_PARAM(platform, "platform"),
343    INIT_PARAM(pio_bus, "The IO Bus to attach to"),
344    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
345    INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
346
347END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
348
349CREATE_SIM_OBJECT(AlphaConsole)
350{
351    return new AlphaConsole(getInstanceName(), sim_console, disk,
352                            system, cpu, platform, mmu, addr, hier, pio_bus);
353}
354
355REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)
356