backdoor.cc revision 2107
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A */ 282665SN/A 292665SN/A/** @file 302665SN/A * Alpha Console Definition 312665SN/A */ 322SN/A 332SN/A#include <cstddef> 341722SN/A#include <cstdio> 355480Snate@binkert.org#include <string> 362SN/A 372SN/A#include "base/inifile.hh" 38146SN/A#include "base/str.hh" 392SN/A#include "base/trace.hh" 402SN/A#include "cpu/base.hh" 412158SN/A#include "cpu/exec_context.hh" 42146SN/A#include "dev/alpha_console.hh" 431805SN/A#include "dev/simconsole.hh" 44146SN/A#include "dev/simple_disk.hh" 451717SN/A#include "dev/tsunami_io.hh" 462680SN/A#include "mem/bus/bus.hh" 475480Snate@binkert.org#include "mem/bus/pio_interface.hh" 482521SN/A#include "mem/bus/pio_interface_impl.hh" 4956SN/A#include "mem/functional/memory_control.hh" 505478SN/A#include "mem/functional/physical.hh" 513348SN/A#include "sim/builder.hh" 523348SN/A#include "sim/sim_object.hh" 532521SN/A#include "sim/system.hh" 545480Snate@binkert.org 551805SN/Ausing namespace std; 562SN/Ausing namespace AlphaISA; 572SN/A 582107SN/AAlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d, 592SN/A System *s, BaseCPU *c, Platform *p, 605480Snate@binkert.org MemoryController *mmu, Addr a, 615478SN/A HierParams *hier, Bus *pio_bus) 624762SN/A : PioDevice(name, p), disk(d), console(cons), system(s), cpu(c), addr(a) 632SN/A{ 64545SN/A mmu->add_child(this, RangeSize(addr, size)); 652521SN/A 662521SN/A if (pio_bus) { 672521SN/A pioInterface = newPioInterface(name + ".pio", hier, pio_bus, this, 682521SN/A &AlphaConsole::cacheAccess); 692SN/A pioInterface->addAddrRange(RangeSize(addr, size)); 702SN/A } 712SN/A 72926SN/A alphaAccess = new Access; 73926SN/A alphaAccess->last_offset = size - 1; 74926SN/A 75926SN/A alphaAccess->version = ALPHA_ACCESS_VERSION; 76926SN/A alphaAccess->diskUnit = 1; 77926SN/A 78926SN/A alphaAccess->diskCount = 0; 794395SN/A alphaAccess->diskPAddr = 0; 801805SN/A alphaAccess->diskBlock = 0; 812SN/A alphaAccess->diskOperation = 0; 822SN/A alphaAccess->outputChar = 0; 831634SN/A alphaAccess->inputChar = 0; 845480Snate@binkert.org alphaAccess->bootStrapImpure = 0; 851634SN/A alphaAccess->bootStrapCPU = 0; 862549SN/A alphaAccess->align2 = 0; 871806SN/A 881634SN/A system->setAlphaAccess(addr); 891634SN/A} 901634SN/A 911634SN/Avoid 921634SN/AAlphaConsole::startup() 932521SN/A{ 941634SN/A alphaAccess->numCPUs = system->getNumCPUs(); 951634SN/A alphaAccess->kernStart = system->getKernelStart(); 962512SN/A alphaAccess->kernEnd = system->getKernelEnd(); 975480Snate@binkert.org alphaAccess->entryPoint = system->getKernelEntry(); 982SN/A alphaAccess->mem_size = system->physmem->size(); 992SN/A alphaAccess->cpuClock = cpu->frequency() / 1000000; // In MHz 1002512SN/A alphaAccess->intrClockFrequency = platform->intrFrequency(); 1012512SN/A} 1022512SN/A 1032512SN/AFault * 104540SN/AAlphaConsole::read(MemReqPtr &req, uint8_t *data) 1052641SN/A{ 1062522SN/A memset(data, 0, req->size); 1072641SN/A 1082512SN/A Addr daddr = req->paddr - (addr & EV5::PAddrImplMask); 1092630SN/A 1104986SN/A switch (req->size) 1112521SN/A { 1122641SN/A case sizeof(uint32_t): 113873SN/A DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, 114873SN/A *(uint32_t*)data); 115873SN/A switch (daddr) 116873SN/A { 117873SN/A case offsetof(AlphaAccess, last_offset): 1182630SN/A *(uint32_t*)data = alphaAccess->last_offset; 119873SN/A break; 120873SN/A case offsetof(AlphaAccess, version): 1212630SN/A *(uint32_t*)data = alphaAccess->version; 122873SN/A break; 123873SN/A case offsetof(AlphaAccess, numCPUs): 1242630SN/A *(uint32_t*)data = alphaAccess->numCPUs; 125873SN/A break; 126873SN/A case offsetof(AlphaAccess, bootStrapCPU): 1272630SN/A *(uint32_t*)data = alphaAccess->bootStrapCPU; 128873SN/A break; 129873SN/A case offsetof(AlphaAccess, intrClockFrequency): 1302512SN/A *(uint32_t*)data = alphaAccess->intrClockFrequency; 1312512SN/A break; 1322512SN/A default: 1334870SN/A // Old console code read in everyting as a 32bit int 134873SN/A *(uint32_t*)data = *(uint32_t*)(consoleData + daddr); 1355480Snate@binkert.org 1362630SN/A } 137873SN/A break; 138873SN/A case sizeof(uint64_t): 139873SN/A DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n", daddr, 140873SN/A *(uint64_t*)data); 141873SN/A switch (daddr) 1425478SN/A { 143873SN/A case offsetof(AlphaAccess, inputChar): 144873SN/A *(uint64_t*)data = console->console_in(); 1452630SN/A break; 146873SN/A case offsetof(AlphaAccess, cpuClock): 147873SN/A *(uint64_t*)data = alphaAccess->cpuClock; 1482630SN/A break; 149873SN/A case offsetof(AlphaAccess, mem_size): 150873SN/A *(uint64_t*)data = alphaAccess->mem_size; 1512630SN/A break; 152873SN/A case offsetof(AlphaAccess, kernStart): 153873SN/A *(uint64_t*)data = alphaAccess->kernStart; 1542630SN/A break; 155873SN/A case offsetof(AlphaAccess, kernEnd): 156873SN/A *(uint64_t*)data = alphaAccess->kernEnd; 1572630SN/A break; 158873SN/A case offsetof(AlphaAccess, entryPoint): 159873SN/A *(uint64_t*)data = alphaAccess->entryPoint; 1602630SN/A break; 161873SN/A case offsetof(AlphaAccess, diskUnit): 162873SN/A *(uint64_t*)data = alphaAccess->diskUnit; 1632630SN/A break; 164873SN/A case offsetof(AlphaAccess, diskCount): 165873SN/A *(uint64_t*)data = alphaAccess->diskCount; 1662630SN/A break; 167873SN/A case offsetof(AlphaAccess, diskPAddr): 168873SN/A *(uint64_t*)data = alphaAccess->diskPAddr; 1692630SN/A break; 170873SN/A case offsetof(AlphaAccess, diskBlock): 171873SN/A *(uint64_t*)data = alphaAccess->diskBlock; 1722630SN/A break; 173873SN/A case offsetof(AlphaAccess, diskOperation): 174873SN/A *(uint64_t*)data = alphaAccess->diskOperation; 1752630SN/A break; 176873SN/A case offsetof(AlphaAccess, outputChar): 177873SN/A *(uint64_t*)data = alphaAccess->outputChar; 1782114SN/A break; 1792114SN/A case offsetof(AlphaAccess, bootStrapImpure): 1802114SN/A *(uint64_t*)data = alphaAccess->bootStrapImpure; 1812114SN/A break; 1822630SN/A default: 1832114SN/A panic("Unknown 64bit access, %#x\n", daddr); 1842114SN/A } 185873SN/A break; 1865480Snate@binkert.org default: 1872630SN/A return MachineCheckFault; 188873SN/A } 189873SN/A 1904870SN/A return NoFault; 1912SN/A} 1922512SN/A 1932SN/AFault * 1942SN/AAlphaConsole::write(MemReqPtr &req, const uint8_t *data) 1952512SN/A{ 1965480Snate@binkert.org uint64_t val; 1972SN/A 1982641SN/A switch (req->size) { 1992641SN/A case sizeof(uint32_t): 200430SN/A val = *(uint32_t *)data; 2012630SN/A break; 2022641SN/A 2032SN/A case sizeof(uint64_t): 204430SN/A val = *(uint64_t *)data; 205430SN/A break; 2062SN/A default: 207430SN/A return MachineCheckFault; 2082SN/A } 209430SN/A 2102SN/A Addr daddr = req->paddr - (addr & EV5::PAddrImplMask); 211430SN/A ExecContext *other_xc; 2122SN/A 213430SN/A switch (daddr) { 2142SN/A case offsetof(AlphaAccess, diskUnit): 215430SN/A alphaAccess->diskUnit = val; 2162SN/A break; 217430SN/A 2182SN/A case offsetof(AlphaAccess, diskCount): 219430SN/A alphaAccess->diskCount = val; 2202SN/A break; 221430SN/A 2222SN/A case offsetof(AlphaAccess, diskPAddr): 2232SN/A alphaAccess->diskPAddr = val; 2242SN/A break; 2252SN/A 2262SN/A case offsetof(AlphaAccess, diskBlock): 2272SN/A alphaAccess->diskBlock = val; 228430SN/A break; 2292SN/A 230430SN/A case offsetof(AlphaAccess, diskOperation): 2315478SN/A if (val == 0x13) 232430SN/A disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock, 2332SN/A alphaAccess->diskCount); 234430SN/A else 2352114SN/A panic("Invalid disk operation!"); 2362114SN/A 2372114SN/A break; 2382114SN/A 2392114SN/A case offsetof(AlphaAccess, outputChar): 2402114SN/A console->out((char)(val & 0xff)); 2412114SN/A break; 2422114SN/A 2432SN/A case offsetof(AlphaAccess, bootStrapImpure): 2442SN/A alphaAccess->bootStrapImpure = val; 2454870SN/A break; 2462SN/A 2472512SN/A case offsetof(AlphaAccess, bootStrapCPU): 248545SN/A warn("%d: Trying to launch another CPU!", curTick); 249545SN/A assert(val > 0 && "Must not access primary cpu"); 2502SN/A 2515480Snate@binkert.org other_xc = req->xc->system->execContexts[val]; 2522SN/A other_xc->regs.intRegFile[16] = val; 253222SN/A other_xc->regs.ipr[TheISA::IPR_PALtemp16] = val; 254222SN/A other_xc->regs.intRegFile[0] = val; 255222SN/A other_xc->regs.intRegFile[30] = alphaAccess->bootStrapImpure; 256222SN/A other_xc->activate(); //Start the cpu 257222SN/A break; 258222SN/A 259222SN/A default: 260222SN/A return MachineCheckFault; 261222SN/A } 262222SN/A 263222SN/A return NoFault; 264222SN/A} 265222SN/A 266222SN/ATick 267222SN/AAlphaConsole::cacheAccess(MemReqPtr &req) 268430SN/A{ 2692114SN/A return curTick + 1000; 2702SN/A} 2712SN/A 2722SN/Avoid 2735480Snate@binkert.orgAlphaConsole::Access::serialize(ostream &os) 2742SN/A{ 275222SN/A SERIALIZE_SCALAR(last_offset); 276222SN/A SERIALIZE_SCALAR(version); 277222SN/A SERIALIZE_SCALAR(numCPUs); 278222SN/A SERIALIZE_SCALAR(mem_size); 279222SN/A SERIALIZE_SCALAR(cpuClock); 280222SN/A SERIALIZE_SCALAR(intrClockFrequency); 281222SN/A SERIALIZE_SCALAR(kernStart); 282222SN/A SERIALIZE_SCALAR(kernEnd); 283222SN/A SERIALIZE_SCALAR(entryPoint); 284222SN/A SERIALIZE_SCALAR(diskUnit); 285222SN/A SERIALIZE_SCALAR(diskCount); 286222SN/A SERIALIZE_SCALAR(diskPAddr); 287222SN/A SERIALIZE_SCALAR(diskBlock); 288222SN/A SERIALIZE_SCALAR(diskOperation); 289222SN/A SERIALIZE_SCALAR(outputChar); 290430SN/A SERIALIZE_SCALAR(inputChar); 2912114SN/A SERIALIZE_SCALAR(bootStrapImpure); 292217SN/A SERIALIZE_SCALAR(bootStrapCPU); 2932SN/A} 294217SN/A 2955480Snate@binkert.orgvoid 296217SN/AAlphaConsole::Access::unserialize(Checkpoint *cp, const std::string §ion) 297217SN/A{ 298217SN/A UNSERIALIZE_SCALAR(last_offset); 299217SN/A UNSERIALIZE_SCALAR(version); 300217SN/A UNSERIALIZE_SCALAR(numCPUs); 3015480Snate@binkert.org UNSERIALIZE_SCALAR(mem_size); 302217SN/A UNSERIALIZE_SCALAR(cpuClock); 303237SN/A UNSERIALIZE_SCALAR(intrClockFrequency); 3042SN/A UNSERIALIZE_SCALAR(kernStart); 3052SN/A UNSERIALIZE_SCALAR(kernEnd); 3065480Snate@binkert.org UNSERIALIZE_SCALAR(entryPoint); 3075480Snate@binkert.org UNSERIALIZE_SCALAR(diskUnit); 3082SN/A UNSERIALIZE_SCALAR(diskCount); 3095480Snate@binkert.org UNSERIALIZE_SCALAR(diskPAddr); 3102SN/A UNSERIALIZE_SCALAR(diskBlock); 311 UNSERIALIZE_SCALAR(diskOperation); 312 UNSERIALIZE_SCALAR(outputChar); 313 UNSERIALIZE_SCALAR(inputChar); 314 UNSERIALIZE_SCALAR(bootStrapImpure); 315 UNSERIALIZE_SCALAR(bootStrapCPU); 316} 317 318void 319AlphaConsole::serialize(ostream &os) 320{ 321 alphaAccess->serialize(os); 322} 323 324void 325AlphaConsole::unserialize(Checkpoint *cp, const std::string §ion) 326{ 327 alphaAccess->unserialize(cp, section); 328} 329 330BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole) 331 332 SimObjectParam<SimConsole *> sim_console; 333 SimObjectParam<SimpleDisk *> disk; 334 SimObjectParam<MemoryController *> mmu; 335 Param<Addr> addr; 336 SimObjectParam<System *> system; 337 SimObjectParam<BaseCPU *> cpu; 338 SimObjectParam<Platform *> platform; 339 SimObjectParam<Bus*> pio_bus; 340 Param<Tick> pio_latency; 341 SimObjectParam<HierParams *> hier; 342 343END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole) 344 345BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole) 346 347 INIT_PARAM(sim_console, "The Simulator Console"), 348 INIT_PARAM(disk, "Simple Disk"), 349 INIT_PARAM(mmu, "Memory Controller"), 350 INIT_PARAM(addr, "Device Address"), 351 INIT_PARAM(system, "system object"), 352 INIT_PARAM(cpu, "Processor"), 353 INIT_PARAM(platform, "platform"), 354 INIT_PARAM(pio_bus, "The IO Bus to attach to"), 355 INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000), 356 INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams) 357 358END_INIT_SIM_OBJECT_PARAMS(AlphaConsole) 359 360CREATE_SIM_OBJECT(AlphaConsole) 361{ 362 return new AlphaConsole(getInstanceName(), sim_console, disk, 363 system, cpu, platform, mmu, addr, hier, pio_bus); 364} 365 366REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole) 367