backdoor.cc revision 12239
111723Sar4jc@virginia.edu/* 211963Sar4jc@virginia.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 311963Sar4jc@virginia.edu * All rights reserved. 411963Sar4jc@virginia.edu * 511963Sar4jc@virginia.edu * Redistribution and use in source and binary forms, with or without 611723Sar4jc@virginia.edu * modification, are permitted provided that the following conditions are 711723Sar4jc@virginia.edu * met: redistributions of source code must retain the above copyright 811723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer; 911723Sar4jc@virginia.edu * redistributions in binary form must reproduce the above copyright 1011723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer in the 1111723Sar4jc@virginia.edu * documentation and/or other materials provided with the distribution; 1211723Sar4jc@virginia.edu * neither the name of the copyright holders nor the names of its 1311723Sar4jc@virginia.edu * contributors may be used to endorse or promote products derived from 1411723Sar4jc@virginia.edu * this software without specific prior written permission. 1511723Sar4jc@virginia.edu * 1611723Sar4jc@virginia.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711723Sar4jc@virginia.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811723Sar4jc@virginia.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911723Sar4jc@virginia.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011723Sar4jc@virginia.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111723Sar4jc@virginia.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211723Sar4jc@virginia.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311723Sar4jc@virginia.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411723Sar4jc@virginia.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511723Sar4jc@virginia.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611723Sar4jc@virginia.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711723Sar4jc@virginia.edu * 2811723Sar4jc@virginia.edu * Authors: Nathan Binkert 2911723Sar4jc@virginia.edu * Ali Saidi 3011723Sar4jc@virginia.edu * Steve Reinhardt 3111723Sar4jc@virginia.edu * Erik Hallnor 3211963Sar4jc@virginia.edu */ 3311963Sar4jc@virginia.edu 3411723Sar4jc@virginia.edu/** @file 3511723Sar4jc@virginia.edu * Alpha Console Backdoor Definition 3611723Sar4jc@virginia.edu */ 3711723Sar4jc@virginia.edu 3811723Sar4jc@virginia.edu#include "dev/alpha/backdoor.hh" 3911963Sar4jc@virginia.edu 4011963Sar4jc@virginia.edu#include <cstddef> 4111963Sar4jc@virginia.edu#include <string> 4211723Sar4jc@virginia.edu 4311723Sar4jc@virginia.edu#include "arch/alpha/system.hh" 4411723Sar4jc@virginia.edu#include "base/inifile.hh" 4511723Sar4jc@virginia.edu#include "base/str.hh" 4611723Sar4jc@virginia.edu#include "base/trace.hh" 4711723Sar4jc@virginia.edu#include "cpu/base.hh" 4811723Sar4jc@virginia.edu#include "cpu/thread_context.hh" 4911723Sar4jc@virginia.edu#include "debug/AlphaBackdoor.hh" 5011723Sar4jc@virginia.edu#include "dev/alpha/tsunami.hh" 5111723Sar4jc@virginia.edu#include "dev/alpha/tsunami_cchip.hh" 5211963Sar4jc@virginia.edu#include "dev/alpha/tsunami_io.hh" 5311963Sar4jc@virginia.edu#include "dev/platform.hh" 5411963Sar4jc@virginia.edu#include "dev/storage/simple_disk.hh" 5511963Sar4jc@virginia.edu#include "dev/serial/terminal.hh" 5611963Sar4jc@virginia.edu#include "mem/packet.hh" 5711963Sar4jc@virginia.edu#include "mem/packet_access.hh" 5811963Sar4jc@virginia.edu#include "mem/physical.hh" 5911963Sar4jc@virginia.edu#include "params/AlphaBackdoor.hh" 6011963Sar4jc@virginia.edu#include "sim/sim_object.hh" 6111963Sar4jc@virginia.edu 6211963Sar4jc@virginia.eduusing namespace std; 6311963Sar4jc@virginia.eduusing namespace AlphaISA; 6411963Sar4jc@virginia.edu 6511963Sar4jc@virginia.eduAlphaBackdoor::AlphaBackdoor(const Params *p) 6611963Sar4jc@virginia.edu : BasicPioDevice(p, sizeof(struct AlphaAccess)), 6711963Sar4jc@virginia.edu disk(p->disk), terminal(p->terminal), 6811963Sar4jc@virginia.edu system(p->system), cpu(p->cpu) 6911963Sar4jc@virginia.edu{ 7011963Sar4jc@virginia.edu alphaAccess = new Access(); 7111963Sar4jc@virginia.edu alphaAccess->last_offset = pioSize - 1; 7211963Sar4jc@virginia.edu 7311963Sar4jc@virginia.edu alphaAccess->version = ALPHA_ACCESS_VERSION; 7411963Sar4jc@virginia.edu alphaAccess->diskUnit = 1; 7511963Sar4jc@virginia.edu 7611963Sar4jc@virginia.edu alphaAccess->diskCount = 0; 7711963Sar4jc@virginia.edu alphaAccess->diskPAddr = 0; 7811963Sar4jc@virginia.edu alphaAccess->diskBlock = 0; 7911963Sar4jc@virginia.edu alphaAccess->diskOperation = 0; 8011963Sar4jc@virginia.edu alphaAccess->outputChar = 0; 8111963Sar4jc@virginia.edu alphaAccess->inputChar = 0; 8211963Sar4jc@virginia.edu std::memset(alphaAccess->cpuStack, 0, sizeof(alphaAccess->cpuStack)); 8311963Sar4jc@virginia.edu 8411963Sar4jc@virginia.edu} 8511963Sar4jc@virginia.edu 8611723Sar4jc@virginia.eduvoid 8711963Sar4jc@virginia.eduAlphaBackdoor::startup() 8811963Sar4jc@virginia.edu{ 8911723Sar4jc@virginia.edu system->setAlphaAccess(pioAddr); 9011723Sar4jc@virginia.edu alphaAccess->numCPUs = system->numContexts(); 9111723Sar4jc@virginia.edu alphaAccess->kernStart = system->getKernelStart(); 9211723Sar4jc@virginia.edu alphaAccess->kernEnd = system->getKernelEnd(); 9311723Sar4jc@virginia.edu alphaAccess->entryPoint = system->getKernelEntry(); 94 alphaAccess->mem_size = system->memSize(); 95 alphaAccess->cpuClock = cpu->frequency() / 1000000; // In MHz 96 Tsunami *tsunami = dynamic_cast<Tsunami *>(params()->platform); 97 if (!tsunami) 98 fatal("Platform is not Tsunami.\n"); 99 alphaAccess->intrClockFrequency = tsunami->io->frequency(); 100} 101 102Tick 103AlphaBackdoor::read(PacketPtr pkt) 104{ 105 106 /** XXX Do we want to push the addr munging to a bus brige or something? So 107 * the device has it's physical address and then the bridge adds on whatever 108 * machine dependent address swizzle is required? 109 */ 110 111 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 112 113 Addr daddr = pkt->getAddr() - pioAddr; 114 115 pkt->makeAtomicResponse(); 116 117 switch (pkt->getSize()) 118 { 119 case sizeof(uint32_t): 120 switch (daddr) 121 { 122 case offsetof(AlphaAccess, last_offset): 123 pkt->set(alphaAccess->last_offset); 124 break; 125 case offsetof(AlphaAccess, version): 126 pkt->set(alphaAccess->version); 127 break; 128 case offsetof(AlphaAccess, numCPUs): 129 pkt->set(alphaAccess->numCPUs); 130 break; 131 case offsetof(AlphaAccess, intrClockFrequency): 132 pkt->set(alphaAccess->intrClockFrequency); 133 break; 134 default: 135 /* Old console code read in everyting as a 32bit int 136 * we now break that for better error checking. 137 */ 138 pkt->setBadAddress(); 139 } 140 DPRINTF(AlphaBackdoor, "read: offset=%#x val=%#x\n", daddr, 141 pkt->get<uint32_t>()); 142 break; 143 case sizeof(uint64_t): 144 switch (daddr) 145 { 146 case offsetof(AlphaAccess, inputChar): 147 pkt->set(terminal->console_in()); 148 break; 149 case offsetof(AlphaAccess, cpuClock): 150 pkt->set(alphaAccess->cpuClock); 151 break; 152 case offsetof(AlphaAccess, mem_size): 153 pkt->set(alphaAccess->mem_size); 154 break; 155 case offsetof(AlphaAccess, kernStart): 156 pkt->set(alphaAccess->kernStart); 157 break; 158 case offsetof(AlphaAccess, kernEnd): 159 pkt->set(alphaAccess->kernEnd); 160 break; 161 case offsetof(AlphaAccess, entryPoint): 162 pkt->set(alphaAccess->entryPoint); 163 break; 164 case offsetof(AlphaAccess, diskUnit): 165 pkt->set(alphaAccess->diskUnit); 166 break; 167 case offsetof(AlphaAccess, diskCount): 168 pkt->set(alphaAccess->diskCount); 169 break; 170 case offsetof(AlphaAccess, diskPAddr): 171 pkt->set(alphaAccess->diskPAddr); 172 break; 173 case offsetof(AlphaAccess, diskBlock): 174 pkt->set(alphaAccess->diskBlock); 175 break; 176 case offsetof(AlphaAccess, diskOperation): 177 pkt->set(alphaAccess->diskOperation); 178 break; 179 case offsetof(AlphaAccess, outputChar): 180 pkt->set(alphaAccess->outputChar); 181 break; 182 default: 183 int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) / 184 sizeof(alphaAccess->cpuStack[0]); 185 186 if (cpunum >= 0 && cpunum < 64) 187 pkt->set(alphaAccess->cpuStack[cpunum]); 188 else 189 panic("Unknown 64bit access, %#x\n", daddr); 190 } 191 DPRINTF(AlphaBackdoor, "read: offset=%#x val=%#x\n", daddr, 192 pkt->get<uint64_t>()); 193 break; 194 default: 195 pkt->setBadAddress(); 196 } 197 return pioDelay; 198} 199 200Tick 201AlphaBackdoor::write(PacketPtr pkt) 202{ 203 assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 204 Addr daddr = pkt->getAddr() - pioAddr; 205 206 uint64_t val = pkt->get<uint64_t>(); 207 assert(pkt->getSize() == sizeof(uint64_t)); 208 209 switch (daddr) { 210 case offsetof(AlphaAccess, diskUnit): 211 alphaAccess->diskUnit = val; 212 break; 213 214 case offsetof(AlphaAccess, diskCount): 215 alphaAccess->diskCount = val; 216 break; 217 218 case offsetof(AlphaAccess, diskPAddr): 219 alphaAccess->diskPAddr = val; 220 break; 221 222 case offsetof(AlphaAccess, diskBlock): 223 alphaAccess->diskBlock = val; 224 break; 225 226 case offsetof(AlphaAccess, diskOperation): 227 if (val == 0x13) 228 disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock, 229 alphaAccess->diskCount); 230 else 231 panic("Invalid disk operation!"); 232 233 break; 234 235 case offsetof(AlphaAccess, outputChar): 236 terminal->writeData((char)(val & 0xff)); 237 break; 238 239 default: 240 int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) / 241 sizeof(alphaAccess->cpuStack[0]); 242 inform("Launching CPU %d @ %d", cpunum, curTick()); 243 assert(val > 0 && "Must not access primary cpu"); 244 if (cpunum >= 0 && cpunum < 64) 245 alphaAccess->cpuStack[cpunum] = val; 246 else 247 panic("Unknown 64bit access, %#x\n", daddr); 248 } 249 250 pkt->makeAtomicResponse(); 251 252 return pioDelay; 253} 254 255void 256AlphaBackdoor::Access::serialize(CheckpointOut &cp) const 257{ 258 SERIALIZE_SCALAR(last_offset); 259 SERIALIZE_SCALAR(version); 260 SERIALIZE_SCALAR(numCPUs); 261 SERIALIZE_SCALAR(mem_size); 262 SERIALIZE_SCALAR(cpuClock); 263 SERIALIZE_SCALAR(intrClockFrequency); 264 SERIALIZE_SCALAR(kernStart); 265 SERIALIZE_SCALAR(kernEnd); 266 SERIALIZE_SCALAR(entryPoint); 267 SERIALIZE_SCALAR(diskUnit); 268 SERIALIZE_SCALAR(diskCount); 269 SERIALIZE_SCALAR(diskPAddr); 270 SERIALIZE_SCALAR(diskBlock); 271 SERIALIZE_SCALAR(diskOperation); 272 SERIALIZE_SCALAR(outputChar); 273 SERIALIZE_SCALAR(inputChar); 274 SERIALIZE_ARRAY(cpuStack,64); 275} 276 277void 278AlphaBackdoor::Access::unserialize(CheckpointIn &cp) 279{ 280 UNSERIALIZE_SCALAR(last_offset); 281 UNSERIALIZE_SCALAR(version); 282 UNSERIALIZE_SCALAR(numCPUs); 283 UNSERIALIZE_SCALAR(mem_size); 284 UNSERIALIZE_SCALAR(cpuClock); 285 UNSERIALIZE_SCALAR(intrClockFrequency); 286 UNSERIALIZE_SCALAR(kernStart); 287 UNSERIALIZE_SCALAR(kernEnd); 288 UNSERIALIZE_SCALAR(entryPoint); 289 UNSERIALIZE_SCALAR(diskUnit); 290 UNSERIALIZE_SCALAR(diskCount); 291 UNSERIALIZE_SCALAR(diskPAddr); 292 UNSERIALIZE_SCALAR(diskBlock); 293 UNSERIALIZE_SCALAR(diskOperation); 294 UNSERIALIZE_SCALAR(outputChar); 295 UNSERIALIZE_SCALAR(inputChar); 296 UNSERIALIZE_ARRAY(cpuStack, 64); 297} 298 299void 300AlphaBackdoor::serialize(CheckpointOut &cp) const 301{ 302 alphaAccess->serialize(cp); 303} 304 305void 306AlphaBackdoor::unserialize(CheckpointIn &cp) 307{ 308 alphaAccess->unserialize(cp); 309} 310 311AlphaBackdoor * 312AlphaBackdoorParams::create() 313{ 314 return new AlphaBackdoor(this); 315} 316