backdoor.cc revision 11264
12SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Nathan Binkert 292665SN/A * Ali Saidi 302665SN/A * Steve Reinhardt 312665SN/A * Erik Hallnor 322SN/A */ 332SN/A 341722SN/A/** @file 355480Snate@binkert.org * Alpha Console Backdoor Definition 362SN/A */ 372SN/A 38146SN/A#include <cstddef> 392SN/A#include <string> 402SN/A 412158SN/A#include "arch/alpha/system.hh" 42146SN/A#include "base/inifile.hh" 431805SN/A#include "base/str.hh" 44146SN/A#include "base/trace.hh" 451717SN/A#include "cpu/base.hh" 462680SN/A#include "cpu/thread_context.hh" 478232Snate@binkert.org#include "debug/AlphaBackdoor.hh" 485480Snate@binkert.org#include "dev/alpha/backdoor.hh" 498741Sgblack@eecs.umich.edu#include "dev/alpha/tsunami.hh" 508741Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_cchip.hh" 518741Sgblack@eecs.umich.edu#include "dev/alpha/tsunami_io.hh" 522521SN/A#include "dev/platform.hh" 5311264Sandreas.sandberg@arm.com#include "dev/storage/simple_disk.hh" 545478SN/A#include "dev/terminal.hh" 553348SN/A#include "mem/packet.hh" 563348SN/A#include "mem/packet_access.hh" 572521SN/A#include "mem/physical.hh" 585480Snate@binkert.org#include "params/AlphaBackdoor.hh" 591805SN/A#include "sim/sim_object.hh" 602SN/A 612SN/Ausing namespace std; 622107SN/Ausing namespace AlphaISA; 632SN/A 645480Snate@binkert.orgAlphaBackdoor::AlphaBackdoor(const Params *p) 659808Sstever@gmail.com : BasicPioDevice(p, sizeof(struct AlphaAccess)), 669808Sstever@gmail.com disk(p->disk), terminal(p->terminal), 678806Sgblack@eecs.umich.edu system(p->system), cpu(p->cpu) 682SN/A{ 692521SN/A alphaAccess = new Access(); 702521SN/A alphaAccess->last_offset = pioSize - 1; 712SN/A 722SN/A alphaAccess->version = ALPHA_ACCESS_VERSION; 732SN/A alphaAccess->diskUnit = 1; 74926SN/A 75926SN/A alphaAccess->diskCount = 0; 76926SN/A alphaAccess->diskPAddr = 0; 77926SN/A alphaAccess->diskBlock = 0; 78926SN/A alphaAccess->diskOperation = 0; 79926SN/A alphaAccess->outputChar = 0; 80926SN/A alphaAccess->inputChar = 0; 814395SN/A std::memset(alphaAccess->cpuStack, 0, sizeof(alphaAccess->cpuStack)); 821805SN/A 832SN/A} 842SN/A 851634SN/Avoid 865480Snate@binkert.orgAlphaBackdoor::startup() 871634SN/A{ 882549SN/A system->setAlphaAccess(pioAddr); 895714Shsul@eecs.umich.edu alphaAccess->numCPUs = system->numContexts(); 901634SN/A alphaAccess->kernStart = system->getKernelStart(); 911634SN/A alphaAccess->kernEnd = system->getKernelEnd(); 921634SN/A alphaAccess->entryPoint = system->getKernelEntry(); 938931Sandreas.hansson@arm.com alphaAccess->mem_size = system->memSize(); 941634SN/A alphaAccess->cpuClock = cpu->frequency() / 1000000; // In MHz 958741Sgblack@eecs.umich.edu Tsunami *tsunami = dynamic_cast<Tsunami *>(params()->platform); 968806Sgblack@eecs.umich.edu if (!tsunami) 978806Sgblack@eecs.umich.edu fatal("Platform is not Tsunami.\n"); 988741Sgblack@eecs.umich.edu alphaAccess->intrClockFrequency = tsunami->io->frequency(); 991634SN/A} 1001634SN/A 1012512SN/ATick 1025480Snate@binkert.orgAlphaBackdoor::read(PacketPtr pkt) 1032SN/A{ 1042SN/A 1052512SN/A /** XXX Do we want to push the addr munging to a bus brige or something? So 1062512SN/A * the device has it's physical address and then the bridge adds on whatever 1072512SN/A * machine dependent address swizzle is required? 1082512SN/A */ 109540SN/A 1102641SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 1112522SN/A 1122641SN/A Addr daddr = pkt->getAddr() - pioAddr; 1132512SN/A 1144986SN/A pkt->makeAtomicResponse(); 1152521SN/A 1162641SN/A switch (pkt->getSize()) 117873SN/A { 118873SN/A case sizeof(uint32_t): 119873SN/A switch (daddr) 120873SN/A { 121873SN/A case offsetof(AlphaAccess, last_offset): 1222630SN/A pkt->set(alphaAccess->last_offset); 123873SN/A break; 124873SN/A case offsetof(AlphaAccess, version): 1252630SN/A pkt->set(alphaAccess->version); 126873SN/A break; 127873SN/A case offsetof(AlphaAccess, numCPUs): 1282630SN/A pkt->set(alphaAccess->numCPUs); 129873SN/A break; 130873SN/A case offsetof(AlphaAccess, intrClockFrequency): 1312630SN/A pkt->set(alphaAccess->intrClockFrequency); 132873SN/A break; 133873SN/A default: 1342512SN/A /* Old console code read in everyting as a 32bit int 1352512SN/A * we now break that for better error checking. 1362512SN/A */ 1374870SN/A pkt->setBadAddress(); 138873SN/A } 1395480Snate@binkert.org DPRINTF(AlphaBackdoor, "read: offset=%#x val=%#x\n", daddr, 1402630SN/A pkt->get<uint32_t>()); 141873SN/A break; 142873SN/A case sizeof(uint64_t): 143873SN/A switch (daddr) 144873SN/A { 145873SN/A case offsetof(AlphaAccess, inputChar): 1465478SN/A pkt->set(terminal->console_in()); 147873SN/A break; 148873SN/A case offsetof(AlphaAccess, cpuClock): 1492630SN/A pkt->set(alphaAccess->cpuClock); 150873SN/A break; 151873SN/A case offsetof(AlphaAccess, mem_size): 1522630SN/A pkt->set(alphaAccess->mem_size); 153873SN/A break; 154873SN/A case offsetof(AlphaAccess, kernStart): 1552630SN/A pkt->set(alphaAccess->kernStart); 156873SN/A break; 157873SN/A case offsetof(AlphaAccess, kernEnd): 1582630SN/A pkt->set(alphaAccess->kernEnd); 159873SN/A break; 160873SN/A case offsetof(AlphaAccess, entryPoint): 1612630SN/A pkt->set(alphaAccess->entryPoint); 162873SN/A break; 163873SN/A case offsetof(AlphaAccess, diskUnit): 1642630SN/A pkt->set(alphaAccess->diskUnit); 165873SN/A break; 166873SN/A case offsetof(AlphaAccess, diskCount): 1672630SN/A pkt->set(alphaAccess->diskCount); 168873SN/A break; 169873SN/A case offsetof(AlphaAccess, diskPAddr): 1702630SN/A pkt->set(alphaAccess->diskPAddr); 171873SN/A break; 172873SN/A case offsetof(AlphaAccess, diskBlock): 1732630SN/A pkt->set(alphaAccess->diskBlock); 174873SN/A break; 175873SN/A case offsetof(AlphaAccess, diskOperation): 1762630SN/A pkt->set(alphaAccess->diskOperation); 177873SN/A break; 178873SN/A case offsetof(AlphaAccess, outputChar): 1792630SN/A pkt->set(alphaAccess->outputChar); 180873SN/A break; 181873SN/A default: 1822114SN/A int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) / 1832114SN/A sizeof(alphaAccess->cpuStack[0]); 1842114SN/A 1852114SN/A if (cpunum >= 0 && cpunum < 64) 1862630SN/A pkt->set(alphaAccess->cpuStack[cpunum]); 1872114SN/A else 1882114SN/A panic("Unknown 64bit access, %#x\n", daddr); 189873SN/A } 1905480Snate@binkert.org DPRINTF(AlphaBackdoor, "read: offset=%#x val=%#x\n", daddr, 1912630SN/A pkt->get<uint64_t>()); 192873SN/A break; 193873SN/A default: 1944870SN/A pkt->setBadAddress(); 1952SN/A } 1962512SN/A return pioDelay; 1972SN/A} 1982SN/A 1992512SN/ATick 2005480Snate@binkert.orgAlphaBackdoor::write(PacketPtr pkt) 2012SN/A{ 2022641SN/A assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 2032641SN/A Addr daddr = pkt->getAddr() - pioAddr; 204430SN/A 2052630SN/A uint64_t val = pkt->get<uint64_t>(); 2062641SN/A assert(pkt->getSize() == sizeof(uint64_t)); 2072SN/A 208430SN/A switch (daddr) { 209430SN/A case offsetof(AlphaAccess, diskUnit): 2102SN/A alphaAccess->diskUnit = val; 211430SN/A break; 2122SN/A 213430SN/A case offsetof(AlphaAccess, diskCount): 2142SN/A alphaAccess->diskCount = val; 215430SN/A break; 2162SN/A 217430SN/A case offsetof(AlphaAccess, diskPAddr): 2182SN/A alphaAccess->diskPAddr = val; 219430SN/A break; 2202SN/A 221430SN/A case offsetof(AlphaAccess, diskBlock): 2222SN/A alphaAccess->diskBlock = val; 223430SN/A break; 2242SN/A 225430SN/A case offsetof(AlphaAccess, diskOperation): 2262SN/A if (val == 0x13) 2272SN/A disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock, 2282SN/A alphaAccess->diskCount); 2292SN/A else 2302SN/A panic("Invalid disk operation!"); 2312SN/A 232430SN/A break; 2332SN/A 234430SN/A case offsetof(AlphaAccess, outputChar): 2355478SN/A terminal->out((char)(val & 0xff)); 236430SN/A break; 2372SN/A 238430SN/A default: 2392114SN/A int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) / 2402114SN/A sizeof(alphaAccess->cpuStack[0]); 2417823Ssteve.reinhardt@amd.com inform("Launching CPU %d @ %d", cpunum, curTick()); 2422114SN/A assert(val > 0 && "Must not access primary cpu"); 2432114SN/A if (cpunum >= 0 && cpunum < 64) 2442114SN/A alphaAccess->cpuStack[cpunum] = val; 2452114SN/A else 2462114SN/A panic("Unknown 64bit access, %#x\n", daddr); 2472SN/A } 2482SN/A 2494870SN/A pkt->makeAtomicResponse(); 2502SN/A 2512512SN/A return pioDelay; 252545SN/A} 253545SN/A 2542SN/Avoid 25510905Sandreas.sandberg@arm.comAlphaBackdoor::Access::serialize(CheckpointOut &cp) const 2562SN/A{ 257222SN/A SERIALIZE_SCALAR(last_offset); 258222SN/A SERIALIZE_SCALAR(version); 259222SN/A SERIALIZE_SCALAR(numCPUs); 260222SN/A SERIALIZE_SCALAR(mem_size); 261222SN/A SERIALIZE_SCALAR(cpuClock); 262222SN/A SERIALIZE_SCALAR(intrClockFrequency); 263222SN/A SERIALIZE_SCALAR(kernStart); 264222SN/A SERIALIZE_SCALAR(kernEnd); 265222SN/A SERIALIZE_SCALAR(entryPoint); 266222SN/A SERIALIZE_SCALAR(diskUnit); 267222SN/A SERIALIZE_SCALAR(diskCount); 268222SN/A SERIALIZE_SCALAR(diskPAddr); 269222SN/A SERIALIZE_SCALAR(diskBlock); 270222SN/A SERIALIZE_SCALAR(diskOperation); 271222SN/A SERIALIZE_SCALAR(outputChar); 272430SN/A SERIALIZE_SCALAR(inputChar); 2732114SN/A SERIALIZE_ARRAY(cpuStack,64); 2742SN/A} 2752SN/A 2762SN/Avoid 27710905Sandreas.sandberg@arm.comAlphaBackdoor::Access::unserialize(CheckpointIn &cp) 2782SN/A{ 279222SN/A UNSERIALIZE_SCALAR(last_offset); 280222SN/A UNSERIALIZE_SCALAR(version); 281222SN/A UNSERIALIZE_SCALAR(numCPUs); 282222SN/A UNSERIALIZE_SCALAR(mem_size); 283222SN/A UNSERIALIZE_SCALAR(cpuClock); 284222SN/A UNSERIALIZE_SCALAR(intrClockFrequency); 285222SN/A UNSERIALIZE_SCALAR(kernStart); 286222SN/A UNSERIALIZE_SCALAR(kernEnd); 287222SN/A UNSERIALIZE_SCALAR(entryPoint); 288222SN/A UNSERIALIZE_SCALAR(diskUnit); 289222SN/A UNSERIALIZE_SCALAR(diskCount); 290222SN/A UNSERIALIZE_SCALAR(diskPAddr); 291222SN/A UNSERIALIZE_SCALAR(diskBlock); 292222SN/A UNSERIALIZE_SCALAR(diskOperation); 293222SN/A UNSERIALIZE_SCALAR(outputChar); 294430SN/A UNSERIALIZE_SCALAR(inputChar); 2952114SN/A UNSERIALIZE_ARRAY(cpuStack, 64); 296217SN/A} 2972SN/A 298217SN/Avoid 29910905Sandreas.sandberg@arm.comAlphaBackdoor::serialize(CheckpointOut &cp) const 300217SN/A{ 30110905Sandreas.sandberg@arm.com alphaAccess->serialize(cp); 302217SN/A} 303217SN/A 304217SN/Avoid 30510905Sandreas.sandberg@arm.comAlphaBackdoor::unserialize(CheckpointIn &cp) 306217SN/A{ 30710905Sandreas.sandberg@arm.com alphaAccess->unserialize(cp); 3082SN/A} 3092SN/A 3105480Snate@binkert.orgAlphaBackdoor * 3115480Snate@binkert.orgAlphaBackdoorParams::create() 3122SN/A{ 3135480Snate@binkert.org return new AlphaBackdoor(this); 3142SN/A} 315