xref: /gem5/src/cpu/trace/TraceCPU.py

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# Authors: Radhika Jagtap
#          Andreas Hansson
#          Thomas Grass

from m5.params import *
from BaseCPU import BaseCPU

class TraceCPU(BaseCPU):
    """Trace CPU model which replays traces generated in a prior simulation
     using DerivO3CPU or its derived classes. It interfaces with L1 caches.
    """
    type = 'TraceCPU'
    cxx_header = "cpu/trace/trace_cpu.hh"

    @classmethod
    def memory_mode(cls):
        return 'timing'

    @classmethod
    def require_caches(cls):
        return True

    def addPMU(self, pmu = None):
        pass

    @classmethod
    def support_take_over(cls):
        return True

    instTraceFile = Param.String("", "Instruction trace file")
    dataTraceFile = Param.String("", "Data dependency trace file")
    sizeStoreBuffer = Param.Unsigned(16, "Number of entries in the store "\
        "buffer")
    sizeLoadBuffer = Param.Unsigned(16, "Number of entries in the load buffer")
    sizeROB =  Param.Unsigned(40, "Number of entries in the re-order buffer")