thread_context.hh revision 6022
12SN/A/* 22190SN/A * Copyright (c) 2006 The Regents of The University of Michigan 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Kevin Lim 292SN/A */ 302SN/A 312680Sktlim@umich.edu#ifndef __CPU_THREAD_CONTEXT_HH__ 322680Sktlim@umich.edu#define __CPU_THREAD_CONTEXT_HH__ 332SN/A 342972Sgblack@eecs.umich.edu#include "arch/regfile.hh" 353453Sgblack@eecs.umich.edu#include "arch/types.hh" 361858SN/A#include "config/full_system.hh" 372423SN/A#include "mem/request.hh" 382190SN/A#include "sim/faults.hh" 3956SN/A#include "sim/host.hh" 40217SN/A#include "sim/serialize.hh" 412036SN/A#include "sim/byteswap.hh" 422SN/A 432190SN/A// @todo: Figure out a more architecture independent way to obtain the ITB and 442190SN/A// DTB pointers. 453453Sgblack@eecs.umich.edunamespace TheISA 463453Sgblack@eecs.umich.edu{ 476022Sgblack@eecs.umich.edu class TLB; 483453Sgblack@eecs.umich.edu} 492190SN/Aclass BaseCPU; 502313SN/Aclass EndQuiesceEvent; 512235SN/Aclass Event; 522423SN/Aclass TranslatingPort; 532521SN/Aclass FunctionalPort; 542521SN/Aclass VirtualPort; 552190SN/Aclass Process; 562190SN/Aclass System; 573548Sgblack@eecs.umich.edunamespace TheISA { 583548Sgblack@eecs.umich.edu namespace Kernel { 593548Sgblack@eecs.umich.edu class Statistics; 603548Sgblack@eecs.umich.edu }; 612330SN/A}; 622SN/A 632680Sktlim@umich.edu/** 642680Sktlim@umich.edu * ThreadContext is the external interface to all thread state for 652680Sktlim@umich.edu * anything outside of the CPU. It provides all accessor methods to 662680Sktlim@umich.edu * state that might be needed by external objects, ranging from 672680Sktlim@umich.edu * register values to things such as kernel stats. It is an abstract 682680Sktlim@umich.edu * base class; the CPU can create its own ThreadContext by either 692680Sktlim@umich.edu * deriving from it, or using the templated ProxyThreadContext. 702680Sktlim@umich.edu * 712680Sktlim@umich.edu * The ThreadContext is slightly different than the ExecContext. The 722680Sktlim@umich.edu * ThreadContext provides access to an individual thread's state; an 732680Sktlim@umich.edu * ExecContext provides ISA access to the CPU (meaning it is 742682Sktlim@umich.edu * implicitly multithreaded on SMT systems). Additionally the 752680Sktlim@umich.edu * ThreadState is an abstract class that exactly defines the 762680Sktlim@umich.edu * interface; the ExecContext is a more implicit interface that must 772680Sktlim@umich.edu * be implemented so that the ISA can access whatever state it needs. 782680Sktlim@umich.edu */ 792680Sktlim@umich.educlass ThreadContext 802SN/A{ 812107SN/A protected: 822107SN/A typedef TheISA::RegFile RegFile; 832107SN/A typedef TheISA::MachInst MachInst; 842190SN/A typedef TheISA::IntReg IntReg; 852455SN/A typedef TheISA::FloatReg FloatReg; 862455SN/A typedef TheISA::FloatRegBits FloatRegBits; 872107SN/A typedef TheISA::MiscRegFile MiscRegFile; 882159SN/A typedef TheISA::MiscReg MiscReg; 892SN/A public: 90246SN/A enum Status 91246SN/A { 92246SN/A /// Initialized but not running yet. All CPUs start in 93246SN/A /// this state, but most transition to Active on cycle 1. 94246SN/A /// In MP or SMT systems, non-primary contexts will stay 95246SN/A /// in this state until a thread is assigned to them. 96246SN/A Unallocated, 97246SN/A 98246SN/A /// Running. Instructions should be executed only when 99246SN/A /// the context is in this state. 100246SN/A Active, 101246SN/A 102246SN/A /// Temporarily inactive. Entered while waiting for 1032190SN/A /// synchronization, etc. 104246SN/A Suspended, 105246SN/A 106246SN/A /// Permanently shut down. Entered when target executes 107246SN/A /// m5exit pseudo-instruction. When all contexts enter 108246SN/A /// this state, the simulation will terminate. 109246SN/A Halted 110246SN/A }; 1112SN/A 1122680Sktlim@umich.edu virtual ~ThreadContext() { }; 1132423SN/A 1142190SN/A virtual BaseCPU *getCpuPtr() = 0; 115180SN/A 1165712Shsul@eecs.umich.edu virtual int cpuId() = 0; 1172190SN/A 1185715Shsul@eecs.umich.edu virtual int threadId() = 0; 1195715Shsul@eecs.umich.edu 1205715Shsul@eecs.umich.edu virtual void setThreadId(int id) = 0; 1215714Shsul@eecs.umich.edu 1225714Shsul@eecs.umich.edu virtual int contextId() = 0; 1235714Shsul@eecs.umich.edu 1245714Shsul@eecs.umich.edu virtual void setContextId(int id) = 0; 1255714Shsul@eecs.umich.edu 1266022Sgblack@eecs.umich.edu virtual TheISA::TLB *getITBPtr() = 0; 1272190SN/A 1286022Sgblack@eecs.umich.edu virtual TheISA::TLB *getDTBPtr() = 0; 1292521SN/A 1304997Sgblack@eecs.umich.edu virtual System *getSystemPtr() = 0; 1314997Sgblack@eecs.umich.edu 1325803Snate@binkert.org#if FULL_SYSTEM 1333548Sgblack@eecs.umich.edu virtual TheISA::Kernel::Statistics *getKernelStats() = 0; 1342654SN/A 1352521SN/A virtual FunctionalPort *getPhysPort() = 0; 1362521SN/A 1375499Ssaidi@eecs.umich.edu virtual VirtualPort *getVirtPort() = 0; 1383673Srdreslin@umich.edu 1395497Ssaidi@eecs.umich.edu virtual void connectMemPorts(ThreadContext *tc) = 0; 1402190SN/A#else 1412518SN/A virtual TranslatingPort *getMemPort() = 0; 1422518SN/A 1432190SN/A virtual Process *getProcessPtr() = 0; 1442190SN/A#endif 1452190SN/A 1462190SN/A virtual Status status() const = 0; 1472159SN/A 1482235SN/A virtual void setStatus(Status new_status) = 0; 1492103SN/A 150393SN/A /// Set the status to Active. Optional delay indicates number of 151393SN/A /// cycles to wait before beginning execution. 1522190SN/A virtual void activate(int delay = 1) = 0; 153393SN/A 154393SN/A /// Set the status to Suspended. 1555250Sksewell@umich.edu virtual void suspend(int delay = 0) = 0; 156393SN/A 157393SN/A /// Set the status to Unallocated. 1582875Sksewell@umich.edu virtual void deallocate(int delay = 0) = 0; 159393SN/A 160393SN/A /// Set the status to Halted. 1615250Sksewell@umich.edu virtual void halt(int delay = 0) = 0; 1622159SN/A 1632159SN/A#if FULL_SYSTEM 1642190SN/A virtual void dumpFuncProfile() = 0; 1652159SN/A#endif 1662159SN/A 1672680Sktlim@umich.edu virtual void takeOverFrom(ThreadContext *old_context) = 0; 1682159SN/A 1692190SN/A virtual void regStats(const std::string &name) = 0; 1702159SN/A 1712190SN/A virtual void serialize(std::ostream &os) = 0; 1722190SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0; 1732159SN/A 1742235SN/A#if FULL_SYSTEM 1752313SN/A virtual EndQuiesceEvent *getQuiesceEvent() = 0; 1762235SN/A 1772235SN/A // Not necessarily the best location for these... 1782235SN/A // Having an extra function just to read these is obnoxious 1792235SN/A virtual Tick readLastActivate() = 0; 1802235SN/A virtual Tick readLastSuspend() = 0; 1812254SN/A 1822254SN/A virtual void profileClear() = 0; 1832254SN/A virtual void profileSample() = 0; 1842235SN/A#endif 1852235SN/A 1862235SN/A // Also somewhat obnoxious. Really only used for the TLB fault. 1872254SN/A // However, may be quite useful in SPARC. 1882190SN/A virtual TheISA::MachInst getInst() = 0; 1892159SN/A 1902680Sktlim@umich.edu virtual void copyArchRegs(ThreadContext *tc) = 0; 1912159SN/A 1922190SN/A virtual void clearArchRegs() = 0; 1932159SN/A 1942159SN/A // 1952159SN/A // New accessors for new decoder. 1962159SN/A // 1972190SN/A virtual uint64_t readIntReg(int reg_idx) = 0; 1982159SN/A 1992455SN/A virtual FloatReg readFloatReg(int reg_idx, int width) = 0; 2002159SN/A 2012455SN/A virtual FloatReg readFloatReg(int reg_idx) = 0; 2022159SN/A 2032455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0; 2042455SN/A 2052455SN/A virtual FloatRegBits readFloatRegBits(int reg_idx) = 0; 2062159SN/A 2072190SN/A virtual void setIntReg(int reg_idx, uint64_t val) = 0; 2082159SN/A 2092455SN/A virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0; 2102159SN/A 2112455SN/A virtual void setFloatReg(int reg_idx, FloatReg val) = 0; 2122159SN/A 2132455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0; 2142455SN/A 2152455SN/A virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0; 2162159SN/A 2172190SN/A virtual uint64_t readPC() = 0; 2182159SN/A 2192190SN/A virtual void setPC(uint64_t val) = 0; 2202159SN/A 2212190SN/A virtual uint64_t readNextPC() = 0; 2222159SN/A 2232190SN/A virtual void setNextPC(uint64_t val) = 0; 2242159SN/A 2252447SN/A virtual uint64_t readNextNPC() = 0; 2262447SN/A 2272447SN/A virtual void setNextNPC(uint64_t val) = 0; 2282447SN/A 2295260Sksewell@umich.edu virtual uint64_t readMicroPC() = 0; 2305260Sksewell@umich.edu 2315260Sksewell@umich.edu virtual void setMicroPC(uint64_t val) = 0; 2325260Sksewell@umich.edu 2335260Sksewell@umich.edu virtual uint64_t readNextMicroPC() = 0; 2345260Sksewell@umich.edu 2355260Sksewell@umich.edu virtual void setNextMicroPC(uint64_t val) = 0; 2365260Sksewell@umich.edu 2374172Ssaidi@eecs.umich.edu virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; 2384172Ssaidi@eecs.umich.edu 2392190SN/A virtual MiscReg readMiscReg(int misc_reg) = 0; 2402159SN/A 2414172Ssaidi@eecs.umich.edu virtual void setMiscRegNoEffect(int misc_reg, const MiscReg &val) = 0; 2422190SN/A 2433468Sgblack@eecs.umich.edu virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0; 2442190SN/A 2454661Sksewell@umich.edu virtual uint64_t readRegOtherThread(int misc_reg, unsigned tid) { return 0; } 2464661Sksewell@umich.edu 2474661Sksewell@umich.edu virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid) { }; 2484661Sksewell@umich.edu 2492235SN/A // Also not necessarily the best location for these two. Hopefully will go 2502235SN/A // away once we decide upon where st cond failures goes. 2512190SN/A virtual unsigned readStCondFailures() = 0; 2522190SN/A 2532190SN/A virtual void setStCondFailures(unsigned sc_failures) = 0; 2542159SN/A 2552235SN/A // Only really makes sense for old CPU model. Still could be useful though. 2562190SN/A virtual bool misspeculating() = 0; 2572190SN/A 2582159SN/A#if !FULL_SYSTEM 2592235SN/A // Same with st cond failures. 2602190SN/A virtual Counter readFuncExeInst() = 0; 2612834Sksewell@umich.edu 2624111Sgblack@eecs.umich.edu virtual void syscall(int64_t callnum) = 0; 2634111Sgblack@eecs.umich.edu 2642834Sksewell@umich.edu // This function exits the thread context in the CPU and returns 2652834Sksewell@umich.edu // 1 if the CPU has no more active threads (meaning it's OK to exit); 2662834Sksewell@umich.edu // Used in syscall-emulation mode when a thread calls the exit syscall. 2672834Sksewell@umich.edu virtual int exit() { return 1; }; 2682159SN/A#endif 2692525SN/A 2705217Ssaidi@eecs.umich.edu /** function to compare two thread contexts (for debugging) */ 2715217Ssaidi@eecs.umich.edu static void compare(ThreadContext *one, ThreadContext *two); 2722159SN/A}; 2732159SN/A 2742682Sktlim@umich.edu/** 2752682Sktlim@umich.edu * ProxyThreadContext class that provides a way to implement a 2762682Sktlim@umich.edu * ThreadContext without having to derive from it. ThreadContext is an 2772682Sktlim@umich.edu * abstract class, so anything that derives from it and uses its 2782682Sktlim@umich.edu * interface will pay the overhead of virtual function calls. This 2792682Sktlim@umich.edu * class is created to enable a user-defined Thread object to be used 2802682Sktlim@umich.edu * wherever ThreadContexts are used, without paying the overhead of 2812682Sktlim@umich.edu * virtual function calls when it is used by itself. See 2822682Sktlim@umich.edu * simple_thread.hh for an example of this. 2832682Sktlim@umich.edu */ 2842680Sktlim@umich.edutemplate <class TC> 2852680Sktlim@umich.educlass ProxyThreadContext : public ThreadContext 2862190SN/A{ 2872190SN/A public: 2882680Sktlim@umich.edu ProxyThreadContext(TC *actual_tc) 2892680Sktlim@umich.edu { actualTC = actual_tc; } 2902159SN/A 2912190SN/A private: 2922680Sktlim@umich.edu TC *actualTC; 2932SN/A 2942SN/A public: 2952SN/A 2962680Sktlim@umich.edu BaseCPU *getCpuPtr() { return actualTC->getCpuPtr(); } 2972SN/A 2985712Shsul@eecs.umich.edu int cpuId() { return actualTC->cpuId(); } 2992SN/A 3005715Shsul@eecs.umich.edu int threadId() { return actualTC->threadId(); } 3015715Shsul@eecs.umich.edu 3025715Shsul@eecs.umich.edu void setThreadId(int id) { return actualTC->setThreadId(id); } 3035714Shsul@eecs.umich.edu 3045714Shsul@eecs.umich.edu int contextId() { return actualTC->contextId(); } 3055714Shsul@eecs.umich.edu 3065714Shsul@eecs.umich.edu void setContextId(int id) { actualTC->setContextId(id); } 3075714Shsul@eecs.umich.edu 3086022Sgblack@eecs.umich.edu TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); } 3091917SN/A 3106022Sgblack@eecs.umich.edu TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); } 3112521SN/A 3124997Sgblack@eecs.umich.edu System *getSystemPtr() { return actualTC->getSystemPtr(); } 3134997Sgblack@eecs.umich.edu 3145803Snate@binkert.org#if FULL_SYSTEM 3153548Sgblack@eecs.umich.edu TheISA::Kernel::Statistics *getKernelStats() 3163548Sgblack@eecs.umich.edu { return actualTC->getKernelStats(); } 3172654SN/A 3182680Sktlim@umich.edu FunctionalPort *getPhysPort() { return actualTC->getPhysPort(); } 3192521SN/A 3205499Ssaidi@eecs.umich.edu VirtualPort *getVirtPort() { return actualTC->getVirtPort(); } 3213673Srdreslin@umich.edu 3225497Ssaidi@eecs.umich.edu void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); } 3232SN/A#else 3242680Sktlim@umich.edu TranslatingPort *getMemPort() { return actualTC->getMemPort(); } 3252518SN/A 3262680Sktlim@umich.edu Process *getProcessPtr() { return actualTC->getProcessPtr(); } 3272SN/A#endif 3282SN/A 3292680Sktlim@umich.edu Status status() const { return actualTC->status(); } 330595SN/A 3312680Sktlim@umich.edu void setStatus(Status new_status) { actualTC->setStatus(new_status); } 3322SN/A 3332190SN/A /// Set the status to Active. Optional delay indicates number of 3342190SN/A /// cycles to wait before beginning execution. 3352680Sktlim@umich.edu void activate(int delay = 1) { actualTC->activate(delay); } 3362SN/A 3372190SN/A /// Set the status to Suspended. 3385250Sksewell@umich.edu void suspend(int delay = 0) { actualTC->suspend(); } 3392SN/A 3402190SN/A /// Set the status to Unallocated. 3412875Sksewell@umich.edu void deallocate(int delay = 0) { actualTC->deallocate(); } 3422SN/A 3432190SN/A /// Set the status to Halted. 3445250Sksewell@umich.edu void halt(int delay = 0) { actualTC->halt(); } 345217SN/A 3461858SN/A#if FULL_SYSTEM 3472680Sktlim@umich.edu void dumpFuncProfile() { actualTC->dumpFuncProfile(); } 3482190SN/A#endif 3492190SN/A 3502680Sktlim@umich.edu void takeOverFrom(ThreadContext *oldContext) 3512680Sktlim@umich.edu { actualTC->takeOverFrom(oldContext); } 3522190SN/A 3532680Sktlim@umich.edu void regStats(const std::string &name) { actualTC->regStats(name); } 3542190SN/A 3552680Sktlim@umich.edu void serialize(std::ostream &os) { actualTC->serialize(os); } 3562190SN/A void unserialize(Checkpoint *cp, const std::string §ion) 3572680Sktlim@umich.edu { actualTC->unserialize(cp, section); } 3582190SN/A 3592235SN/A#if FULL_SYSTEM 3602680Sktlim@umich.edu EndQuiesceEvent *getQuiesceEvent() { return actualTC->getQuiesceEvent(); } 3612235SN/A 3622680Sktlim@umich.edu Tick readLastActivate() { return actualTC->readLastActivate(); } 3632680Sktlim@umich.edu Tick readLastSuspend() { return actualTC->readLastSuspend(); } 3642254SN/A 3652680Sktlim@umich.edu void profileClear() { return actualTC->profileClear(); } 3662680Sktlim@umich.edu void profileSample() { return actualTC->profileSample(); } 3672235SN/A#endif 3682190SN/A // @todo: Do I need this? 3692680Sktlim@umich.edu MachInst getInst() { return actualTC->getInst(); } 3702SN/A 3712190SN/A // @todo: Do I need this? 3722680Sktlim@umich.edu void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); } 3732SN/A 3742680Sktlim@umich.edu void clearArchRegs() { actualTC->clearArchRegs(); } 375716SN/A 3762SN/A // 3772SN/A // New accessors for new decoder. 3782SN/A // 3792SN/A uint64_t readIntReg(int reg_idx) 3802680Sktlim@umich.edu { return actualTC->readIntReg(reg_idx); } 3812SN/A 3822455SN/A FloatReg readFloatReg(int reg_idx, int width) 3832680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx, width); } 3842SN/A 3852455SN/A FloatReg readFloatReg(int reg_idx) 3862680Sktlim@umich.edu { return actualTC->readFloatReg(reg_idx); } 3872SN/A 3882455SN/A FloatRegBits readFloatRegBits(int reg_idx, int width) 3892680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx, width); } 3902455SN/A 3912455SN/A FloatRegBits readFloatRegBits(int reg_idx) 3922680Sktlim@umich.edu { return actualTC->readFloatRegBits(reg_idx); } 3932SN/A 3942SN/A void setIntReg(int reg_idx, uint64_t val) 3952680Sktlim@umich.edu { actualTC->setIntReg(reg_idx, val); } 3962SN/A 3972455SN/A void setFloatReg(int reg_idx, FloatReg val, int width) 3982680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val, width); } 3992SN/A 4002455SN/A void setFloatReg(int reg_idx, FloatReg val) 4012680Sktlim@umich.edu { actualTC->setFloatReg(reg_idx, val); } 4022SN/A 4032455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val, int width) 4042680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val, width); } 4052455SN/A 4062455SN/A void setFloatRegBits(int reg_idx, FloatRegBits val) 4072680Sktlim@umich.edu { actualTC->setFloatRegBits(reg_idx, val); } 4082SN/A 4092680Sktlim@umich.edu uint64_t readPC() { return actualTC->readPC(); } 4102SN/A 4112680Sktlim@umich.edu void setPC(uint64_t val) { actualTC->setPC(val); } 4122206SN/A 4132680Sktlim@umich.edu uint64_t readNextPC() { return actualTC->readNextPC(); } 4142252SN/A 4152680Sktlim@umich.edu void setNextPC(uint64_t val) { actualTC->setNextPC(val); } 4162SN/A 4172680Sktlim@umich.edu uint64_t readNextNPC() { return actualTC->readNextNPC(); } 4182447SN/A 4192680Sktlim@umich.edu void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } 4202447SN/A 4215260Sksewell@umich.edu uint64_t readMicroPC() { return actualTC->readMicroPC(); } 4225260Sksewell@umich.edu 4235260Sksewell@umich.edu void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); } 4245260Sksewell@umich.edu 4255260Sksewell@umich.edu uint64_t readNextMicroPC() { return actualTC->readMicroPC(); } 4265260Sksewell@umich.edu 4275592Sgblack@eecs.umich.edu void setNextMicroPC(uint64_t val) { actualTC->setNextMicroPC(val); } 4285260Sksewell@umich.edu 4294172Ssaidi@eecs.umich.edu MiscReg readMiscRegNoEffect(int misc_reg) 4304172Ssaidi@eecs.umich.edu { return actualTC->readMiscRegNoEffect(misc_reg); } 4314172Ssaidi@eecs.umich.edu 4322159SN/A MiscReg readMiscReg(int misc_reg) 4332680Sktlim@umich.edu { return actualTC->readMiscReg(misc_reg); } 4342SN/A 4354172Ssaidi@eecs.umich.edu void setMiscRegNoEffect(int misc_reg, const MiscReg &val) 4364172Ssaidi@eecs.umich.edu { return actualTC->setMiscRegNoEffect(misc_reg, val); } 4372SN/A 4383468Sgblack@eecs.umich.edu void setMiscReg(int misc_reg, const MiscReg &val) 4392680Sktlim@umich.edu { return actualTC->setMiscReg(misc_reg, val); } 4402SN/A 4412190SN/A unsigned readStCondFailures() 4422680Sktlim@umich.edu { return actualTC->readStCondFailures(); } 4432190SN/A 4442190SN/A void setStCondFailures(unsigned sc_failures) 4452680Sktlim@umich.edu { actualTC->setStCondFailures(sc_failures); } 4462SN/A 4472190SN/A // @todo: Fix this! 4482680Sktlim@umich.edu bool misspeculating() { return actualTC->misspeculating(); } 4492190SN/A 4501858SN/A#if !FULL_SYSTEM 4514111Sgblack@eecs.umich.edu void syscall(int64_t callnum) 4524111Sgblack@eecs.umich.edu { actualTC->syscall(callnum); } 4534111Sgblack@eecs.umich.edu 4542680Sktlim@umich.edu Counter readFuncExeInst() { return actualTC->readFuncExeInst(); } 4552SN/A#endif 4562SN/A}; 4572SN/A 4582190SN/A#endif 459